netlistdb/
lib.rs

1//! A flattened gate-level circuit netlist database.
2
3use std::collections::HashMap;
4use std::sync::Arc;
5use std::collections::HashSet;
6use zeroable::Zeroable;
7use sverilogparse::*;
8use arcstr::{ArcStr, Substr};
9use ulib::{ UVec, Device, UniversalCopy };
10
11/// types of directions: input or output.
12/// 
13/// note: inout is not supported yet.
14/// **should be identical to `csrc/lib.h`**.
15#[derive(Zeroable, Debug, PartialEq, Eq, Clone, UniversalCopy)]
16#[repr(u8)]
17pub enum Direction {
18    /// input
19    I = 0,
20    /// output
21    O = 1,
22    /// unknown (unassigned)
23    Unknown = 2
24}
25
26mod csr;
27pub use csr::VecCSR;
28
29mod hier_name;
30pub use hier_name::{ HierName, GeneralHierName, GeneralPinName, RefPinName };
31
32#[derive(Debug, Copy, Clone, PartialEq, Eq)]
33enum LogicPinType {
34    TopPort,
35    Net,
36    LeafCellPin,
37    Others
38}
39
40impl LogicPinType {
41    #[inline]
42    pub fn is_pin(self) -> bool {
43        use LogicPinType::*;
44        if let TopPort | LeafCellPin = self { true } else { false }
45    }
46
47    #[inline]
48    pub fn is_net(self) -> bool {
49        use LogicPinType::*;
50        if let TopPort | Net = self { true } else { false }
51    }
52}
53
54/// The netlist storage.
55/// 
56/// The public members are all READ-ONLY outside. Please modify
57/// them through the ECO commands that will be available
58/// in the future.
59#[readonly::make]
60#[derive(Debug)]
61pub struct NetlistDB {
62    /// top-level design name.
63    pub name: Substr,
64    /// number of cells/nodes/instances in the netlist.
65    ///
66    /// This is always greater than 1, as the 0th cell is always
67    /// the top-level macro.
68    pub num_cells: usize,
69    /// number of logical pins.
70    /// 
71    /// A logical pin is not necessarily a pin. It might
72    /// be the I/O port of non-leaf modules, or the result
73    /// of an assign operation.
74    pub num_logic_pins: usize,
75    /// number of pins.
76    pub num_pins: usize,
77    /// number of nets/wires.
78    pub num_nets: usize,
79
80    /// Cell name to index.
81    ///
82    /// The top-level macro is always the 0th cell, which has a
83    /// special name of empty string.
84    /// Also, the hierarchical non-leaf cells do NOT reside in here,
85    /// yet -- they are to-be-added in the future.
86    /// This map only contains leaf cells.
87    pub cellname2id: HashMap<HierName, usize>,
88    /// Logical pin name tuple (cell hier name, macro pin type, vec idx) to logical pin index.
89    ///
90    /// Logic pin names are always unique without ambiguity.
91    /// The case of logic pins include:
92    /// 1. net wires  (yes, nets are also ``logic pins''.)
93    /// 2. I/O ports of top module and submodules
94    /// 3. pins of leaf cells.
95    logicpinname2id: HashMap<(HierName, Substr, Option<isize>), usize>,
96    /// Pin name tuple (cell hier name, macro pin type, vec idx) to index.
97    /// 
98    /// Pin names are always unique without ambiguity.
99    /// For top-level named port connections, only the port names are
100    /// created as valid pin names. The I/O definition can be referred
101    /// in logicpinname2id (private member).
102    pub pinname2id: HashMap<(HierName, Substr, Option<isize>), usize>,
103    /// Net name tuple (net hier name, vec idx) to index.
104    ///
105    /// Multiple nets can be mapped to one single
106    /// index, due to connected nets across hierarchy boundaries.
107    pub netname2id: HashMap<(HierName, Substr, Option<isize>), usize>,
108
109    /// Cell index to macro name.
110    pub celltypes: Vec<Substr>,
111    /// Cell index to name (hierarchical).
112    ///
113    /// This information actually contains the tree structure that
114    /// might be useful later when we implement verilog writer.
115    pub cellnames: Vec<HierName>,
116    /// Logic pin classes.
117    logicpintypes: Vec<LogicPinType>,
118    /// Logic pin index to name.
119    logicpinnames: Vec<(HierName, Substr, Option<isize>)>,
120    /// Pin index to corresponding logic pin index.
121    pinid2logicpinid: Vec<usize>,
122    /// Pin index to cell hier, macro pin name, and pin index.
123    pub pinnames: Vec<(HierName, Substr, Option<isize>)>,
124
125    /// Pin to parent cell.
126    pub pin2cell: UVec<usize>,
127    /// Pin to parent net.
128    pub pin2net: UVec<usize>,
129    /// Cell CSR.
130    pub cell2pin: VecCSR,
131    /// Net CSR.
132    ///
133    /// **Caveat**: After assigning directions, it is guaranteed that
134    /// the net root would be the first in net CSR.
135    /// Before such assignment, the order is not determined.
136    pub net2pin: VecCSR,
137
138    /// Pin direction.
139    pub pindirect: UVec<Direction>,
140
141    /// Constant zero net index.
142    pub net_zero: Option<usize>,
143    /// Constant one net index.
144    pub net_one: Option<usize>
145}
146
147mod utils;
148use utils::*;
149
150mod disjoint_set;
151use disjoint_set::*;
152
153mod builder;
154pub use builder::{DirectionProvider, NoDirection};
netlistdb/lib.rs

netlistdb/
lib.rs
