nescore/
common.rs

1//
2// common.rs
3//
4// @author Natesh Narain <nnaraindev@gmail.com>
5// @date Nov 21 2019
6//
7use std::rc::Rc;
8use std::cell::RefCell;
9
10#[macro_export]
11macro_rules! kb {
12    ($x:expr) => {
13        $x * 1024
14    };
15}
16
17/// Interrupt
18#[derive(Copy, Clone, PartialEq, Debug)]
19pub enum Interrupt {
20    Nmi,
21    Irq,
22}
23
24/// Access a memory mapped component
25pub trait IoAccess {
26    #[allow(unused)]
27    fn read_byte(&self, addr: u16) -> u8 { 0 }
28    #[allow(unused)]
29    fn write_byte(&mut self, addr: u16, data: u8) {}
30    #[allow(unused)]
31    fn raise_interrupt(&mut self, interrupt_type: Interrupt){}
32}
33
34pub type IoAccessRef = Rc<RefCell<dyn IoAccess>>;
35
36/// A clockable component. Optionally, returns a value for every tick
37pub trait Clockable<T=()> {
38    fn tick(&mut self) -> T;
39}
40
41pub trait Register<T> {
42    fn new(value: T) -> Self
43    where Self: Default {
44        let mut r = Self::default();
45        r.load(value);
46        r
47    }
48    #[allow(unused)]
49    fn load(&mut self, value: T){}
50    fn value(&self) -> T;
51}