n32g4/n32g455/tim2/
ctrl2.rs

1///Register `CTRL2` reader
2pub type R = crate::R<Ctrl2Spec>;
3///Register `CTRL2` writer
4pub type W = crate::W<Ctrl2Spec>;
5///Field `CCPCTL` reader - CCPCTL
6pub type CcpctlR = crate::BitReader;
7///Field `CCPCTL` writer - CCPCTL
8pub type CcpctlW<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `CCUSEL` reader - CCUSEL
10pub type CcuselR = crate::BitReader;
11///Field `CCUSEL` writer - CCUSEL
12pub type CcuselW<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `CCDSEL` reader - CCDSEL
14pub type CcdselR = crate::BitReader;
15///Field `CCDSEL` writer - CCDSEL
16pub type CcdselW<'a, REG> = crate::BitWriter<'a, REG>;
17///MMSEL
18///
19///Value on reset: 0
20#[derive(Clone, Copy, Debug, PartialEq, Eq)]
21#[repr(u8)]
22pub enum Mmsel {
23    ///0: Use UPG bit from SWEVG register
24    Reset = 0,
25    ///1: Use CEN bit from CTL0 register
26    Enable = 1,
27    ///2: Use the update event
28    Update = 2,
29    ///3: The trigger output send a positive pulse when a capture or a compare match occurred in channel 0
30    CaptureComparePulse = 3,
31    ///4: O0CPRE signal is used as trigger output
32    CompareO0c = 4,
33    ///5: O1CPRE signal is used as trigger output
34    CompareO1c = 5,
35    ///6: O2CPRE signal is used as trigger output
36    CompareO2c = 6,
37    ///7: O3CPRE signal is used as trigger output
38    CompareO3c = 7,
39}
40impl From<Mmsel> for u8 {
41    #[inline(always)]
42    fn from(variant: Mmsel) -> Self {
43        variant as _
44    }
45}
46impl crate::FieldSpec for Mmsel {
47    type Ux = u8;
48}
49impl crate::IsEnum for Mmsel {}
50///Field `MMSEL` reader - MMSEL
51pub type MmselR = crate::FieldReader<Mmsel>;
52impl MmselR {
53    ///Get enumerated values variant
54    #[inline(always)]
55    pub const fn variant(&self) -> Mmsel {
56        match self.bits {
57            0 => Mmsel::Reset,
58            1 => Mmsel::Enable,
59            2 => Mmsel::Update,
60            3 => Mmsel::CaptureComparePulse,
61            4 => Mmsel::CompareO0c,
62            5 => Mmsel::CompareO1c,
63            6 => Mmsel::CompareO2c,
64            7 => Mmsel::CompareO3c,
65            _ => unreachable!(),
66        }
67    }
68    ///Use UPG bit from SWEVG register
69    #[inline(always)]
70    pub fn is_reset(&self) -> bool {
71        *self == Mmsel::Reset
72    }
73    ///Use CEN bit from CTL0 register
74    #[inline(always)]
75    pub fn is_enable(&self) -> bool {
76        *self == Mmsel::Enable
77    }
78    ///Use the update event
79    #[inline(always)]
80    pub fn is_update(&self) -> bool {
81        *self == Mmsel::Update
82    }
83    ///The trigger output send a positive pulse when a capture or a compare match occurred in channel 0
84    #[inline(always)]
85    pub fn is_capture_compare_pulse(&self) -> bool {
86        *self == Mmsel::CaptureComparePulse
87    }
88    ///O0CPRE signal is used as trigger output
89    #[inline(always)]
90    pub fn is_compare_o0c(&self) -> bool {
91        *self == Mmsel::CompareO0c
92    }
93    ///O1CPRE signal is used as trigger output
94    #[inline(always)]
95    pub fn is_compare_o1c(&self) -> bool {
96        *self == Mmsel::CompareO1c
97    }
98    ///O2CPRE signal is used as trigger output
99    #[inline(always)]
100    pub fn is_compare_o2c(&self) -> bool {
101        *self == Mmsel::CompareO2c
102    }
103    ///O3CPRE signal is used as trigger output
104    #[inline(always)]
105    pub fn is_compare_o3c(&self) -> bool {
106        *self == Mmsel::CompareO3c
107    }
108}
109///Field `MMSEL` writer - MMSEL
110pub type MmselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mmsel, crate::Safe>;
111impl<'a, REG> MmselW<'a, REG>
112where
113    REG: crate::Writable + crate::RegisterSpec,
114    REG::Ux: From<u8>,
115{
116    ///Use UPG bit from SWEVG register
117    #[inline(always)]
118    pub fn reset(self) -> &'a mut crate::W<REG> {
119        self.variant(Mmsel::Reset)
120    }
121    ///Use CEN bit from CTL0 register
122    #[inline(always)]
123    pub fn enable(self) -> &'a mut crate::W<REG> {
124        self.variant(Mmsel::Enable)
125    }
126    ///Use the update event
127    #[inline(always)]
128    pub fn update(self) -> &'a mut crate::W<REG> {
129        self.variant(Mmsel::Update)
130    }
131    ///The trigger output send a positive pulse when a capture or a compare match occurred in channel 0
132    #[inline(always)]
133    pub fn capture_compare_pulse(self) -> &'a mut crate::W<REG> {
134        self.variant(Mmsel::CaptureComparePulse)
135    }
136    ///O0CPRE signal is used as trigger output
137    #[inline(always)]
138    pub fn compare_o0c(self) -> &'a mut crate::W<REG> {
139        self.variant(Mmsel::CompareO0c)
140    }
141    ///O1CPRE signal is used as trigger output
142    #[inline(always)]
143    pub fn compare_o1c(self) -> &'a mut crate::W<REG> {
144        self.variant(Mmsel::CompareO1c)
145    }
146    ///O2CPRE signal is used as trigger output
147    #[inline(always)]
148    pub fn compare_o2c(self) -> &'a mut crate::W<REG> {
149        self.variant(Mmsel::CompareO2c)
150    }
151    ///O3CPRE signal is used as trigger output
152    #[inline(always)]
153    pub fn compare_o3c(self) -> &'a mut crate::W<REG> {
154        self.variant(Mmsel::CompareO3c)
155    }
156}
157///Field `TI1SEL` reader - TI1SEL
158pub type Ti1selR = crate::BitReader;
159///Field `TI1SEL` writer - TI1SEL
160pub type Ti1selW<'a, REG> = crate::BitWriter<'a, REG>;
161///Field `OI1` reader - OI1
162pub type Oi1R = crate::BitReader;
163///Field `OI1` writer - OI1
164pub type Oi1W<'a, REG> = crate::BitWriter<'a, REG>;
165///Field `OI1N` reader - OI1N
166pub type Oi1nR = crate::BitReader;
167///Field `OI1N` writer - OI1N
168pub type Oi1nW<'a, REG> = crate::BitWriter<'a, REG>;
169///Field `OI2` reader - OI2
170pub type Oi2R = crate::BitReader;
171///Field `OI2` writer - OI2
172pub type Oi2W<'a, REG> = crate::BitWriter<'a, REG>;
173///Field `OI2N` reader - OI2N
174pub type Oi2nR = crate::BitReader;
175///Field `OI2N` writer - OI2N
176pub type Oi2nW<'a, REG> = crate::BitWriter<'a, REG>;
177///Field `OI3` reader - OI3
178pub type Oi3R = crate::BitReader;
179///Field `OI3` writer - OI3
180pub type Oi3W<'a, REG> = crate::BitWriter<'a, REG>;
181///Field `OI3N` reader - OI3N
182pub type Oi3nR = crate::BitReader;
183///Field `OI3N` writer - OI3N
184pub type Oi3nW<'a, REG> = crate::BitWriter<'a, REG>;
185///Field `OI4` reader - OI4
186pub type Oi4R = crate::BitReader;
187///Field `OI4` writer - OI4
188pub type Oi4W<'a, REG> = crate::BitWriter<'a, REG>;
189///Field `OI5` reader - OI5
190pub type Oi5R = crate::BitReader;
191///Field `OI5` writer - OI5
192pub type Oi5W<'a, REG> = crate::BitWriter<'a, REG>;
193///Field `OI6` reader - OI6
194pub type Oi6R = crate::BitReader;
195///Field `OI6` writer - OI6
196pub type Oi6W<'a, REG> = crate::BitWriter<'a, REG>;
197impl R {
198    ///Bit 0 - CCPCTL
199    #[inline(always)]
200    pub fn ccpctl(&self) -> CcpctlR {
201        CcpctlR::new((self.bits & 1) != 0)
202    }
203    ///Bit 2 - CCUSEL
204    #[inline(always)]
205    pub fn ccusel(&self) -> CcuselR {
206        CcuselR::new(((self.bits >> 2) & 1) != 0)
207    }
208    ///Bit 3 - CCDSEL
209    #[inline(always)]
210    pub fn ccdsel(&self) -> CcdselR {
211        CcdselR::new(((self.bits >> 3) & 1) != 0)
212    }
213    ///Bits 4:6 - MMSEL
214    #[inline(always)]
215    pub fn mmsel(&self) -> MmselR {
216        MmselR::new(((self.bits >> 4) & 7) as u8)
217    }
218    ///Bit 7 - TI1SEL
219    #[inline(always)]
220    pub fn ti1sel(&self) -> Ti1selR {
221        Ti1selR::new(((self.bits >> 7) & 1) != 0)
222    }
223    ///Bit 8 - OI1
224    #[inline(always)]
225    pub fn oi1(&self) -> Oi1R {
226        Oi1R::new(((self.bits >> 8) & 1) != 0)
227    }
228    ///Bit 9 - OI1N
229    #[inline(always)]
230    pub fn oi1n(&self) -> Oi1nR {
231        Oi1nR::new(((self.bits >> 9) & 1) != 0)
232    }
233    ///Bit 10 - OI2
234    #[inline(always)]
235    pub fn oi2(&self) -> Oi2R {
236        Oi2R::new(((self.bits >> 10) & 1) != 0)
237    }
238    ///Bit 11 - OI2N
239    #[inline(always)]
240    pub fn oi2n(&self) -> Oi2nR {
241        Oi2nR::new(((self.bits >> 11) & 1) != 0)
242    }
243    ///Bit 12 - OI3
244    #[inline(always)]
245    pub fn oi3(&self) -> Oi3R {
246        Oi3R::new(((self.bits >> 12) & 1) != 0)
247    }
248    ///Bit 13 - OI3N
249    #[inline(always)]
250    pub fn oi3n(&self) -> Oi3nR {
251        Oi3nR::new(((self.bits >> 13) & 1) != 0)
252    }
253    ///Bit 14 - OI4
254    #[inline(always)]
255    pub fn oi4(&self) -> Oi4R {
256        Oi4R::new(((self.bits >> 14) & 1) != 0)
257    }
258    ///Bit 16 - OI5
259    #[inline(always)]
260    pub fn oi5(&self) -> Oi5R {
261        Oi5R::new(((self.bits >> 16) & 1) != 0)
262    }
263    ///Bit 18 - OI6
264    #[inline(always)]
265    pub fn oi6(&self) -> Oi6R {
266        Oi6R::new(((self.bits >> 18) & 1) != 0)
267    }
268}
269impl W {
270    ///Bit 0 - CCPCTL
271    #[inline(always)]
272    #[must_use]
273    pub fn ccpctl(&mut self) -> CcpctlW<Ctrl2Spec> {
274        CcpctlW::new(self, 0)
275    }
276    ///Bit 2 - CCUSEL
277    #[inline(always)]
278    #[must_use]
279    pub fn ccusel(&mut self) -> CcuselW<Ctrl2Spec> {
280        CcuselW::new(self, 2)
281    }
282    ///Bit 3 - CCDSEL
283    #[inline(always)]
284    #[must_use]
285    pub fn ccdsel(&mut self) -> CcdselW<Ctrl2Spec> {
286        CcdselW::new(self, 3)
287    }
288    ///Bits 4:6 - MMSEL
289    #[inline(always)]
290    #[must_use]
291    pub fn mmsel(&mut self) -> MmselW<Ctrl2Spec> {
292        MmselW::new(self, 4)
293    }
294    ///Bit 7 - TI1SEL
295    #[inline(always)]
296    #[must_use]
297    pub fn ti1sel(&mut self) -> Ti1selW<Ctrl2Spec> {
298        Ti1selW::new(self, 7)
299    }
300    ///Bit 8 - OI1
301    #[inline(always)]
302    #[must_use]
303    pub fn oi1(&mut self) -> Oi1W<Ctrl2Spec> {
304        Oi1W::new(self, 8)
305    }
306    ///Bit 9 - OI1N
307    #[inline(always)]
308    #[must_use]
309    pub fn oi1n(&mut self) -> Oi1nW<Ctrl2Spec> {
310        Oi1nW::new(self, 9)
311    }
312    ///Bit 10 - OI2
313    #[inline(always)]
314    #[must_use]
315    pub fn oi2(&mut self) -> Oi2W<Ctrl2Spec> {
316        Oi2W::new(self, 10)
317    }
318    ///Bit 11 - OI2N
319    #[inline(always)]
320    #[must_use]
321    pub fn oi2n(&mut self) -> Oi2nW<Ctrl2Spec> {
322        Oi2nW::new(self, 11)
323    }
324    ///Bit 12 - OI3
325    #[inline(always)]
326    #[must_use]
327    pub fn oi3(&mut self) -> Oi3W<Ctrl2Spec> {
328        Oi3W::new(self, 12)
329    }
330    ///Bit 13 - OI3N
331    #[inline(always)]
332    #[must_use]
333    pub fn oi3n(&mut self) -> Oi3nW<Ctrl2Spec> {
334        Oi3nW::new(self, 13)
335    }
336    ///Bit 14 - OI4
337    #[inline(always)]
338    #[must_use]
339    pub fn oi4(&mut self) -> Oi4W<Ctrl2Spec> {
340        Oi4W::new(self, 14)
341    }
342    ///Bit 16 - OI5
343    #[inline(always)]
344    #[must_use]
345    pub fn oi5(&mut self) -> Oi5W<Ctrl2Spec> {
346        Oi5W::new(self, 16)
347    }
348    ///Bit 18 - OI6
349    #[inline(always)]
350    #[must_use]
351    pub fn oi6(&mut self) -> Oi6W<Ctrl2Spec> {
352        Oi6W::new(self, 18)
353    }
354}
355///TIMx_CTRL2
356///
357///You can [`read`](crate::generic::Reg::read) this register and get [`ctrl2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
358pub struct Ctrl2Spec;
359impl crate::RegisterSpec for Ctrl2Spec {
360    type Ux = u32;
361}
362///`read()` method returns [`ctrl2::R`](R) reader structure
363impl crate::Readable for Ctrl2Spec {}
364///`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure
365impl crate::Writable for Ctrl2Spec {
366    type Safety = crate::Unsafe;
367    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
368    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
369}
370///`reset()` method sets CTRL2 to value 0
371impl crate::Resettable for Ctrl2Spec {
372    const RESET_VALUE: u32 = 0;
373}
n32g4/n32g455/tim2/ctrl2.rs

n32g4/n32g455/tim2/
ctrl2.rs
