n32g4/n32g455/rcc/
ctrl.rs

1///Register `CTRL` reader
2pub type R = crate::R<CtrlSpec>;
3///Register `CTRL` writer
4pub type W = crate::W<CtrlSpec>;
5///HSIEN
6///
7///Value on reset: 1
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum Hsien {
10    ///0: HSI Off
11    Off = 0,
12    ///1: HSI On
13    On = 1,
14}
15impl From<Hsien> for bool {
16    #[inline(always)]
17    fn from(variant: Hsien) -> Self {
18        variant as u8 != 0
19    }
20}
21///Field `HSIEN` reader - HSIEN
22pub type HsienR = crate::BitReader<Hsien>;
23impl HsienR {
24    ///Get enumerated values variant
25    #[inline(always)]
26    pub const fn variant(&self) -> Hsien {
27        match self.bits {
28            false => Hsien::Off,
29            true => Hsien::On,
30        }
31    }
32    ///HSI Off
33    #[inline(always)]
34    pub fn is_off(&self) -> bool {
35        *self == Hsien::Off
36    }
37    ///HSI On
38    #[inline(always)]
39    pub fn is_on(&self) -> bool {
40        *self == Hsien::On
41    }
42}
43///Field `HSIEN` writer - HSIEN
44pub type HsienW<'a, REG> = crate::BitWriter<'a, REG, Hsien>;
45impl<'a, REG> HsienW<'a, REG>
46where
47    REG: crate::Writable + crate::RegisterSpec,
48{
49    ///HSI Off
50    #[inline(always)]
51    pub fn off(self) -> &'a mut crate::W<REG> {
52        self.variant(Hsien::Off)
53    }
54    ///HSI On
55    #[inline(always)]
56    pub fn on(self) -> &'a mut crate::W<REG> {
57        self.variant(Hsien::On)
58    }
59}
60///Field `HSIRDF` reader - HSIRDF
61pub type HsirdfR = crate::BitReader;
62///Field `HSIRDF` writer - HSIRDF
63pub type HsirdfW<'a, REG> = crate::BitWriter<'a, REG>;
64///Field `HSITRIM` reader - HSITRIM
65pub type HsitrimR = crate::FieldReader;
66///Field `HSITRIM` writer - HSITRIM
67pub type HsitrimW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
68///Field `HSICAL` reader - HSICAL
69pub type HsicalR = crate::FieldReader;
70///Field `HSICAL` writer - HSICAL
71pub type HsicalW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
72///HSEEN
73///
74///Value on reset: 0
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum Hseen {
77    ///0: HSE Off
78    Off = 0,
79    ///1: HSE On
80    On = 1,
81}
82impl From<Hseen> for bool {
83    #[inline(always)]
84    fn from(variant: Hseen) -> Self {
85        variant as u8 != 0
86    }
87}
88///Field `HSEEN` reader - HSEEN
89pub type HseenR = crate::BitReader<Hseen>;
90impl HseenR {
91    ///Get enumerated values variant
92    #[inline(always)]
93    pub const fn variant(&self) -> Hseen {
94        match self.bits {
95            false => Hseen::Off,
96            true => Hseen::On,
97        }
98    }
99    ///HSE Off
100    #[inline(always)]
101    pub fn is_off(&self) -> bool {
102        *self == Hseen::Off
103    }
104    ///HSE On
105    #[inline(always)]
106    pub fn is_on(&self) -> bool {
107        *self == Hseen::On
108    }
109}
110///Field `HSEEN` writer - HSEEN
111pub type HseenW<'a, REG> = crate::BitWriter<'a, REG, Hseen>;
112impl<'a, REG> HseenW<'a, REG>
113where
114    REG: crate::Writable + crate::RegisterSpec,
115{
116    ///HSE Off
117    #[inline(always)]
118    pub fn off(self) -> &'a mut crate::W<REG> {
119        self.variant(Hseen::Off)
120    }
121    ///HSE On
122    #[inline(always)]
123    pub fn on(self) -> &'a mut crate::W<REG> {
124        self.variant(Hseen::On)
125    }
126}
127///Field `HSERDF` reader - HSERDF
128pub type HserdfR = crate::BitReader;
129///Field `HSERDF` writer - HSERDF
130pub type HserdfW<'a, REG> = crate::BitWriter<'a, REG>;
131///HSEBP
132///
133///Value on reset: 0
134#[derive(Clone, Copy, Debug, PartialEq, Eq)]
135pub enum Hsebp {
136    ///0: HXTAL crystal oscillator not bypassed
137    NotBypassed = 0,
138    ///1: HXTAL crystal oscillator bypassed with external clock
139    Bypassed = 1,
140}
141impl From<Hsebp> for bool {
142    #[inline(always)]
143    fn from(variant: Hsebp) -> Self {
144        variant as u8 != 0
145    }
146}
147///Field `HSEBP` reader - HSEBP
148pub type HsebpR = crate::BitReader<Hsebp>;
149impl HsebpR {
150    ///Get enumerated values variant
151    #[inline(always)]
152    pub const fn variant(&self) -> Hsebp {
153        match self.bits {
154            false => Hsebp::NotBypassed,
155            true => Hsebp::Bypassed,
156        }
157    }
158    ///HXTAL crystal oscillator not bypassed
159    #[inline(always)]
160    pub fn is_not_bypassed(&self) -> bool {
161        *self == Hsebp::NotBypassed
162    }
163    ///HXTAL crystal oscillator bypassed with external clock
164    #[inline(always)]
165    pub fn is_bypassed(&self) -> bool {
166        *self == Hsebp::Bypassed
167    }
168}
169///Field `HSEBP` writer - HSEBP
170pub type HsebpW<'a, REG> = crate::BitWriter<'a, REG, Hsebp>;
171impl<'a, REG> HsebpW<'a, REG>
172where
173    REG: crate::Writable + crate::RegisterSpec,
174{
175    ///HXTAL crystal oscillator not bypassed
176    #[inline(always)]
177    pub fn not_bypassed(self) -> &'a mut crate::W<REG> {
178        self.variant(Hsebp::NotBypassed)
179    }
180    ///HXTAL crystal oscillator bypassed with external clock
181    #[inline(always)]
182    pub fn bypassed(self) -> &'a mut crate::W<REG> {
183        self.variant(Hsebp::Bypassed)
184    }
185}
186///CLKSSEN
187///
188///Value on reset: 0
189#[derive(Clone, Copy, Debug, PartialEq, Eq)]
190pub enum Clkssen {
191    ///0: Clock monitor disabled
192    Off = 0,
193    ///1: Clock monitor enabled
194    On = 1,
195}
196impl From<Clkssen> for bool {
197    #[inline(always)]
198    fn from(variant: Clkssen) -> Self {
199        variant as u8 != 0
200    }
201}
202///Field `CLKSSEN` reader - CLKSSEN
203pub type ClkssenR = crate::BitReader<Clkssen>;
204impl ClkssenR {
205    ///Get enumerated values variant
206    #[inline(always)]
207    pub const fn variant(&self) -> Clkssen {
208        match self.bits {
209            false => Clkssen::Off,
210            true => Clkssen::On,
211        }
212    }
213    ///Clock monitor disabled
214    #[inline(always)]
215    pub fn is_off(&self) -> bool {
216        *self == Clkssen::Off
217    }
218    ///Clock monitor enabled
219    #[inline(always)]
220    pub fn is_on(&self) -> bool {
221        *self == Clkssen::On
222    }
223}
224///Field `CLKSSEN` writer - CLKSSEN
225pub type ClkssenW<'a, REG> = crate::BitWriter<'a, REG, Clkssen>;
226impl<'a, REG> ClkssenW<'a, REG>
227where
228    REG: crate::Writable + crate::RegisterSpec,
229{
230    ///Clock monitor disabled
231    #[inline(always)]
232    pub fn off(self) -> &'a mut crate::W<REG> {
233        self.variant(Clkssen::Off)
234    }
235    ///Clock monitor enabled
236    #[inline(always)]
237    pub fn on(self) -> &'a mut crate::W<REG> {
238        self.variant(Clkssen::On)
239    }
240}
241///PLLEN
242///
243///Value on reset: 0
244#[derive(Clone, Copy, Debug, PartialEq, Eq)]
245pub enum Pllen {
246    ///0: PLL Off
247    Off = 0,
248    ///1: PLL On
249    On = 1,
250}
251impl From<Pllen> for bool {
252    #[inline(always)]
253    fn from(variant: Pllen) -> Self {
254        variant as u8 != 0
255    }
256}
257///Field `PLLEN` reader - PLLEN
258pub type PllenR = crate::BitReader<Pllen>;
259impl PllenR {
260    ///Get enumerated values variant
261    #[inline(always)]
262    pub const fn variant(&self) -> Pllen {
263        match self.bits {
264            false => Pllen::Off,
265            true => Pllen::On,
266        }
267    }
268    ///PLL Off
269    #[inline(always)]
270    pub fn is_off(&self) -> bool {
271        *self == Pllen::Off
272    }
273    ///PLL On
274    #[inline(always)]
275    pub fn is_on(&self) -> bool {
276        *self == Pllen::On
277    }
278}
279///Field `PLLEN` writer - PLLEN
280pub type PllenW<'a, REG> = crate::BitWriter<'a, REG, Pllen>;
281impl<'a, REG> PllenW<'a, REG>
282where
283    REG: crate::Writable + crate::RegisterSpec,
284{
285    ///PLL Off
286    #[inline(always)]
287    pub fn off(self) -> &'a mut crate::W<REG> {
288        self.variant(Pllen::Off)
289    }
290    ///PLL On
291    #[inline(always)]
292    pub fn on(self) -> &'a mut crate::W<REG> {
293        self.variant(Pllen::On)
294    }
295}
296///PLLRDF
297///
298///Value on reset: 0
299#[derive(Clone, Copy, Debug, PartialEq, Eq)]
300pub enum Pllrdfr {
301    ///0: PLL is not stable
302    NotReady = 0,
303    ///1: PLL is stable
304    Ready = 1,
305}
306impl From<Pllrdfr> for bool {
307    #[inline(always)]
308    fn from(variant: Pllrdfr) -> Self {
309        variant as u8 != 0
310    }
311}
312///Field `PLLRDF` reader - PLLRDF
313pub type PllrdfR = crate::BitReader<Pllrdfr>;
314impl PllrdfR {
315    ///Get enumerated values variant
316    #[inline(always)]
317    pub const fn variant(&self) -> Pllrdfr {
318        match self.bits {
319            false => Pllrdfr::NotReady,
320            true => Pllrdfr::Ready,
321        }
322    }
323    ///PLL is not stable
324    #[inline(always)]
325    pub fn is_not_ready(&self) -> bool {
326        *self == Pllrdfr::NotReady
327    }
328    ///PLL is stable
329    #[inline(always)]
330    pub fn is_ready(&self) -> bool {
331        *self == Pllrdfr::Ready
332    }
333}
334///Field `PLLRDF` writer - PLLRDF
335pub type PllrdfW<'a, REG> = crate::BitWriter<'a, REG, Pllrdfr>;
336impl<'a, REG> PllrdfW<'a, REG>
337where
338    REG: crate::Writable + crate::RegisterSpec,
339{
340    ///PLL is not stable
341    #[inline(always)]
342    pub fn not_ready(self) -> &'a mut crate::W<REG> {
343        self.variant(Pllrdfr::NotReady)
344    }
345    ///PLL is stable
346    #[inline(always)]
347    pub fn ready(self) -> &'a mut crate::W<REG> {
348        self.variant(Pllrdfr::Ready)
349    }
350}
351impl R {
352    ///Bit 0 - HSIEN
353    #[inline(always)]
354    pub fn hsien(&self) -> HsienR {
355        HsienR::new((self.bits & 1) != 0)
356    }
357    ///Bit 1 - HSIRDF
358    #[inline(always)]
359    pub fn hsirdf(&self) -> HsirdfR {
360        HsirdfR::new(((self.bits >> 1) & 1) != 0)
361    }
362    ///Bits 3:7 - HSITRIM
363    #[inline(always)]
364    pub fn hsitrim(&self) -> HsitrimR {
365        HsitrimR::new(((self.bits >> 3) & 0x1f) as u8)
366    }
367    ///Bits 8:15 - HSICAL
368    #[inline(always)]
369    pub fn hsical(&self) -> HsicalR {
370        HsicalR::new(((self.bits >> 8) & 0xff) as u8)
371    }
372    ///Bit 16 - HSEEN
373    #[inline(always)]
374    pub fn hseen(&self) -> HseenR {
375        HseenR::new(((self.bits >> 16) & 1) != 0)
376    }
377    ///Bit 17 - HSERDF
378    #[inline(always)]
379    pub fn hserdf(&self) -> HserdfR {
380        HserdfR::new(((self.bits >> 17) & 1) != 0)
381    }
382    ///Bit 18 - HSEBP
383    #[inline(always)]
384    pub fn hsebp(&self) -> HsebpR {
385        HsebpR::new(((self.bits >> 18) & 1) != 0)
386    }
387    ///Bit 19 - CLKSSEN
388    #[inline(always)]
389    pub fn clkssen(&self) -> ClkssenR {
390        ClkssenR::new(((self.bits >> 19) & 1) != 0)
391    }
392    ///Bit 24 - PLLEN
393    #[inline(always)]
394    pub fn pllen(&self) -> PllenR {
395        PllenR::new(((self.bits >> 24) & 1) != 0)
396    }
397    ///Bit 25 - PLLRDF
398    #[inline(always)]
399    pub fn pllrdf(&self) -> PllrdfR {
400        PllrdfR::new(((self.bits >> 25) & 1) != 0)
401    }
402}
403impl W {
404    ///Bit 0 - HSIEN
405    #[inline(always)]
406    #[must_use]
407    pub fn hsien(&mut self) -> HsienW<CtrlSpec> {
408        HsienW::new(self, 0)
409    }
410    ///Bit 1 - HSIRDF
411    #[inline(always)]
412    #[must_use]
413    pub fn hsirdf(&mut self) -> HsirdfW<CtrlSpec> {
414        HsirdfW::new(self, 1)
415    }
416    ///Bits 3:7 - HSITRIM
417    #[inline(always)]
418    #[must_use]
419    pub fn hsitrim(&mut self) -> HsitrimW<CtrlSpec> {
420        HsitrimW::new(self, 3)
421    }
422    ///Bits 8:15 - HSICAL
423    #[inline(always)]
424    #[must_use]
425    pub fn hsical(&mut self) -> HsicalW<CtrlSpec> {
426        HsicalW::new(self, 8)
427    }
428    ///Bit 16 - HSEEN
429    #[inline(always)]
430    #[must_use]
431    pub fn hseen(&mut self) -> HseenW<CtrlSpec> {
432        HseenW::new(self, 16)
433    }
434    ///Bit 17 - HSERDF
435    #[inline(always)]
436    #[must_use]
437    pub fn hserdf(&mut self) -> HserdfW<CtrlSpec> {
438        HserdfW::new(self, 17)
439    }
440    ///Bit 18 - HSEBP
441    #[inline(always)]
442    #[must_use]
443    pub fn hsebp(&mut self) -> HsebpW<CtrlSpec> {
444        HsebpW::new(self, 18)
445    }
446    ///Bit 19 - CLKSSEN
447    #[inline(always)]
448    #[must_use]
449    pub fn clkssen(&mut self) -> ClkssenW<CtrlSpec> {
450        ClkssenW::new(self, 19)
451    }
452    ///Bit 24 - PLLEN
453    #[inline(always)]
454    #[must_use]
455    pub fn pllen(&mut self) -> PllenW<CtrlSpec> {
456        PllenW::new(self, 24)
457    }
458    ///Bit 25 - PLLRDF
459    #[inline(always)]
460    #[must_use]
461    pub fn pllrdf(&mut self) -> PllrdfW<CtrlSpec> {
462        PllrdfW::new(self, 25)
463    }
464}
465///RCC_CTRL
466///
467///You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
468pub struct CtrlSpec;
469impl crate::RegisterSpec for CtrlSpec {
470    type Ux = u32;
471}
472///`read()` method returns [`ctrl::R`](R) reader structure
473impl crate::Readable for CtrlSpec {}
474///`write(|w| ..)` method takes [`ctrl::W`](W) writer structure
475impl crate::Writable for CtrlSpec {
476    type Safety = crate::Unsafe;
477    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
478    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
479}
480///`reset()` method sets CTRL to value 0x83
481impl crate::Resettable for CtrlSpec {
482    const RESET_VALUE: u32 = 0x83;
483}
n32g4/n32g455/rcc/ctrl.rs

n32g4/n32g455/rcc/
ctrl.rs
