n32g4/n32g430/afio/
exti_cfg2.rs

1///Register `EXTI_CFG2` reader
2pub type R = crate::R<ExtiCfg2Spec>;
3///Register `EXTI_CFG2` writer
4pub type W = crate::W<ExtiCfg2Spec>;
5///Field `EXTI4` reader - EXTI4
6pub type Exti4R = crate::FieldReader;
7///Field `EXTI4` writer - EXTI4
8pub type Exti4W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9///Field `EXTI5` reader - EXTI5
10pub type Exti5R = crate::FieldReader;
11///Field `EXTI5` writer - EXTI5
12pub type Exti5W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13///Field `EXTI6` reader - EXTI6
14pub type Exti6R = crate::FieldReader;
15///Field `EXTI6` writer - EXTI6
16pub type Exti6W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17///Field `EXTI7` reader - EXTI7
18pub type Exti7R = crate::FieldReader;
19///Field `EXTI7` writer - EXTI7
20pub type Exti7W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
21impl R {
22    ///Bits 0:5 - EXTI4
23    #[inline(always)]
24    pub fn exti4(&self) -> Exti4R {
25        Exti4R::new((self.bits & 0x3f) as u8)
26    }
27    ///Bits 8:13 - EXTI5
28    #[inline(always)]
29    pub fn exti5(&self) -> Exti5R {
30        Exti5R::new(((self.bits >> 8) & 0x3f) as u8)
31    }
32    ///Bits 16:21 - EXTI6
33    #[inline(always)]
34    pub fn exti6(&self) -> Exti6R {
35        Exti6R::new(((self.bits >> 16) & 0x3f) as u8)
36    }
37    ///Bits 24:29 - EXTI7
38    #[inline(always)]
39    pub fn exti7(&self) -> Exti7R {
40        Exti7R::new(((self.bits >> 24) & 0x3f) as u8)
41    }
42}
43impl W {
44    ///Bits 0:5 - EXTI4
45    #[inline(always)]
46    #[must_use]
47    pub fn exti4(&mut self) -> Exti4W<ExtiCfg2Spec> {
48        Exti4W::new(self, 0)
49    }
50    ///Bits 8:13 - EXTI5
51    #[inline(always)]
52    #[must_use]
53    pub fn exti5(&mut self) -> Exti5W<ExtiCfg2Spec> {
54        Exti5W::new(self, 8)
55    }
56    ///Bits 16:21 - EXTI6
57    #[inline(always)]
58    #[must_use]
59    pub fn exti6(&mut self) -> Exti6W<ExtiCfg2Spec> {
60        Exti6W::new(self, 16)
61    }
62    ///Bits 24:29 - EXTI7
63    #[inline(always)]
64    #[must_use]
65    pub fn exti7(&mut self) -> Exti7W<ExtiCfg2Spec> {
66        Exti7W::new(self, 24)
67    }
68}
69///AFIO_EXTI_CFG2
70///
71///You can [`read`](crate::generic::Reg::read) this register and get [`exti_cfg2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exti_cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
72pub struct ExtiCfg2Spec;
73impl crate::RegisterSpec for ExtiCfg2Spec {
74    type Ux = u32;
75}
76///`read()` method returns [`exti_cfg2::R`](R) reader structure
77impl crate::Readable for ExtiCfg2Spec {}
78///`write(|w| ..)` method takes [`exti_cfg2::W`](W) writer structure
79impl crate::Writable for ExtiCfg2Spec {
80    type Safety = crate::Unsafe;
81    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
82    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
83}
84///`reset()` method sets EXTI_CFG2 to value 0
85impl crate::Resettable for ExtiCfg2Spec {
86    const RESET_VALUE: u32 = 0;
87}
n32g4/n32g430/afio/exti_cfg2.rs

n32g4/n32g430/afio/
exti_cfg2.rs
