muscab1_pac/i_cache/
icctrl.rs

1#[doc = "Register `ICCTRL` reader"]
2pub type R = crate::R<IcctrlSpec>;
3#[doc = "Register `ICCTRL` writer"]
4pub type W = crate::W<IcctrlSpec>;
5#[doc = "Enable Cache\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Cacheen {
8    #[doc = "1: Caching is enabled"]
9    Enabled = 1,
10    #[doc = "0: All accesses bypass the cache"]
11    Disabled = 0,
12}
13impl From<Cacheen> for bool {
14    #[inline(always)]
15    fn from(variant: Cacheen) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `CACHEEN` reader - Enable Cache"]
20pub type CacheenR = crate::BitReader<Cacheen>;
21impl CacheenR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Cacheen {
25        match self.bits {
26            true => Cacheen::Enabled,
27            false => Cacheen::Disabled,
28        }
29    }
30    #[doc = "Caching is enabled"]
31    #[inline(always)]
32    pub fn is_enabled(&self) -> bool {
33        *self == Cacheen::Enabled
34    }
35    #[doc = "All accesses bypass the cache"]
36    #[inline(always)]
37    pub fn is_disabled(&self) -> bool {
38        *self == Cacheen::Disabled
39    }
40}
41#[doc = "Field `CACHEEN` writer - Enable Cache"]
42pub type CacheenW<'a, REG> = crate::BitWriter<'a, REG, Cacheen>;
43impl<'a, REG> CacheenW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Caching is enabled"]
48    #[inline(always)]
49    pub fn enabled(self) -> &'a mut crate::W<REG> {
50        self.variant(Cacheen::Enabled)
51    }
52    #[doc = "All accesses bypass the cache"]
53    #[inline(always)]
54    pub fn disabled(self) -> &'a mut crate::W<REG> {
55        self.variant(Cacheen::Disabled)
56    }
57}
58#[doc = "Full Cache Invalidate\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum Finv {
61    #[doc = "1: Triggers the instruction cache to start invalidating all cache lines"]
62    Invalidate = 1,
63}
64impl From<Finv> for bool {
65    #[inline(always)]
66    fn from(variant: Finv) -> Self {
67        variant as u8 != 0
68    }
69}
70#[doc = "Field `FINV` writer - Full Cache Invalidate"]
71pub type FinvW<'a, REG> = crate::BitWriter<'a, REG, Finv>;
72impl<'a, REG> FinvW<'a, REG>
73where
74    REG: crate::Writable + crate::RegisterSpec,
75{
76    #[doc = "Triggers the instruction cache to start invalidating all cache lines"]
77    #[inline(always)]
78    pub fn invalidate(self) -> &'a mut crate::W<REG> {
79        self.variant(Finv::Invalidate)
80    }
81}
82#[doc = "Enable Statistic function\n\nValue on reset: 0"]
83#[derive(Clone, Copy, Debug, PartialEq, Eq)]
84pub enum Staten {
85    #[doc = "1: Cache statistic counters are enabled"]
86    Enabled = 1,
87    #[doc = "0: Cache statistic counters are disabled"]
88    Disabled = 0,
89}
90impl From<Staten> for bool {
91    #[inline(always)]
92    fn from(variant: Staten) -> Self {
93        variant as u8 != 0
94    }
95}
96#[doc = "Field `STATEN` reader - Enable Statistic function"]
97pub type StatenR = crate::BitReader<Staten>;
98impl StatenR {
99    #[doc = "Get enumerated values variant"]
100    #[inline(always)]
101    pub const fn variant(&self) -> Staten {
102        match self.bits {
103            true => Staten::Enabled,
104            false => Staten::Disabled,
105        }
106    }
107    #[doc = "Cache statistic counters are enabled"]
108    #[inline(always)]
109    pub fn is_enabled(&self) -> bool {
110        *self == Staten::Enabled
111    }
112    #[doc = "Cache statistic counters are disabled"]
113    #[inline(always)]
114    pub fn is_disabled(&self) -> bool {
115        *self == Staten::Disabled
116    }
117}
118#[doc = "Field `STATEN` writer - Enable Statistic function"]
119pub type StatenW<'a, REG> = crate::BitWriter<'a, REG, Staten>;
120impl<'a, REG> StatenW<'a, REG>
121where
122    REG: crate::Writable + crate::RegisterSpec,
123{
124    #[doc = "Cache statistic counters are enabled"]
125    #[inline(always)]
126    pub fn enabled(self) -> &'a mut crate::W<REG> {
127        self.variant(Staten::Enabled)
128    }
129    #[doc = "Cache statistic counters are disabled"]
130    #[inline(always)]
131    pub fn disabled(self) -> &'a mut crate::W<REG> {
132        self.variant(Staten::Disabled)
133    }
134}
135#[doc = "Clear Statistic values\n\nValue on reset: 0"]
136#[derive(Clone, Copy, Debug, PartialEq, Eq)]
137pub enum Statc {
138    #[doc = "1: Triggers the instruction cache to start clear all cache statistic counters"]
139    Clear = 1,
140}
141impl From<Statc> for bool {
142    #[inline(always)]
143    fn from(variant: Statc) -> Self {
144        variant as u8 != 0
145    }
146}
147#[doc = "Field `STATC` writer - Clear Statistic values"]
148pub type StatcW<'a, REG> = crate::BitWriter<'a, REG, Statc>;
149impl<'a, REG> StatcW<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Triggers the instruction cache to start clear all cache statistic counters"]
154    #[inline(always)]
155    pub fn clear(self) -> &'a mut crate::W<REG> {
156        self.variant(Statc::Clear)
157    }
158}
159#[doc = "Enable Handler Allocation\n\nValue on reset: 0"]
160#[derive(Clone, Copy, Debug, PartialEq, Eq)]
161pub enum Halloc {
162    #[doc = "0: All incoming handler code fetches are not allocated a cache line if a miss occurs"]
163    Low = 0,
164    #[doc = "1: Handler code access is treated like any other code access arriving at its interface"]
165    High = 1,
166}
167impl From<Halloc> for bool {
168    #[inline(always)]
169    fn from(variant: Halloc) -> Self {
170        variant as u8 != 0
171    }
172}
173#[doc = "Field `HALLOC` reader - Enable Handler Allocation"]
174pub type HallocR = crate::BitReader<Halloc>;
175impl HallocR {
176    #[doc = "Get enumerated values variant"]
177    #[inline(always)]
178    pub const fn variant(&self) -> Halloc {
179        match self.bits {
180            false => Halloc::Low,
181            true => Halloc::High,
182        }
183    }
184    #[doc = "All incoming handler code fetches are not allocated a cache line if a miss occurs"]
185    #[inline(always)]
186    pub fn is_low(&self) -> bool {
187        *self == Halloc::Low
188    }
189    #[doc = "Handler code access is treated like any other code access arriving at its interface"]
190    #[inline(always)]
191    pub fn is_high(&self) -> bool {
192        *self == Halloc::High
193    }
194}
195#[doc = "Field `HALLOC` writer - Enable Handler Allocation"]
196pub type HallocW<'a, REG> = crate::BitWriter<'a, REG, Halloc>;
197impl<'a, REG> HallocW<'a, REG>
198where
199    REG: crate::Writable + crate::RegisterSpec,
200{
201    #[doc = "All incoming handler code fetches are not allocated a cache line if a miss occurs"]
202    #[inline(always)]
203    pub fn low(self) -> &'a mut crate::W<REG> {
204        self.variant(Halloc::Low)
205    }
206    #[doc = "Handler code access is treated like any other code access arriving at its interface"]
207    #[inline(always)]
208    pub fn high(self) -> &'a mut crate::W<REG> {
209        self.variant(Halloc::High)
210    }
211}
212impl R {
213    #[doc = "Bit 0 - Enable Cache"]
214    #[inline(always)]
215    pub fn cacheen(&self) -> CacheenR {
216        CacheenR::new((self.bits & 1) != 0)
217    }
218    #[doc = "Bit 3 - Enable Statistic function"]
219    #[inline(always)]
220    pub fn staten(&self) -> StatenR {
221        StatenR::new(((self.bits >> 3) & 1) != 0)
222    }
223    #[doc = "Bit 5 - Enable Handler Allocation"]
224    #[inline(always)]
225    pub fn halloc(&self) -> HallocR {
226        HallocR::new(((self.bits >> 5) & 1) != 0)
227    }
228}
229impl W {
230    #[doc = "Bit 0 - Enable Cache"]
231    #[inline(always)]
232    pub fn cacheen(&mut self) -> CacheenW<IcctrlSpec> {
233        CacheenW::new(self, 0)
234    }
235    #[doc = "Bit 2 - Full Cache Invalidate"]
236    #[inline(always)]
237    pub fn finv(&mut self) -> FinvW<IcctrlSpec> {
238        FinvW::new(self, 2)
239    }
240    #[doc = "Bit 3 - Enable Statistic function"]
241    #[inline(always)]
242    pub fn staten(&mut self) -> StatenW<IcctrlSpec> {
243        StatenW::new(self, 3)
244    }
245    #[doc = "Bit 4 - Clear Statistic values"]
246    #[inline(always)]
247    pub fn statc(&mut self) -> StatcW<IcctrlSpec> {
248        StatcW::new(self, 4)
249    }
250    #[doc = "Bit 5 - Enable Handler Allocation"]
251    #[inline(always)]
252    pub fn halloc(&mut self) -> HallocW<IcctrlSpec> {
253        HallocW::new(self, 5)
254    }
255}
256#[doc = "Instruction Cache Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`icctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
257pub struct IcctrlSpec;
258impl crate::RegisterSpec for IcctrlSpec {
259    type Ux = u32;
260}
261#[doc = "`read()` method returns [`icctrl::R`](R) reader structure"]
262impl crate::Readable for IcctrlSpec {}
263#[doc = "`write(|w| ..)` method takes [`icctrl::W`](W) writer structure"]
264impl crate::Writable for IcctrlSpec {
265    type Safety = crate::Unsafe;
266    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
267    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
268}
269#[doc = "`reset()` method sets ICCTRL to value 0"]
270impl crate::Resettable for IcctrlSpec {
271    const RESET_VALUE: u32 = 0;
272}
muscab1_pac/i_cache/icctrl.rs

muscab1_pac/i_cache/
icctrl.rs
