muscab1_pac/scc/
clk_test_ctrl.rs

1#[doc = "Register `CLK_TEST_CTRL` reader"]
2pub type R = crate::R<ClkTestCtrlSpec>;
3#[doc = "Register `CLK_TEST_CTRL` writer"]
4pub type W = crate::W<ClkTestCtrlSpec>;
5#[doc = "Field `CLK_TEST_SEL` reader - Select TESTMUX input"]
6pub type ClkTestSelR = crate::FieldReader;
7#[doc = "Field `CLK_TEST_SEL` writer - Select TESTMUX input"]
8pub type ClkTestSelW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `CLK_TEST_EN` reader - 0: Not enable 1: Enable"]
10pub type ClkTestEnR = crate::BitReader;
11#[doc = "Field `CLK_TEST_EN` writer - 0: Not enable 1: Enable"]
12pub type ClkTestEnW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CLK_MAIN_FORCE_RDY` reader - CLK_MAIN_FORCE_RDY"]
14pub type ClkMainForceRdyR = crate::BitReader;
15#[doc = "Field `CLK_MAIN_FORCE_RDY` writer - CLK_MAIN_FORCE_RDY"]
16pub type ClkMainForceRdyW<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bits 0:4 - Select TESTMUX input"]
19    #[inline(always)]
20    pub fn clk_test_sel(&self) -> ClkTestSelR {
21        ClkTestSelR::new((self.bits & 0x1f) as u8)
22    }
23    #[doc = "Bit 5 - 0: Not enable 1: Enable"]
24    #[inline(always)]
25    pub fn clk_test_en(&self) -> ClkTestEnR {
26        ClkTestEnR::new(((self.bits >> 5) & 1) != 0)
27    }
28    #[doc = "Bit 6 - CLK_MAIN_FORCE_RDY"]
29    #[inline(always)]
30    pub fn clk_main_force_rdy(&self) -> ClkMainForceRdyR {
31        ClkMainForceRdyR::new(((self.bits >> 6) & 1) != 0)
32    }
33}
34impl W {
35    #[doc = "Bits 0:4 - Select TESTMUX input"]
36    #[inline(always)]
37    pub fn clk_test_sel(&mut self) -> ClkTestSelW<ClkTestCtrlSpec> {
38        ClkTestSelW::new(self, 0)
39    }
40    #[doc = "Bit 5 - 0: Not enable 1: Enable"]
41    #[inline(always)]
42    pub fn clk_test_en(&mut self) -> ClkTestEnW<ClkTestCtrlSpec> {
43        ClkTestEnW::new(self, 5)
44    }
45    #[doc = "Bit 6 - CLK_MAIN_FORCE_RDY"]
46    #[inline(always)]
47    pub fn clk_main_force_rdy(&mut self) -> ClkMainForceRdyW<ClkTestCtrlSpec> {
48        ClkMainForceRdyW::new(self, 6)
49    }
50}
51#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_test_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_test_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
52pub struct ClkTestCtrlSpec;
53impl crate::RegisterSpec for ClkTestCtrlSpec {
54    type Ux = u32;
55}
56#[doc = "`read()` method returns [`clk_test_ctrl::R`](R) reader structure"]
57impl crate::Readable for ClkTestCtrlSpec {}
58#[doc = "`write(|w| ..)` method takes [`clk_test_ctrl::W`](W) writer structure"]
59impl crate::Writable for ClkTestCtrlSpec {
60    type Safety = crate::Unsafe;
61    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
62    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
63}
64#[doc = "`reset()` method sets CLK_TEST_CTRL to value 0"]
65impl crate::Resettable for ClkTestCtrlSpec {
66    const RESET_VALUE: u32 = 0;
67}
muscab1_pac/scc/clk_test_ctrl.rs

muscab1_pac/scc/
clk_test_ctrl.rs
