muscab1_pac/sysinfo/
sys_config.rs1#[doc = "Register `SYS_CONFIG` reader"]
2pub type R = crate::R<SysConfigSpec>;
3#[doc = "Field `SRAM_NUM_BANK` reader - SRAM Number of Banks"]
4pub type SramNumBankR = crate::FieldReader;
5#[doc = "Field `SRAM_ADDR_WIDTH` reader - SRAM Bank Address Width"]
6pub type SramAddrWidthR = crate::FieldReader;
7#[doc = "CPU 0 has Data TCM:\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum Cpu0HasTcm {
10 #[doc = "0: CPU 0 does not have Data TCM"]
11 No = 0,
12 #[doc = "1: CPU 0 has Data TCM"]
13 Yes = 1,
14}
15impl From<Cpu0HasTcm> for bool {
16 #[inline(always)]
17 fn from(variant: Cpu0HasTcm) -> Self {
18 variant as u8 != 0
19 }
20}
21#[doc = "Field `CPU0_HAS_TCM` reader - CPU 0 has Data TCM:"]
22pub type Cpu0HasTcmR = crate::BitReader<Cpu0HasTcm>;
23impl Cpu0HasTcmR {
24 #[doc = "Get enumerated values variant"]
25 #[inline(always)]
26 pub const fn variant(&self) -> Cpu0HasTcm {
27 match self.bits {
28 false => Cpu0HasTcm::No,
29 true => Cpu0HasTcm::Yes,
30 }
31 }
32 #[doc = "CPU 0 does not have Data TCM"]
33 #[inline(always)]
34 pub fn is_no(&self) -> bool {
35 *self == Cpu0HasTcm::No
36 }
37 #[doc = "CPU 0 has Data TCM"]
38 #[inline(always)]
39 pub fn is_yes(&self) -> bool {
40 *self == Cpu0HasTcm::Yes
41 }
42}
43#[doc = "CPU 1 has Data TCM:\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45pub enum Cpu1HasTcm {
46 #[doc = "0: CPU 1 does not have Data TCM"]
47 No = 0,
48 #[doc = "1: CPU 1 has Data TCM"]
49 Yes = 1,
50}
51impl From<Cpu1HasTcm> for bool {
52 #[inline(always)]
53 fn from(variant: Cpu1HasTcm) -> Self {
54 variant as u8 != 0
55 }
56}
57#[doc = "Field `CPU1_HAS_TCM` reader - CPU 1 has Data TCM:"]
58pub type Cpu1HasTcmR = crate::BitReader<Cpu1HasTcm>;
59impl Cpu1HasTcmR {
60 #[doc = "Get enumerated values variant"]
61 #[inline(always)]
62 pub const fn variant(&self) -> Cpu1HasTcm {
63 match self.bits {
64 false => Cpu1HasTcm::No,
65 true => Cpu1HasTcm::Yes,
66 }
67 }
68 #[doc = "CPU 1 does not have Data TCM"]
69 #[inline(always)]
70 pub fn is_no(&self) -> bool {
71 *self == Cpu1HasTcm::No
72 }
73 #[doc = "CPU 1 has Data TCM"]
74 #[inline(always)]
75 pub fn is_yes(&self) -> bool {
76 *self == Cpu1HasTcm::Yes
77 }
78}
79#[doc = "Whether CryptoCell Included:\n\nValue on reset: 0"]
80#[derive(Clone, Copy, Debug, PartialEq, Eq)]
81pub enum HasCrypto {
82 #[doc = "0: CryptoCell Not Included"]
83 No = 0,
84 #[doc = "1: CryptoCell Included"]
85 Yes = 1,
86}
87impl From<HasCrypto> for bool {
88 #[inline(always)]
89 fn from(variant: HasCrypto) -> Self {
90 variant as u8 != 0
91 }
92}
93#[doc = "Field `HAS_CRYPTO` reader - Whether CryptoCell Included:"]
94pub type HasCryptoR = crate::BitReader<HasCrypto>;
95impl HasCryptoR {
96 #[doc = "Get enumerated values variant"]
97 #[inline(always)]
98 pub const fn variant(&self) -> HasCrypto {
99 match self.bits {
100 false => HasCrypto::No,
101 true => HasCrypto::Yes,
102 }
103 }
104 #[doc = "CryptoCell Not Included"]
105 #[inline(always)]
106 pub fn is_no(&self) -> bool {
107 *self == HasCrypto::No
108 }
109 #[doc = "CryptoCell Included"]
110 #[inline(always)]
111 pub fn is_yes(&self) -> bool {
112 *self == HasCrypto::Yes
113 }
114}
115#[doc = "Field `CPU0_TCM_BANK_NUM` reader - The SRAM Bank that maps CPU0 Data TCM"]
116pub type Cpu0TcmBankNumR = crate::FieldReader;
117#[doc = "Number of SRAM banks\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119#[repr(u8)]
120pub enum Cpu1TcmBankNum {
121 #[doc = "3: 4 SRAM Banks"]
122 Four = 3,
123 #[doc = "2: 3 SRAM Banks"]
124 Three = 2,
125 #[doc = "1: 2 SRAM Banks"]
126 Two = 1,
127 #[doc = "0: Otherwise"]
128 Otherwise = 0,
129}
130impl From<Cpu1TcmBankNum> for u8 {
131 #[inline(always)]
132 fn from(variant: Cpu1TcmBankNum) -> Self {
133 variant as _
134 }
135}
136impl crate::FieldSpec for Cpu1TcmBankNum {
137 type Ux = u8;
138}
139impl crate::IsEnum for Cpu1TcmBankNum {}
140#[doc = "Field `CPU1_TCM_BANK_NUM` reader - Number of SRAM banks"]
141pub type Cpu1TcmBankNumR = crate::FieldReader<Cpu1TcmBankNum>;
142impl Cpu1TcmBankNumR {
143 #[doc = "Get enumerated values variant"]
144 #[inline(always)]
145 pub const fn variant(&self) -> Option<Cpu1TcmBankNum> {
146 match self.bits {
147 3 => Some(Cpu1TcmBankNum::Four),
148 2 => Some(Cpu1TcmBankNum::Three),
149 1 => Some(Cpu1TcmBankNum::Two),
150 0 => Some(Cpu1TcmBankNum::Otherwise),
151 _ => None,
152 }
153 }
154 #[doc = "4 SRAM Banks"]
155 #[inline(always)]
156 pub fn is_four(&self) -> bool {
157 *self == Cpu1TcmBankNum::Four
158 }
159 #[doc = "3 SRAM Banks"]
160 #[inline(always)]
161 pub fn is_three(&self) -> bool {
162 *self == Cpu1TcmBankNum::Three
163 }
164 #[doc = "2 SRAM Banks"]
165 #[inline(always)]
166 pub fn is_two(&self) -> bool {
167 *self == Cpu1TcmBankNum::Two
168 }
169 #[doc = "Otherwise"]
170 #[inline(always)]
171 pub fn is_otherwise(&self) -> bool {
172 *self == Cpu1TcmBankNum::Otherwise
173 }
174}
175#[doc = "CPU 0 Core Type\n\nValue on reset: 0"]
176#[derive(Clone, Copy, Debug, PartialEq, Eq)]
177#[repr(u8)]
178pub enum Cpu0Type {
179 #[doc = "0: Does Not Exist"]
180 NotExist = 0,
181 #[doc = "2: Cortex-M33 Core"]
182 Cm33 = 2,
183}
184impl From<Cpu0Type> for u8 {
185 #[inline(always)]
186 fn from(variant: Cpu0Type) -> Self {
187 variant as _
188 }
189}
190impl crate::FieldSpec for Cpu0Type {
191 type Ux = u8;
192}
193impl crate::IsEnum for Cpu0Type {}
194#[doc = "Field `CPU0_TYPE` reader - CPU 0 Core Type"]
195pub type Cpu0TypeR = crate::FieldReader<Cpu0Type>;
196impl Cpu0TypeR {
197 #[doc = "Get enumerated values variant"]
198 #[inline(always)]
199 pub const fn variant(&self) -> Option<Cpu0Type> {
200 match self.bits {
201 0 => Some(Cpu0Type::NotExist),
202 2 => Some(Cpu0Type::Cm33),
203 _ => None,
204 }
205 }
206 #[doc = "Does Not Exist"]
207 #[inline(always)]
208 pub fn is_not_exist(&self) -> bool {
209 *self == Cpu0Type::NotExist
210 }
211 #[doc = "Cortex-M33 Core"]
212 #[inline(always)]
213 pub fn is_cm33(&self) -> bool {
214 *self == Cpu0Type::Cm33
215 }
216}
217#[doc = "CPU 1 Core Type\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219#[repr(u8)]
220pub enum Cpu1Type {
221 #[doc = "0: Does Not Exist"]
222 NotExist = 0,
223 #[doc = "2: Cortex-M33 Core"]
224 Cm33 = 2,
225}
226impl From<Cpu1Type> for u8 {
227 #[inline(always)]
228 fn from(variant: Cpu1Type) -> Self {
229 variant as _
230 }
231}
232impl crate::FieldSpec for Cpu1Type {
233 type Ux = u8;
234}
235impl crate::IsEnum for Cpu1Type {}
236#[doc = "Field `CPU1_TYPE` reader - CPU 1 Core Type"]
237pub type Cpu1TypeR = crate::FieldReader<Cpu1Type>;
238impl Cpu1TypeR {
239 #[doc = "Get enumerated values variant"]
240 #[inline(always)]
241 pub const fn variant(&self) -> Option<Cpu1Type> {
242 match self.bits {
243 0 => Some(Cpu1Type::NotExist),
244 2 => Some(Cpu1Type::Cm33),
245 _ => None,
246 }
247 }
248 #[doc = "Does Not Exist"]
249 #[inline(always)]
250 pub fn is_not_exist(&self) -> bool {
251 *self == Cpu1Type::NotExist
252 }
253 #[doc = "Cortex-M33 Core"]
254 #[inline(always)]
255 pub fn is_cm33(&self) -> bool {
256 *self == Cpu1Type::Cm33
257 }
258}
259impl R {
260 #[doc = "Bits 0:3 - SRAM Number of Banks"]
261 #[inline(always)]
262 pub fn sram_num_bank(&self) -> SramNumBankR {
263 SramNumBankR::new((self.bits & 0x0f) as u8)
264 }
265 #[doc = "Bits 4:8 - SRAM Bank Address Width"]
266 #[inline(always)]
267 pub fn sram_addr_width(&self) -> SramAddrWidthR {
268 SramAddrWidthR::new(((self.bits >> 4) & 0x1f) as u8)
269 }
270 #[doc = "Bit 9 - CPU 0 has Data TCM:"]
271 #[inline(always)]
272 pub fn cpu0_has_tcm(&self) -> Cpu0HasTcmR {
273 Cpu0HasTcmR::new(((self.bits >> 9) & 1) != 0)
274 }
275 #[doc = "Bit 10 - CPU 1 has Data TCM:"]
276 #[inline(always)]
277 pub fn cpu1_has_tcm(&self) -> Cpu1HasTcmR {
278 Cpu1HasTcmR::new(((self.bits >> 10) & 1) != 0)
279 }
280 #[doc = "Bit 12 - Whether CryptoCell Included:"]
281 #[inline(always)]
282 pub fn has_crypto(&self) -> HasCryptoR {
283 HasCryptoR::new(((self.bits >> 12) & 1) != 0)
284 }
285 #[doc = "Bits 16:19 - The SRAM Bank that maps CPU0 Data TCM"]
286 #[inline(always)]
287 pub fn cpu0_tcm_bank_num(&self) -> Cpu0TcmBankNumR {
288 Cpu0TcmBankNumR::new(((self.bits >> 16) & 0x0f) as u8)
289 }
290 #[doc = "Bits 20:23 - Number of SRAM banks"]
291 #[inline(always)]
292 pub fn cpu1_tcm_bank_num(&self) -> Cpu1TcmBankNumR {
293 Cpu1TcmBankNumR::new(((self.bits >> 20) & 0x0f) as u8)
294 }
295 #[doc = "Bits 24:27 - CPU 0 Core Type"]
296 #[inline(always)]
297 pub fn cpu0_type(&self) -> Cpu0TypeR {
298 Cpu0TypeR::new(((self.bits >> 24) & 0x0f) as u8)
299 }
300 #[doc = "Bits 28:31 - CPU 1 Core Type"]
301 #[inline(always)]
302 pub fn cpu1_type(&self) -> Cpu1TypeR {
303 Cpu1TypeR::new(((self.bits >> 28) & 0x0f) as u8)
304 }
305}
306#[doc = "System Hardware Configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
307pub struct SysConfigSpec;
308impl crate::RegisterSpec for SysConfigSpec {
309 type Ux = u32;
310}
311#[doc = "`read()` method returns [`sys_config::R`](R) reader structure"]
312impl crate::Readable for SysConfigSpec {}
313#[doc = "`reset()` method sets SYS_CONFIG to value 0"]
314impl crate::Resettable for SysConfigSpec {
315 const RESET_VALUE: u32 = 0;
316}