Type Definition muscab1_pac::scc::clk_ctrl_enable::W

type W = W<u32, CLK_CTRL_ENABLE>;

Writer for register CLK_CTRL_ENABLE

Methods

impl W

pub fn ctrl_enable_1hz(&mut self) -> CTRL_ENABLE_1HZ_W

Bit 0 - 0: Disable; 1: Enable

pub fn ctrl_enable_dapswclk(&mut self) -> CTRL_ENABLE_DAPSWCLK_W

Bit 1 - 0: Disable; 1: Enable

pub fn ctrl_enable_gpiohclk(&mut self) -> CTRL_ENABLE_GPIOHCLK_W

Bit 2 - 0: Disable; 1: Enable

pub fn ctrl_enable_i2sclk0(&mut self) -> CTRL_ENABLE_I2SCLK0_W

Bit 3 - 0: Disable; 1: Enable

pub fn ctrl_enable_i2sclk1(&mut self) -> CTRL_ENABLE_I2SCLK1_W

Bit 4 - 0: Disable; 1: Enable

pub fn ctrl_enable_i2sclk2(&mut self) -> CTRL_ENABLE_I2SCLK2_W

Bit 5 - 0: Disable; 1: Enable

pub fn ctrl_enable_mainclk(&mut self) -> CTRL_ENABLE_MAINCLK_W

Bit 8 - 0: Disable; 1: Enable

pub fn ctrl_enable_qspi_phy_clk(&mut self) -> CTRL_ENABLE_QSPI_PHY_CLK_W

Bit 9 - 0: Disable; 1: Enable

pub fn ctrl_enable_refclk(&mut self) -> CTRL_ENABLE_REFCLK_W

Bit 10 - 0: Disable; 1: Enable

pub fn ctrl_enable_rm38kclk(&mut self) -> CTRL_ENABLE_RM38KCLK_W

Bit 11 - 0: Disable; 1: Enable

pub fn ctrl_enable_sccclk(&mut self) -> CTRL_ENABLE_SCCCLK_W

Bit 12 - 0: Disable; 1: Enable

pub fn ctrl_enable_sdphyclk(&mut self) -> CTRL_ENABLE_SDPHYCLK_W

Bit 13 - 0: Disable; 1: Enable

pub fn ctrl_enable_testclk(&mut self) -> CTRL_ENABLE_TESTCLK_W

Bit 15 - 0: Disable; 1: Enable