[−][src]Type Definition muscab1_pac::qspifctrl::qspicfg::W
type W = W<u32, QSPICFG>;
Writer for register QSPICFG
Methods
impl W[src]
pub fn piplidle(&mut self) -> PIPLIDLE_W[src]
Bit 31 - Serial Interface and QSPI pipeline is IDLE
pub fn piplphyen(&mut self) -> PIPLPHYEN_W[src]
Bit 25 - Pipeline PHY Mode enable
pub fn dtren(&mut self) -> DTREN_W[src]
Bit 24 - Enable DTR Protocol
pub fn ahbdecen(&mut self) -> AHBDECEN_W[src]
Bit 23 - Enable AHB Decoder
pub fn mamobrdiv(&mut self) -> MAMOBRDIV_W[src]
Bits 19:22 - Master mode baud rate divisor (2 to 32)
pub fn entrxipmodeimm(&mut self) -> ENTRXIPMODEIMM_W[src]
Bit 18 - Enter XIP Mode immediately
pub fn entrxipmodeonr(&mut self) -> ENTRXIPMODEONR_W[src]
Bit 17 - Enter XIP Mode on next READ
pub fn enahbaddrrm(&mut self) -> ENAHBADDRRM_W[src]
Bit 16 - Enable AHB Address Re-mapping
pub fn endmapif(&mut self) -> ENDMAPIF_W[src]
Bit 15 - Enable DMA Peripheral Interface
pub fn wppindrv(&mut self) -> WPPINDRV_W[src]
Bit 14 - Set to drive the WP pin of Flash device
pub fn percslines(&mut self) -> PERCSLINES_W[src]
Bits 10:13 - Peripheral chip select lines
pub fn perseldec(&mut self) -> PERSELDEC_W[src]
Bit 9 - Peripheral select decode
pub fn legipmodeen(&mut self) -> LEGIPMODEEN_W[src]
Bit 8 - Legacy IP Mode Enable
pub fn endiraccctr(&mut self) -> ENDIRACCCTR_W[src]
Bit 7 - Enable Direct Access Controller
pub fn phymodeen(&mut self) -> PHYMODEEN_W[src]
Bit 3 - PHY Mode enable
pub fn clkphase(&mut self) -> CLKPHASE_W[src]
Bit 2 - Clock phase, this maps to the standard SPI CPHA transfer format
pub fn clkpolarity(&mut self) -> CLKPOLARITY_W[src]
Bit 1 - Clock polarity outside SPI word. This maps to the standard SPI CPOL transfer format
pub fn qspien(&mut self) -> QSPIEN_W[src]
Bit 0 - QSPI Enable