mtb_pac_psoc6_03/
lib.rs

1/*
2(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
3
4    or an affiliate of Cypress Semiconductor Corporation.
5
6
7
8    SPDX-License-Identifier: Apache-2.0
9
10
11
12    Licensed under the Apache License, Version 2.0 (the "License");
13
14    you may not use this file except in compliance with the License.
15
16    You may obtain a copy of the License at
17
18
19
20      http://www.apache.org/licenses/LICENSE-2.0
21
22
23
24    Unless required by applicable law or agreed to in writing, software
25
26    distributed under the License is distributed on an "AS IS" BASIS,
27
28    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
29
30    See the License for the specific language governing permissions and
31
32    limitations under the License.
33*/
34// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:22:34 +0000
35#![no_std]
36#![allow(non_camel_case_types)]
37#![doc = "PSOC6_03"]
38pub mod common;
39pub use common::*;
40
41#[cfg(feature = "backup")]
42pub mod backup;
43#[cfg(feature = "canfd0")]
44pub mod canfd;
45#[cfg(feature = "cpuss")]
46pub mod cpuss;
47#[cfg(feature = "crypto")]
48pub mod crypto;
49#[cfg(feature = "csd0")]
50pub mod csd;
51#[cfg(feature = "dmac")]
52pub mod dmac;
53#[cfg(feature = "dw0")]
54pub mod dw;
55#[cfg(feature = "efuse")]
56pub mod efuse;
57#[cfg(feature = "fault")]
58pub mod fault;
59#[cfg(feature = "flashc")]
60pub mod flashc;
61#[cfg(feature = "gpio")]
62pub mod gpio;
63#[cfg(feature = "hsiom")]
64pub mod hsiom;
65#[cfg(feature = "ipc")]
66pub mod ipc;
67#[cfg(feature = "lcd0")]
68pub mod lcd;
69#[cfg(feature = "lpcomp")]
70pub mod lpcomp;
71#[cfg(feature = "pass")]
72pub mod pass;
73#[cfg(feature = "peri")]
74pub mod peri;
75#[cfg(feature = "peri_ms")]
76pub mod peri_ms;
77#[cfg(feature = "prot")]
78pub mod prot;
79#[cfg(feature = "sar")]
80pub mod sar;
81#[cfg(feature = "scb0")]
82pub mod scb;
83#[cfg(feature = "sdhc0")]
84pub mod sdhc;
85#[cfg(feature = "smartio")]
86pub mod smartio;
87#[cfg(feature = "smif0")]
88pub mod smif;
89#[cfg(feature = "srss")]
90pub mod srss;
91#[cfg(feature = "tcpwm0")]
92pub mod tcpwm;
93#[cfg(feature = "usbfs0")]
94pub mod usbfs;
95
96#[cfg(feature = "peri")]
97#[derive(Copy, Clone, Eq, PartialEq)]
98pub struct Peri {
99    ptr: *mut u8,
100}
101#[cfg(feature = "peri")]
102pub const PERI: self::Peri = self::Peri {
103    ptr: 0x40000000u32 as _,
104};
105#[cfg(feature = "peri_ms")]
106#[derive(Copy, Clone, Eq, PartialEq)]
107pub struct PeriMs {
108    ptr: *mut u8,
109}
110#[cfg(feature = "peri_ms")]
111pub const PERI_MS: self::PeriMs = self::PeriMs {
112    ptr: 0x40010000u32 as _,
113};
114#[cfg(feature = "crypto")]
115#[derive(Copy, Clone, Eq, PartialEq)]
116pub struct Crypto {
117    ptr: *mut u8,
118}
119#[cfg(feature = "crypto")]
120pub const CRYPTO: self::Crypto = self::Crypto {
121    ptr: 0x40100000u32 as _,
122};
123#[cfg(feature = "cpuss")]
124#[derive(Copy, Clone, Eq, PartialEq)]
125pub struct Cpuss {
126    ptr: *mut u8,
127}
128#[cfg(feature = "cpuss")]
129pub const CPUSS: self::Cpuss = self::Cpuss {
130    ptr: 0x40200000u32 as _,
131};
132#[cfg(feature = "fault")]
133#[derive(Copy, Clone, Eq, PartialEq)]
134pub struct Fault {
135    ptr: *mut u8,
136}
137#[cfg(feature = "fault")]
138pub const FAULT: self::Fault = self::Fault {
139    ptr: 0x40210000u32 as _,
140};
141#[cfg(feature = "ipc")]
142#[derive(Copy, Clone, Eq, PartialEq)]
143pub struct Ipc {
144    ptr: *mut u8,
145}
146#[cfg(feature = "ipc")]
147pub const IPC: self::Ipc = self::Ipc {
148    ptr: 0x40220000u32 as _,
149};
150#[cfg(feature = "prot")]
151#[derive(Copy, Clone, Eq, PartialEq)]
152pub struct Prot {
153    ptr: *mut u8,
154}
155#[cfg(feature = "prot")]
156pub const PROT: self::Prot = self::Prot {
157    ptr: 0x40230000u32 as _,
158};
159#[cfg(feature = "flashc")]
160#[derive(Copy, Clone, Eq, PartialEq)]
161pub struct Flashc {
162    ptr: *mut u8,
163}
164#[cfg(feature = "flashc")]
165pub const FLASHC: self::Flashc = self::Flashc {
166    ptr: 0x40240000u32 as _,
167};
168#[cfg(feature = "srss")]
169#[derive(Copy, Clone, Eq, PartialEq)]
170pub struct Srss {
171    ptr: *mut u8,
172}
173#[cfg(feature = "srss")]
174pub const SRSS: self::Srss = self::Srss {
175    ptr: 0x40260000u32 as _,
176};
177#[cfg(feature = "backup")]
178#[derive(Copy, Clone, Eq, PartialEq)]
179pub struct Backup {
180    ptr: *mut u8,
181}
182#[cfg(feature = "backup")]
183pub const BACKUP: self::Backup = self::Backup {
184    ptr: 0x40270000u32 as _,
185};
186#[cfg(feature = "dw0")]
187#[derive(Copy, Clone, Eq, PartialEq)]
188pub struct Dw {
189    ptr: *mut u8,
190}
191#[cfg(feature = "dw0")]
192pub const DW0: self::Dw = self::Dw {
193    ptr: 0x40280000u32 as _,
194};
195#[cfg(feature = "dw1")]
196pub const DW1: self::Dw = self::Dw {
197    ptr: 0x40290000u32 as _,
198};
199#[cfg(feature = "dmac")]
200#[derive(Copy, Clone, Eq, PartialEq)]
201pub struct Dmac {
202    ptr: *mut u8,
203}
204#[cfg(feature = "dmac")]
205pub const DMAC: self::Dmac = self::Dmac {
206    ptr: 0x402a0000u32 as _,
207};
208#[cfg(feature = "efuse")]
209#[derive(Copy, Clone, Eq, PartialEq)]
210pub struct Efuse {
211    ptr: *mut u8,
212}
213#[cfg(feature = "efuse")]
214pub const EFUSE: self::Efuse = self::Efuse {
215    ptr: 0x402c0000u32 as _,
216};
217#[cfg(feature = "hsiom")]
218#[derive(Copy, Clone, Eq, PartialEq)]
219pub struct Hsiom {
220    ptr: *mut u8,
221}
222#[cfg(feature = "hsiom")]
223pub const HSIOM: self::Hsiom = self::Hsiom {
224    ptr: 0x40300000u32 as _,
225};
226#[cfg(feature = "gpio")]
227#[derive(Copy, Clone, Eq, PartialEq)]
228pub struct Gpio {
229    ptr: *mut u8,
230}
231#[cfg(feature = "gpio")]
232pub const GPIO: self::Gpio = self::Gpio {
233    ptr: 0x40310000u32 as _,
234};
235#[cfg(feature = "smartio")]
236#[derive(Copy, Clone, Eq, PartialEq)]
237pub struct Smartio {
238    ptr: *mut u8,
239}
240#[cfg(feature = "smartio")]
241pub const SMARTIO: self::Smartio = self::Smartio {
242    ptr: 0x40320000u32 as _,
243};
244#[cfg(feature = "lpcomp")]
245#[derive(Copy, Clone, Eq, PartialEq)]
246pub struct Lpcomp {
247    ptr: *mut u8,
248}
249#[cfg(feature = "lpcomp")]
250pub const LPCOMP: self::Lpcomp = self::Lpcomp {
251    ptr: 0x40350000u32 as _,
252};
253#[cfg(feature = "csd0")]
254#[derive(Copy, Clone, Eq, PartialEq)]
255pub struct Csd {
256    ptr: *mut u8,
257}
258#[cfg(feature = "csd0")]
259pub const CSD0: self::Csd = self::Csd {
260    ptr: 0x40360000u32 as _,
261};
262#[cfg(feature = "tcpwm0")]
263#[derive(Copy, Clone, Eq, PartialEq)]
264pub struct Tcpwm {
265    ptr: *mut u8,
266}
267#[cfg(feature = "tcpwm0")]
268pub const TCPWM0: self::Tcpwm = self::Tcpwm {
269    ptr: 0x40380000u32 as _,
270};
271#[cfg(feature = "tcpwm1")]
272pub const TCPWM1: self::Tcpwm = self::Tcpwm {
273    ptr: 0x40390000u32 as _,
274};
275#[cfg(feature = "lcd0")]
276#[derive(Copy, Clone, Eq, PartialEq)]
277pub struct Lcd {
278    ptr: *mut u8,
279}
280#[cfg(feature = "lcd0")]
281pub const LCD0: self::Lcd = self::Lcd {
282    ptr: 0x403b0000u32 as _,
283};
284#[cfg(feature = "usbfs0")]
285#[derive(Copy, Clone, Eq, PartialEq)]
286pub struct Usbfs {
287    ptr: *mut u8,
288}
289#[cfg(feature = "usbfs0")]
290pub const USBFS0: self::Usbfs = self::Usbfs {
291    ptr: 0x403f0000u32 as _,
292};
293#[cfg(feature = "smif0")]
294#[derive(Copy, Clone, Eq, PartialEq)]
295pub struct Smif {
296    ptr: *mut u8,
297}
298#[cfg(feature = "smif0")]
299pub const SMIF0: self::Smif = self::Smif {
300    ptr: 0x40420000u32 as _,
301};
302#[cfg(feature = "sdhc0")]
303#[derive(Copy, Clone, Eq, PartialEq)]
304pub struct Sdhc {
305    ptr: *mut u8,
306}
307#[cfg(feature = "sdhc0")]
308pub const SDHC0: self::Sdhc = self::Sdhc {
309    ptr: 0x40460000u32 as _,
310};
311#[cfg(feature = "canfd0")]
312#[derive(Copy, Clone, Eq, PartialEq)]
313pub struct Canfd {
314    ptr: *mut u8,
315}
316#[cfg(feature = "canfd0")]
317pub const CANFD0: self::Canfd = self::Canfd {
318    ptr: 0x40520000u32 as _,
319};
320#[cfg(feature = "scb0")]
321#[derive(Copy, Clone, Eq, PartialEq)]
322pub struct Scb {
323    ptr: *mut u8,
324}
325#[cfg(feature = "scb0")]
326pub const SCB0: self::Scb = self::Scb {
327    ptr: 0x40600000u32 as _,
328};
329#[cfg(feature = "scb1")]
330pub const SCB1: self::Scb = self::Scb {
331    ptr: 0x40610000u32 as _,
332};
333#[cfg(feature = "scb2")]
334pub const SCB2: self::Scb = self::Scb {
335    ptr: 0x40620000u32 as _,
336};
337#[cfg(feature = "scb3")]
338pub const SCB3: self::Scb = self::Scb {
339    ptr: 0x40630000u32 as _,
340};
341#[cfg(feature = "scb4")]
342pub const SCB4: self::Scb = self::Scb {
343    ptr: 0x40640000u32 as _,
344};
345#[cfg(feature = "scb5")]
346pub const SCB5: self::Scb = self::Scb {
347    ptr: 0x40650000u32 as _,
348};
349#[cfg(feature = "scb6")]
350pub const SCB6: self::Scb = self::Scb {
351    ptr: 0x40660000u32 as _,
352};
353#[cfg(feature = "sar")]
354#[derive(Copy, Clone, Eq, PartialEq)]
355pub struct Sar {
356    ptr: *mut u8,
357}
358#[cfg(feature = "sar")]
359pub const SAR: self::Sar = self::Sar {
360    ptr: 0x409d0000u32 as _,
361};
362#[cfg(feature = "pass")]
363#[derive(Copy, Clone, Eq, PartialEq)]
364pub struct Pass {
365    ptr: *mut u8,
366}
367#[cfg(feature = "pass")]
368pub const PASS: self::Pass = self::Pass {
369    ptr: 0x409f0000u32 as _,
370};
371
372pub use cortex_m::peripheral::Peripherals as CorePeripherals;
373pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
374#[doc = "Number available in the NVIC for configuring priority"]
375pub const NVIC_PRIO_BITS: u8 = 3;
376#[doc(hidden)]
377pub union Vector {
378    _handler: unsafe extern "C" fn(),
379    _reserved: u32,
380}
381#[cfg(feature = "rt")]
382pub use self::Interrupt as interrupt;
383#[cfg(feature = "rt")]
384pub use cortex_m_rt::interrupt;
385#[cfg(feature = "rt")]
386pub mod interrupt_handlers {
387    extern "C" {
388        pub fn IOSS_INTERRUPTS_GPIO_0();
389        pub fn IOSS_INTERRUPTS_GPIO_2();
390        pub fn IOSS_INTERRUPTS_GPIO_3();
391        pub fn IOSS_INTERRUPTS_GPIO_5();
392        pub fn IOSS_INTERRUPTS_GPIO_6();
393        pub fn IOSS_INTERRUPTS_GPIO_7();
394        pub fn IOSS_INTERRUPTS_GPIO_8();
395        pub fn IOSS_INTERRUPTS_GPIO_9();
396        pub fn IOSS_INTERRUPTS_GPIO_10();
397        pub fn IOSS_INTERRUPTS_GPIO_11();
398        pub fn IOSS_INTERRUPTS_GPIO_12();
399        pub fn IOSS_INTERRUPTS_GPIO_14();
400        pub fn IOSS_INTERRUPT_GPIO();
401        pub fn IOSS_INTERRUPT_VDD();
402        pub fn LPCOMP_INTERRUPT();
403        pub fn SCB_6_INTERRUPT();
404        pub fn SRSS_INTERRUPT_MCWDT_0();
405        pub fn SRSS_INTERRUPT_MCWDT_1();
406        pub fn SRSS_INTERRUPT_BACKUP();
407        pub fn SRSS_INTERRUPT();
408        pub fn CPUSS_INTERRUPTS_IPC_0();
409        pub fn CPUSS_INTERRUPTS_IPC_1();
410        pub fn CPUSS_INTERRUPTS_IPC_2();
411        pub fn CPUSS_INTERRUPTS_IPC_3();
412        pub fn CPUSS_INTERRUPTS_IPC_4();
413        pub fn CPUSS_INTERRUPTS_IPC_5();
414        pub fn CPUSS_INTERRUPTS_IPC_6();
415        pub fn CPUSS_INTERRUPTS_IPC_7();
416        pub fn CPUSS_INTERRUPTS_IPC_8();
417        pub fn CPUSS_INTERRUPTS_IPC_9();
418        pub fn CPUSS_INTERRUPTS_IPC_10();
419        pub fn CPUSS_INTERRUPTS_IPC_11();
420        pub fn CPUSS_INTERRUPTS_IPC_12();
421        pub fn CPUSS_INTERRUPTS_IPC_13();
422        pub fn CPUSS_INTERRUPTS_IPC_14();
423        pub fn CPUSS_INTERRUPTS_IPC_15();
424        pub fn SCB_0_INTERRUPT();
425        pub fn SCB_1_INTERRUPT();
426        pub fn SCB_2_INTERRUPT();
427        pub fn SCB_3_INTERRUPT();
428        pub fn SCB_4_INTERRUPT();
429        pub fn SCB_5_INTERRUPT();
430        pub fn CSD_INTERRUPT();
431        pub fn CPUSS_INTERRUPTS_DMAC_0();
432        pub fn CPUSS_INTERRUPTS_DMAC_1();
433        pub fn CPUSS_INTERRUPTS_DW0_0();
434        pub fn CPUSS_INTERRUPTS_DW0_1();
435        pub fn CPUSS_INTERRUPTS_DW0_2();
436        pub fn CPUSS_INTERRUPTS_DW0_3();
437        pub fn CPUSS_INTERRUPTS_DW0_4();
438        pub fn CPUSS_INTERRUPTS_DW0_5();
439        pub fn CPUSS_INTERRUPTS_DW0_6();
440        pub fn CPUSS_INTERRUPTS_DW0_7();
441        pub fn CPUSS_INTERRUPTS_DW0_8();
442        pub fn CPUSS_INTERRUPTS_DW0_9();
443        pub fn CPUSS_INTERRUPTS_DW0_10();
444        pub fn CPUSS_INTERRUPTS_DW0_11();
445        pub fn CPUSS_INTERRUPTS_DW0_12();
446        pub fn CPUSS_INTERRUPTS_DW0_13();
447        pub fn CPUSS_INTERRUPTS_DW0_14();
448        pub fn CPUSS_INTERRUPTS_DW0_15();
449        pub fn CPUSS_INTERRUPTS_DW0_16();
450        pub fn CPUSS_INTERRUPTS_DW0_17();
451        pub fn CPUSS_INTERRUPTS_DW0_18();
452        pub fn CPUSS_INTERRUPTS_DW0_19();
453        pub fn CPUSS_INTERRUPTS_DW0_20();
454        pub fn CPUSS_INTERRUPTS_DW0_21();
455        pub fn CPUSS_INTERRUPTS_DW0_22();
456        pub fn CPUSS_INTERRUPTS_DW0_23();
457        pub fn CPUSS_INTERRUPTS_DW0_24();
458        pub fn CPUSS_INTERRUPTS_DW0_25();
459        pub fn CPUSS_INTERRUPTS_DW0_26();
460        pub fn CPUSS_INTERRUPTS_DW0_27();
461        pub fn CPUSS_INTERRUPTS_DW0_28();
462        pub fn CPUSS_INTERRUPTS_DW1_0();
463        pub fn CPUSS_INTERRUPTS_DW1_1();
464        pub fn CPUSS_INTERRUPTS_DW1_2();
465        pub fn CPUSS_INTERRUPTS_DW1_3();
466        pub fn CPUSS_INTERRUPTS_DW1_4();
467        pub fn CPUSS_INTERRUPTS_DW1_5();
468        pub fn CPUSS_INTERRUPTS_DW1_6();
469        pub fn CPUSS_INTERRUPTS_DW1_7();
470        pub fn CPUSS_INTERRUPTS_DW1_8();
471        pub fn CPUSS_INTERRUPTS_DW1_9();
472        pub fn CPUSS_INTERRUPTS_DW1_10();
473        pub fn CPUSS_INTERRUPTS_DW1_11();
474        pub fn CPUSS_INTERRUPTS_DW1_12();
475        pub fn CPUSS_INTERRUPTS_DW1_13();
476        pub fn CPUSS_INTERRUPTS_DW1_14();
477        pub fn CPUSS_INTERRUPTS_DW1_15();
478        pub fn CPUSS_INTERRUPTS_DW1_16();
479        pub fn CPUSS_INTERRUPTS_DW1_17();
480        pub fn CPUSS_INTERRUPTS_DW1_18();
481        pub fn CPUSS_INTERRUPTS_DW1_19();
482        pub fn CPUSS_INTERRUPTS_DW1_20();
483        pub fn CPUSS_INTERRUPTS_DW1_21();
484        pub fn CPUSS_INTERRUPTS_DW1_22();
485        pub fn CPUSS_INTERRUPTS_DW1_23();
486        pub fn CPUSS_INTERRUPTS_DW1_24();
487        pub fn CPUSS_INTERRUPTS_DW1_25();
488        pub fn CPUSS_INTERRUPTS_DW1_26();
489        pub fn CPUSS_INTERRUPTS_DW1_27();
490        pub fn CPUSS_INTERRUPTS_DW1_28();
491        pub fn CPUSS_INTERRUPTS_FAULT_0();
492        pub fn CPUSS_INTERRUPTS_FAULT_1();
493        pub fn CPUSS_INTERRUPT_CRYPTO();
494        pub fn CPUSS_INTERRUPT_FM();
495        pub fn CPUSS_INTERRUPTS_CM4_FP();
496        pub fn CPUSS_INTERRUPTS_CM0_CTI_0();
497        pub fn CPUSS_INTERRUPTS_CM0_CTI_1();
498        pub fn CPUSS_INTERRUPTS_CM4_CTI_0();
499        pub fn CPUSS_INTERRUPTS_CM4_CTI_1();
500        pub fn TCPWM_0_INTERRUPTS_0();
501        pub fn TCPWM_0_INTERRUPTS_1();
502        pub fn TCPWM_0_INTERRUPTS_2();
503        pub fn TCPWM_0_INTERRUPTS_3();
504        pub fn TCPWM_1_INTERRUPTS_0();
505        pub fn TCPWM_1_INTERRUPTS_1();
506        pub fn TCPWM_1_INTERRUPTS_2();
507        pub fn TCPWM_1_INTERRUPTS_3();
508        pub fn TCPWM_1_INTERRUPTS_4();
509        pub fn TCPWM_1_INTERRUPTS_5();
510        pub fn TCPWM_1_INTERRUPTS_6();
511        pub fn TCPWM_1_INTERRUPTS_7();
512        pub fn PASS_INTERRUPT_SAR();
513        pub fn SMIF_INTERRUPT();
514        pub fn USB_INTERRUPT_HI();
515        pub fn USB_INTERRUPT_MED();
516        pub fn USB_INTERRUPT_LO();
517        pub fn SDHC_0_INTERRUPT_WAKEUP();
518        pub fn SDHC_0_INTERRUPT_GENERAL();
519        pub fn CANFD_0_INTERRUPT0();
520        pub fn CANFD_0_INTERRUPTS0_0();
521        pub fn CANFD_0_INTERRUPTS1_0();
522        pub fn CPUSS_INTERRUPTS_DW1_29();
523        pub fn CPUSS_INTERRUPTS_DW1_30();
524        pub fn CPUSS_INTERRUPTS_DW1_31();
525    }
526}
527#[cfg(feature = "rt")]
528#[doc(hidden)]
529#[link_section = ".vector_table.interrupts"]
530#[no_mangle]
531pub static __INTERRUPTS: [Vector; 174] = [
532    Vector {
533        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_0,
534    },
535    Vector { _reserved: 0 },
536    Vector {
537        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_2,
538    },
539    Vector {
540        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_3,
541    },
542    Vector { _reserved: 0 },
543    Vector {
544        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_5,
545    },
546    Vector {
547        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_6,
548    },
549    Vector {
550        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_7,
551    },
552    Vector {
553        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_8,
554    },
555    Vector {
556        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_9,
557    },
558    Vector {
559        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_10,
560    },
561    Vector {
562        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_11,
563    },
564    Vector {
565        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_12,
566    },
567    Vector { _reserved: 0 },
568    Vector {
569        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_14,
570    },
571    Vector {
572        _handler: interrupt_handlers::IOSS_INTERRUPT_GPIO,
573    },
574    Vector {
575        _handler: interrupt_handlers::IOSS_INTERRUPT_VDD,
576    },
577    Vector {
578        _handler: interrupt_handlers::LPCOMP_INTERRUPT,
579    },
580    Vector {
581        _handler: interrupt_handlers::SCB_6_INTERRUPT,
582    },
583    Vector {
584        _handler: interrupt_handlers::SRSS_INTERRUPT_MCWDT_0,
585    },
586    Vector {
587        _handler: interrupt_handlers::SRSS_INTERRUPT_MCWDT_1,
588    },
589    Vector {
590        _handler: interrupt_handlers::SRSS_INTERRUPT_BACKUP,
591    },
592    Vector {
593        _handler: interrupt_handlers::SRSS_INTERRUPT,
594    },
595    Vector {
596        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_0,
597    },
598    Vector {
599        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_1,
600    },
601    Vector {
602        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_2,
603    },
604    Vector {
605        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_3,
606    },
607    Vector {
608        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_4,
609    },
610    Vector {
611        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_5,
612    },
613    Vector {
614        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_6,
615    },
616    Vector {
617        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_7,
618    },
619    Vector {
620        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_8,
621    },
622    Vector {
623        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_9,
624    },
625    Vector {
626        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_10,
627    },
628    Vector {
629        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_11,
630    },
631    Vector {
632        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_12,
633    },
634    Vector {
635        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_13,
636    },
637    Vector {
638        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_14,
639    },
640    Vector {
641        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_15,
642    },
643    Vector {
644        _handler: interrupt_handlers::SCB_0_INTERRUPT,
645    },
646    Vector {
647        _handler: interrupt_handlers::SCB_1_INTERRUPT,
648    },
649    Vector {
650        _handler: interrupt_handlers::SCB_2_INTERRUPT,
651    },
652    Vector {
653        _handler: interrupt_handlers::SCB_3_INTERRUPT,
654    },
655    Vector {
656        _handler: interrupt_handlers::SCB_4_INTERRUPT,
657    },
658    Vector {
659        _handler: interrupt_handlers::SCB_5_INTERRUPT,
660    },
661    Vector { _reserved: 0 },
662    Vector { _reserved: 0 },
663    Vector { _reserved: 0 },
664    Vector { _reserved: 0 },
665    Vector { _reserved: 0 },
666    Vector { _reserved: 0 },
667    Vector {
668        _handler: interrupt_handlers::CSD_INTERRUPT,
669    },
670    Vector {
671        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DMAC_0,
672    },
673    Vector {
674        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DMAC_1,
675    },
676    Vector { _reserved: 0 },
677    Vector { _reserved: 0 },
678    Vector {
679        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_0,
680    },
681    Vector {
682        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_1,
683    },
684    Vector {
685        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_2,
686    },
687    Vector {
688        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_3,
689    },
690    Vector {
691        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_4,
692    },
693    Vector {
694        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_5,
695    },
696    Vector {
697        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_6,
698    },
699    Vector {
700        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_7,
701    },
702    Vector {
703        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_8,
704    },
705    Vector {
706        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_9,
707    },
708    Vector {
709        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_10,
710    },
711    Vector {
712        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_11,
713    },
714    Vector {
715        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_12,
716    },
717    Vector {
718        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_13,
719    },
720    Vector {
721        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_14,
722    },
723    Vector {
724        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_15,
725    },
726    Vector {
727        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_16,
728    },
729    Vector {
730        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_17,
731    },
732    Vector {
733        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_18,
734    },
735    Vector {
736        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_19,
737    },
738    Vector {
739        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_20,
740    },
741    Vector {
742        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_21,
743    },
744    Vector {
745        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_22,
746    },
747    Vector {
748        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_23,
749    },
750    Vector {
751        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_24,
752    },
753    Vector {
754        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_25,
755    },
756    Vector {
757        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_26,
758    },
759    Vector {
760        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_27,
761    },
762    Vector {
763        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_28,
764    },
765    Vector {
766        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_0,
767    },
768    Vector {
769        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_1,
770    },
771    Vector {
772        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_2,
773    },
774    Vector {
775        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_3,
776    },
777    Vector {
778        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_4,
779    },
780    Vector {
781        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_5,
782    },
783    Vector {
784        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_6,
785    },
786    Vector {
787        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_7,
788    },
789    Vector {
790        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_8,
791    },
792    Vector {
793        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_9,
794    },
795    Vector {
796        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_10,
797    },
798    Vector {
799        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_11,
800    },
801    Vector {
802        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_12,
803    },
804    Vector {
805        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_13,
806    },
807    Vector {
808        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_14,
809    },
810    Vector {
811        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_15,
812    },
813    Vector {
814        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_16,
815    },
816    Vector {
817        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_17,
818    },
819    Vector {
820        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_18,
821    },
822    Vector {
823        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_19,
824    },
825    Vector {
826        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_20,
827    },
828    Vector {
829        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_21,
830    },
831    Vector {
832        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_22,
833    },
834    Vector {
835        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_23,
836    },
837    Vector {
838        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_24,
839    },
840    Vector {
841        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_25,
842    },
843    Vector {
844        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_26,
845    },
846    Vector {
847        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_27,
848    },
849    Vector {
850        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_28,
851    },
852    Vector {
853        _handler: interrupt_handlers::CPUSS_INTERRUPTS_FAULT_0,
854    },
855    Vector {
856        _handler: interrupt_handlers::CPUSS_INTERRUPTS_FAULT_1,
857    },
858    Vector {
859        _handler: interrupt_handlers::CPUSS_INTERRUPT_CRYPTO,
860    },
861    Vector {
862        _handler: interrupt_handlers::CPUSS_INTERRUPT_FM,
863    },
864    Vector {
865        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM4_FP,
866    },
867    Vector {
868        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM0_CTI_0,
869    },
870    Vector {
871        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM0_CTI_1,
872    },
873    Vector {
874        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM4_CTI_0,
875    },
876    Vector {
877        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM4_CTI_1,
878    },
879    Vector {
880        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_0,
881    },
882    Vector {
883        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_1,
884    },
885    Vector {
886        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_2,
887    },
888    Vector {
889        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_3,
890    },
891    Vector { _reserved: 0 },
892    Vector { _reserved: 0 },
893    Vector { _reserved: 0 },
894    Vector { _reserved: 0 },
895    Vector {
896        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_0,
897    },
898    Vector {
899        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_1,
900    },
901    Vector {
902        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_2,
903    },
904    Vector {
905        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_3,
906    },
907    Vector {
908        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_4,
909    },
910    Vector {
911        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_5,
912    },
913    Vector {
914        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_6,
915    },
916    Vector {
917        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_7,
918    },
919    Vector { _reserved: 0 },
920    Vector { _reserved: 0 },
921    Vector { _reserved: 0 },
922    Vector { _reserved: 0 },
923    Vector { _reserved: 0 },
924    Vector { _reserved: 0 },
925    Vector { _reserved: 0 },
926    Vector { _reserved: 0 },
927    Vector { _reserved: 0 },
928    Vector { _reserved: 0 },
929    Vector { _reserved: 0 },
930    Vector { _reserved: 0 },
931    Vector { _reserved: 0 },
932    Vector { _reserved: 0 },
933    Vector { _reserved: 0 },
934    Vector { _reserved: 0 },
935    Vector {
936        _handler: interrupt_handlers::PASS_INTERRUPT_SAR,
937    },
938    Vector { _reserved: 0 },
939    Vector { _reserved: 0 },
940    Vector { _reserved: 0 },
941    Vector { _reserved: 0 },
942    Vector {
943        _handler: interrupt_handlers::SMIF_INTERRUPT,
944    },
945    Vector {
946        _handler: interrupt_handlers::USB_INTERRUPT_HI,
947    },
948    Vector {
949        _handler: interrupt_handlers::USB_INTERRUPT_MED,
950    },
951    Vector {
952        _handler: interrupt_handlers::USB_INTERRUPT_LO,
953    },
954    Vector {
955        _handler: interrupt_handlers::SDHC_0_INTERRUPT_WAKEUP,
956    },
957    Vector {
958        _handler: interrupt_handlers::SDHC_0_INTERRUPT_GENERAL,
959    },
960    Vector { _reserved: 0 },
961    Vector { _reserved: 0 },
962    Vector {
963        _handler: interrupt_handlers::CANFD_0_INTERRUPT0,
964    },
965    Vector {
966        _handler: interrupt_handlers::CANFD_0_INTERRUPTS0_0,
967    },
968    Vector {
969        _handler: interrupt_handlers::CANFD_0_INTERRUPTS1_0,
970    },
971    Vector {
972        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_29,
973    },
974    Vector {
975        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_30,
976    },
977    Vector {
978        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_31,
979    },
980];
981#[doc = "Enumeration of all the interrupts."]
982#[derive(Copy, Clone, Debug, PartialEq, Eq)]
983#[repr(u16)]
984pub enum Interrupt {
985    #[doc = "GPIO Port Interrupt #0"]
986    IOSS_INTERRUPTS_GPIO_0 = 0,
987
988    #[doc = "GPIO Port Interrupt #2"]
989    IOSS_INTERRUPTS_GPIO_2 = 2,
990
991    #[doc = "GPIO Port Interrupt #3"]
992    IOSS_INTERRUPTS_GPIO_3 = 3,
993
994    #[doc = "GPIO Port Interrupt #5"]
995    IOSS_INTERRUPTS_GPIO_5 = 5,
996
997    #[doc = "GPIO Port Interrupt #6"]
998    IOSS_INTERRUPTS_GPIO_6 = 6,
999
1000    #[doc = "GPIO Port Interrupt #7"]
1001    IOSS_INTERRUPTS_GPIO_7 = 7,
1002
1003    #[doc = "GPIO Port Interrupt #8"]
1004    IOSS_INTERRUPTS_GPIO_8 = 8,
1005
1006    #[doc = "GPIO Port Interrupt #9"]
1007    IOSS_INTERRUPTS_GPIO_9 = 9,
1008
1009    #[doc = "GPIO Port Interrupt #10"]
1010    IOSS_INTERRUPTS_GPIO_10 = 10,
1011
1012    #[doc = "GPIO Port Interrupt #11"]
1013    IOSS_INTERRUPTS_GPIO_11 = 11,
1014
1015    #[doc = "GPIO Port Interrupt #12"]
1016    IOSS_INTERRUPTS_GPIO_12 = 12,
1017
1018    #[doc = "GPIO Port Interrupt #14"]
1019    IOSS_INTERRUPTS_GPIO_14 = 14,
1020
1021    #[doc = "GPIO All Ports"]
1022    IOSS_INTERRUPT_GPIO = 15,
1023
1024    #[doc = "GPIO Supply Detect Interrupt"]
1025    IOSS_INTERRUPT_VDD = 16,
1026
1027    #[doc = "Low Power Comparator Interrupt"]
1028    LPCOMP_INTERRUPT = 17,
1029
1030    #[doc = "Serial Communication Block #6 (DeepSleep capable)"]
1031    SCB_6_INTERRUPT = 18,
1032
1033    #[doc = "Multi Counter Watchdog Timer interrupt"]
1034    SRSS_INTERRUPT_MCWDT_0 = 19,
1035
1036    #[doc = "Multi Counter Watchdog Timer interrupt"]
1037    SRSS_INTERRUPT_MCWDT_1 = 20,
1038
1039    #[doc = "Backup domain interrupt"]
1040    SRSS_INTERRUPT_BACKUP = 21,
1041
1042    #[doc = "Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)"]
1043    SRSS_INTERRUPT = 22,
1044
1045    #[doc = "CPUSS Inter Process Communication Interrupt #0"]
1046    CPUSS_INTERRUPTS_IPC_0 = 23,
1047
1048    #[doc = "CPUSS Inter Process Communication Interrupt #1"]
1049    CPUSS_INTERRUPTS_IPC_1 = 24,
1050
1051    #[doc = "CPUSS Inter Process Communication Interrupt #2"]
1052    CPUSS_INTERRUPTS_IPC_2 = 25,
1053
1054    #[doc = "CPUSS Inter Process Communication Interrupt #3"]
1055    CPUSS_INTERRUPTS_IPC_3 = 26,
1056
1057    #[doc = "CPUSS Inter Process Communication Interrupt #4"]
1058    CPUSS_INTERRUPTS_IPC_4 = 27,
1059
1060    #[doc = "CPUSS Inter Process Communication Interrupt #5"]
1061    CPUSS_INTERRUPTS_IPC_5 = 28,
1062
1063    #[doc = "CPUSS Inter Process Communication Interrupt #6"]
1064    CPUSS_INTERRUPTS_IPC_6 = 29,
1065
1066    #[doc = "CPUSS Inter Process Communication Interrupt #7"]
1067    CPUSS_INTERRUPTS_IPC_7 = 30,
1068
1069    #[doc = "CPUSS Inter Process Communication Interrupt #8"]
1070    CPUSS_INTERRUPTS_IPC_8 = 31,
1071
1072    #[doc = "CPUSS Inter Process Communication Interrupt #9"]
1073    CPUSS_INTERRUPTS_IPC_9 = 32,
1074
1075    #[doc = "CPUSS Inter Process Communication Interrupt #10"]
1076    CPUSS_INTERRUPTS_IPC_10 = 33,
1077
1078    #[doc = "CPUSS Inter Process Communication Interrupt #11"]
1079    CPUSS_INTERRUPTS_IPC_11 = 34,
1080
1081    #[doc = "CPUSS Inter Process Communication Interrupt #12"]
1082    CPUSS_INTERRUPTS_IPC_12 = 35,
1083
1084    #[doc = "CPUSS Inter Process Communication Interrupt #13"]
1085    CPUSS_INTERRUPTS_IPC_13 = 36,
1086
1087    #[doc = "CPUSS Inter Process Communication Interrupt #14"]
1088    CPUSS_INTERRUPTS_IPC_14 = 37,
1089
1090    #[doc = "CPUSS Inter Process Communication Interrupt #15"]
1091    CPUSS_INTERRUPTS_IPC_15 = 38,
1092
1093    #[doc = "Serial Communication Block #0"]
1094    SCB_0_INTERRUPT = 39,
1095
1096    #[doc = "Serial Communication Block #1"]
1097    SCB_1_INTERRUPT = 40,
1098
1099    #[doc = "Serial Communication Block #2"]
1100    SCB_2_INTERRUPT = 41,
1101
1102    #[doc = "Serial Communication Block #3"]
1103    SCB_3_INTERRUPT = 42,
1104
1105    #[doc = "Serial Communication Block #4"]
1106    SCB_4_INTERRUPT = 43,
1107
1108    #[doc = "Serial Communication Block #5"]
1109    SCB_5_INTERRUPT = 44,
1110
1111    #[doc = "CSD (Capsense) interrupt"]
1112    CSD_INTERRUPT = 51,
1113
1114    #[doc = "CPUSS DMAC, Channel #0"]
1115    CPUSS_INTERRUPTS_DMAC_0 = 52,
1116
1117    #[doc = "CPUSS DMAC, Channel #1"]
1118    CPUSS_INTERRUPTS_DMAC_1 = 53,
1119
1120    #[doc = "CPUSS DataWire #0, Channel #0"]
1121    CPUSS_INTERRUPTS_DW0_0 = 56,
1122
1123    #[doc = "CPUSS DataWire #0, Channel #1"]
1124    CPUSS_INTERRUPTS_DW0_1 = 57,
1125
1126    #[doc = "CPUSS DataWire #0, Channel #2"]
1127    CPUSS_INTERRUPTS_DW0_2 = 58,
1128
1129    #[doc = "CPUSS DataWire #0, Channel #3"]
1130    CPUSS_INTERRUPTS_DW0_3 = 59,
1131
1132    #[doc = "CPUSS DataWire #0, Channel #4"]
1133    CPUSS_INTERRUPTS_DW0_4 = 60,
1134
1135    #[doc = "CPUSS DataWire #0, Channel #5"]
1136    CPUSS_INTERRUPTS_DW0_5 = 61,
1137
1138    #[doc = "CPUSS DataWire #0, Channel #6"]
1139    CPUSS_INTERRUPTS_DW0_6 = 62,
1140
1141    #[doc = "CPUSS DataWire #0, Channel #7"]
1142    CPUSS_INTERRUPTS_DW0_7 = 63,
1143
1144    #[doc = "CPUSS DataWire #0, Channel #8"]
1145    CPUSS_INTERRUPTS_DW0_8 = 64,
1146
1147    #[doc = "CPUSS DataWire #0, Channel #9"]
1148    CPUSS_INTERRUPTS_DW0_9 = 65,
1149
1150    #[doc = "CPUSS DataWire #0, Channel #10"]
1151    CPUSS_INTERRUPTS_DW0_10 = 66,
1152
1153    #[doc = "CPUSS DataWire #0, Channel #11"]
1154    CPUSS_INTERRUPTS_DW0_11 = 67,
1155
1156    #[doc = "CPUSS DataWire #0, Channel #12"]
1157    CPUSS_INTERRUPTS_DW0_12 = 68,
1158
1159    #[doc = "CPUSS DataWire #0, Channel #13"]
1160    CPUSS_INTERRUPTS_DW0_13 = 69,
1161
1162    #[doc = "CPUSS DataWire #0, Channel #14"]
1163    CPUSS_INTERRUPTS_DW0_14 = 70,
1164
1165    #[doc = "CPUSS DataWire #0, Channel #15"]
1166    CPUSS_INTERRUPTS_DW0_15 = 71,
1167
1168    #[doc = "CPUSS DataWire #0, Channel #16"]
1169    CPUSS_INTERRUPTS_DW0_16 = 72,
1170
1171    #[doc = "CPUSS DataWire #0, Channel #17"]
1172    CPUSS_INTERRUPTS_DW0_17 = 73,
1173
1174    #[doc = "CPUSS DataWire #0, Channel #18"]
1175    CPUSS_INTERRUPTS_DW0_18 = 74,
1176
1177    #[doc = "CPUSS DataWire #0, Channel #19"]
1178    CPUSS_INTERRUPTS_DW0_19 = 75,
1179
1180    #[doc = "CPUSS DataWire #0, Channel #20"]
1181    CPUSS_INTERRUPTS_DW0_20 = 76,
1182
1183    #[doc = "CPUSS DataWire #0, Channel #21"]
1184    CPUSS_INTERRUPTS_DW0_21 = 77,
1185
1186    #[doc = "CPUSS DataWire #0, Channel #22"]
1187    CPUSS_INTERRUPTS_DW0_22 = 78,
1188
1189    #[doc = "CPUSS DataWire #0, Channel #23"]
1190    CPUSS_INTERRUPTS_DW0_23 = 79,
1191
1192    #[doc = "CPUSS DataWire #0, Channel #24"]
1193    CPUSS_INTERRUPTS_DW0_24 = 80,
1194
1195    #[doc = "CPUSS DataWire #0, Channel #25"]
1196    CPUSS_INTERRUPTS_DW0_25 = 81,
1197
1198    #[doc = "CPUSS DataWire #0, Channel #26"]
1199    CPUSS_INTERRUPTS_DW0_26 = 82,
1200
1201    #[doc = "CPUSS DataWire #0, Channel #27"]
1202    CPUSS_INTERRUPTS_DW0_27 = 83,
1203
1204    #[doc = "CPUSS DataWire #0, Channel #28"]
1205    CPUSS_INTERRUPTS_DW0_28 = 84,
1206
1207    #[doc = "CPUSS DataWire #1, Channel #0"]
1208    CPUSS_INTERRUPTS_DW1_0 = 85,
1209
1210    #[doc = "CPUSS DataWire #1, Channel #1"]
1211    CPUSS_INTERRUPTS_DW1_1 = 86,
1212
1213    #[doc = "CPUSS DataWire #1, Channel #2"]
1214    CPUSS_INTERRUPTS_DW1_2 = 87,
1215
1216    #[doc = "CPUSS DataWire #1, Channel #3"]
1217    CPUSS_INTERRUPTS_DW1_3 = 88,
1218
1219    #[doc = "CPUSS DataWire #1, Channel #4"]
1220    CPUSS_INTERRUPTS_DW1_4 = 89,
1221
1222    #[doc = "CPUSS DataWire #1, Channel #5"]
1223    CPUSS_INTERRUPTS_DW1_5 = 90,
1224
1225    #[doc = "CPUSS DataWire #1, Channel #6"]
1226    CPUSS_INTERRUPTS_DW1_6 = 91,
1227
1228    #[doc = "CPUSS DataWire #1, Channel #7"]
1229    CPUSS_INTERRUPTS_DW1_7 = 92,
1230
1231    #[doc = "CPUSS DataWire #1, Channel #8"]
1232    CPUSS_INTERRUPTS_DW1_8 = 93,
1233
1234    #[doc = "CPUSS DataWire #1, Channel #9"]
1235    CPUSS_INTERRUPTS_DW1_9 = 94,
1236
1237    #[doc = "CPUSS DataWire #1, Channel #10"]
1238    CPUSS_INTERRUPTS_DW1_10 = 95,
1239
1240    #[doc = "CPUSS DataWire #1, Channel #11"]
1241    CPUSS_INTERRUPTS_DW1_11 = 96,
1242
1243    #[doc = "CPUSS DataWire #1, Channel #12"]
1244    CPUSS_INTERRUPTS_DW1_12 = 97,
1245
1246    #[doc = "CPUSS DataWire #1, Channel #13"]
1247    CPUSS_INTERRUPTS_DW1_13 = 98,
1248
1249    #[doc = "CPUSS DataWire #1, Channel #14"]
1250    CPUSS_INTERRUPTS_DW1_14 = 99,
1251
1252    #[doc = "CPUSS DataWire #1, Channel #15"]
1253    CPUSS_INTERRUPTS_DW1_15 = 100,
1254
1255    #[doc = "CPUSS DataWire #1, Channel #16"]
1256    CPUSS_INTERRUPTS_DW1_16 = 101,
1257
1258    #[doc = "CPUSS DataWire #1, Channel #17"]
1259    CPUSS_INTERRUPTS_DW1_17 = 102,
1260
1261    #[doc = "CPUSS DataWire #1, Channel #18"]
1262    CPUSS_INTERRUPTS_DW1_18 = 103,
1263
1264    #[doc = "CPUSS DataWire #1, Channel #19"]
1265    CPUSS_INTERRUPTS_DW1_19 = 104,
1266
1267    #[doc = "CPUSS DataWire #1, Channel #20"]
1268    CPUSS_INTERRUPTS_DW1_20 = 105,
1269
1270    #[doc = "CPUSS DataWire #1, Channel #21"]
1271    CPUSS_INTERRUPTS_DW1_21 = 106,
1272
1273    #[doc = "CPUSS DataWire #1, Channel #22"]
1274    CPUSS_INTERRUPTS_DW1_22 = 107,
1275
1276    #[doc = "CPUSS DataWire #1, Channel #23"]
1277    CPUSS_INTERRUPTS_DW1_23 = 108,
1278
1279    #[doc = "CPUSS DataWire #1, Channel #24"]
1280    CPUSS_INTERRUPTS_DW1_24 = 109,
1281
1282    #[doc = "CPUSS DataWire #1, Channel #25"]
1283    CPUSS_INTERRUPTS_DW1_25 = 110,
1284
1285    #[doc = "CPUSS DataWire #1, Channel #26"]
1286    CPUSS_INTERRUPTS_DW1_26 = 111,
1287
1288    #[doc = "CPUSS DataWire #1, Channel #27"]
1289    CPUSS_INTERRUPTS_DW1_27 = 112,
1290
1291    #[doc = "CPUSS DataWire #1, Channel #28"]
1292    CPUSS_INTERRUPTS_DW1_28 = 113,
1293
1294    #[doc = "CPUSS Fault Structure Interrupt #0"]
1295    CPUSS_INTERRUPTS_FAULT_0 = 114,
1296
1297    #[doc = "CPUSS Fault Structure Interrupt #1"]
1298    CPUSS_INTERRUPTS_FAULT_1 = 115,
1299
1300    #[doc = "CRYPTO Accelerator Interrupt"]
1301    CPUSS_INTERRUPT_CRYPTO = 116,
1302
1303    #[doc = "FLASH Macro Interrupt"]
1304    CPUSS_INTERRUPT_FM = 117,
1305
1306    #[doc = "Floating Point operation fault"]
1307    CPUSS_INTERRUPTS_CM4_FP = 118,
1308
1309    #[doc = "CM0+ CTI #0"]
1310    CPUSS_INTERRUPTS_CM0_CTI_0 = 119,
1311
1312    #[doc = "CM0+ CTI #1"]
1313    CPUSS_INTERRUPTS_CM0_CTI_1 = 120,
1314
1315    #[doc = "CM4 CTI #0"]
1316    CPUSS_INTERRUPTS_CM4_CTI_0 = 121,
1317
1318    #[doc = "CM4 CTI #1"]
1319    CPUSS_INTERRUPTS_CM4_CTI_1 = 122,
1320
1321    #[doc = "TCPWM #0, Counter #0"]
1322    TCPWM_0_INTERRUPTS_0 = 123,
1323
1324    #[doc = "TCPWM #0, Counter #1"]
1325    TCPWM_0_INTERRUPTS_1 = 124,
1326
1327    #[doc = "TCPWM #0, Counter #2"]
1328    TCPWM_0_INTERRUPTS_2 = 125,
1329
1330    #[doc = "TCPWM #0, Counter #3"]
1331    TCPWM_0_INTERRUPTS_3 = 126,
1332
1333    #[doc = "TCPWM #1, Counter #0"]
1334    TCPWM_1_INTERRUPTS_0 = 131,
1335
1336    #[doc = "TCPWM #1, Counter #1"]
1337    TCPWM_1_INTERRUPTS_1 = 132,
1338
1339    #[doc = "TCPWM #1, Counter #2"]
1340    TCPWM_1_INTERRUPTS_2 = 133,
1341
1342    #[doc = "TCPWM #1, Counter #3"]
1343    TCPWM_1_INTERRUPTS_3 = 134,
1344
1345    #[doc = "TCPWM #1, Counter #4"]
1346    TCPWM_1_INTERRUPTS_4 = 135,
1347
1348    #[doc = "TCPWM #1, Counter #5"]
1349    TCPWM_1_INTERRUPTS_5 = 136,
1350
1351    #[doc = "TCPWM #1, Counter #6"]
1352    TCPWM_1_INTERRUPTS_6 = 137,
1353
1354    #[doc = "TCPWM #1, Counter #7"]
1355    TCPWM_1_INTERRUPTS_7 = 138,
1356
1357    #[doc = "SAR ADC interrupt"]
1358    PASS_INTERRUPT_SAR = 155,
1359
1360    #[doc = "Serial Memory Interface interrupt"]
1361    SMIF_INTERRUPT = 160,
1362
1363    #[doc = "USB Interrupt"]
1364    USB_INTERRUPT_HI = 161,
1365
1366    #[doc = "USB Interrupt"]
1367    USB_INTERRUPT_MED = 162,
1368
1369    #[doc = "USB Interrupt"]
1370    USB_INTERRUPT_LO = 163,
1371
1372    #[doc = "SDIO wakeup interrupt for mxsdhc"]
1373    SDHC_0_INTERRUPT_WAKEUP = 164,
1374
1375    #[doc = "Consolidated interrupt for mxsdhc for everything else"]
1376    SDHC_0_INTERRUPT_GENERAL = 165,
1377
1378    #[doc = "Can #0, Consolidated interrupt #0"]
1379    CANFD_0_INTERRUPT0 = 168,
1380
1381    #[doc = "CAN #0, Interrupt #0, Channel #0"]
1382    CANFD_0_INTERRUPTS0_0 = 169,
1383
1384    #[doc = "CAN #0, Interrupt #1, Channel #0"]
1385    CANFD_0_INTERRUPTS1_0 = 170,
1386
1387    #[doc = "CPUSS DataWire #1, Channel #29"]
1388    CPUSS_INTERRUPTS_DW1_29 = 171,
1389
1390    #[doc = "CPUSS DataWire #1, Channel #30"]
1391    CPUSS_INTERRUPTS_DW1_30 = 172,
1392
1393    #[doc = "CPUSS DataWire #1, Channel #31"]
1394    CPUSS_INTERRUPTS_DW1_31 = 173,
1395}
1396unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
1397    #[inline(always)]
1398    fn number(self) -> u16 {
1399        self as u16
1400    }
1401}
1402#[allow(non_snake_case)]
1403/// Required for compatibility with RTIC and other frameworks
1404pub struct Peripherals {
1405    #[cfg(feature = "peri")]
1406    pub PERI: self::Peri,
1407    #[cfg(feature = "peri_ms")]
1408    pub PERI_MS: self::PeriMs,
1409    #[cfg(feature = "crypto")]
1410    pub CRYPTO: self::Crypto,
1411    #[cfg(feature = "cpuss")]
1412    pub CPUSS: self::Cpuss,
1413    #[cfg(feature = "fault")]
1414    pub FAULT: self::Fault,
1415    #[cfg(feature = "ipc")]
1416    pub IPC: self::Ipc,
1417    #[cfg(feature = "prot")]
1418    pub PROT: self::Prot,
1419    #[cfg(feature = "flashc")]
1420    pub FLASHC: self::Flashc,
1421    #[cfg(feature = "srss")]
1422    pub SRSS: self::Srss,
1423    #[cfg(feature = "backup")]
1424    pub BACKUP: self::Backup,
1425    #[cfg(feature = "dw0")]
1426    pub DW0: self::Dw,
1427    #[cfg(feature = "dw1")]
1428    pub DW1: self::Dw,
1429    #[cfg(feature = "dmac")]
1430    pub DMAC: self::Dmac,
1431    #[cfg(feature = "efuse")]
1432    pub EFUSE: self::Efuse,
1433    #[cfg(feature = "hsiom")]
1434    pub HSIOM: self::Hsiom,
1435    #[cfg(feature = "gpio")]
1436    pub GPIO: self::Gpio,
1437    #[cfg(feature = "smartio")]
1438    pub SMARTIO: self::Smartio,
1439    #[cfg(feature = "lpcomp")]
1440    pub LPCOMP: self::Lpcomp,
1441    #[cfg(feature = "csd0")]
1442    pub CSD0: self::Csd,
1443    #[cfg(feature = "tcpwm0")]
1444    pub TCPWM0: self::Tcpwm,
1445    #[cfg(feature = "tcpwm1")]
1446    pub TCPWM1: self::Tcpwm,
1447    #[cfg(feature = "lcd0")]
1448    pub LCD0: self::Lcd,
1449    #[cfg(feature = "usbfs0")]
1450    pub USBFS0: self::Usbfs,
1451    #[cfg(feature = "smif0")]
1452    pub SMIF0: self::Smif,
1453    #[cfg(feature = "sdhc0")]
1454    pub SDHC0: self::Sdhc,
1455    #[cfg(feature = "canfd0")]
1456    pub CANFD0: self::Canfd,
1457    #[cfg(feature = "scb0")]
1458    pub SCB0: self::Scb,
1459    #[cfg(feature = "scb1")]
1460    pub SCB1: self::Scb,
1461    #[cfg(feature = "scb2")]
1462    pub SCB2: self::Scb,
1463    #[cfg(feature = "scb3")]
1464    pub SCB3: self::Scb,
1465    #[cfg(feature = "scb4")]
1466    pub SCB4: self::Scb,
1467    #[cfg(feature = "scb5")]
1468    pub SCB5: self::Scb,
1469    #[cfg(feature = "scb6")]
1470    pub SCB6: self::Scb,
1471    #[cfg(feature = "sar")]
1472    pub SAR: self::Sar,
1473    #[cfg(feature = "pass")]
1474    pub PASS: self::Pass,
1475}
1476
1477impl Peripherals {
1478    /// Returns Peripheral struct multiple times
1479    /// Required for compatibility with RTIC and other frameworks
1480    #[inline]
1481    pub fn take() -> Option<Self> {
1482        Some(Self::steal())
1483    }
1484
1485    /// Returns Peripheral struct multiple times
1486    /// Required for compatibility with RTIC and other frameworks
1487    #[inline]
1488    pub fn steal() -> Self {
1489        Peripherals {
1490            #[cfg(feature = "peri")]
1491            PERI: crate::PERI,
1492            #[cfg(feature = "peri_ms")]
1493            PERI_MS: crate::PERI_MS,
1494            #[cfg(feature = "crypto")]
1495            CRYPTO: crate::CRYPTO,
1496            #[cfg(feature = "cpuss")]
1497            CPUSS: crate::CPUSS,
1498            #[cfg(feature = "fault")]
1499            FAULT: crate::FAULT,
1500            #[cfg(feature = "ipc")]
1501            IPC: crate::IPC,
1502            #[cfg(feature = "prot")]
1503            PROT: crate::PROT,
1504            #[cfg(feature = "flashc")]
1505            FLASHC: crate::FLASHC,
1506            #[cfg(feature = "srss")]
1507            SRSS: crate::SRSS,
1508            #[cfg(feature = "backup")]
1509            BACKUP: crate::BACKUP,
1510            #[cfg(feature = "dw0")]
1511            DW0: crate::DW0,
1512            #[cfg(feature = "dw1")]
1513            DW1: crate::DW1,
1514            #[cfg(feature = "dmac")]
1515            DMAC: crate::DMAC,
1516            #[cfg(feature = "efuse")]
1517            EFUSE: crate::EFUSE,
1518            #[cfg(feature = "hsiom")]
1519            HSIOM: crate::HSIOM,
1520            #[cfg(feature = "gpio")]
1521            GPIO: crate::GPIO,
1522            #[cfg(feature = "smartio")]
1523            SMARTIO: crate::SMARTIO,
1524            #[cfg(feature = "lpcomp")]
1525            LPCOMP: crate::LPCOMP,
1526            #[cfg(feature = "csd0")]
1527            CSD0: crate::CSD0,
1528            #[cfg(feature = "tcpwm0")]
1529            TCPWM0: crate::TCPWM0,
1530            #[cfg(feature = "tcpwm1")]
1531            TCPWM1: crate::TCPWM1,
1532            #[cfg(feature = "lcd0")]
1533            LCD0: crate::LCD0,
1534            #[cfg(feature = "usbfs0")]
1535            USBFS0: crate::USBFS0,
1536            #[cfg(feature = "smif0")]
1537            SMIF0: crate::SMIF0,
1538            #[cfg(feature = "sdhc0")]
1539            SDHC0: crate::SDHC0,
1540            #[cfg(feature = "canfd0")]
1541            CANFD0: crate::CANFD0,
1542            #[cfg(feature = "scb0")]
1543            SCB0: crate::SCB0,
1544            #[cfg(feature = "scb1")]
1545            SCB1: crate::SCB1,
1546            #[cfg(feature = "scb2")]
1547            SCB2: crate::SCB2,
1548            #[cfg(feature = "scb3")]
1549            SCB3: crate::SCB3,
1550            #[cfg(feature = "scb4")]
1551            SCB4: crate::SCB4,
1552            #[cfg(feature = "scb5")]
1553            SCB5: crate::SCB5,
1554            #[cfg(feature = "scb6")]
1555            SCB6: crate::SCB6,
1556            #[cfg(feature = "sar")]
1557            SAR: crate::SAR,
1558            #[cfg(feature = "pass")]
1559            PASS: crate::PASS,
1560        }
1561    }
1562}
mtb_pac_psoc6_03/lib.rs

mtb_pac_psoc6_03/
lib.rs
