1# [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - This bit enables the VREF module."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "This bit enables the VREF module.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - This bit enables the VREF module."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_ENABLEBIAS` reader - This bit enables the VREF Bias."] pub type CTL0_ENABLEBIAS_R = crate :: BitReader < CTL0_ENABLEBIAS_A > ; # [doc = "This bit enables the VREF Bias.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLEBIAS_A { # [doc = "0: DISABLE"] CTL0_ENABLEBIAS_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLEBIAS_ENABLE = 1 , } impl From < CTL0_ENABLEBIAS_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLEBIAS_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLEBIAS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLEBIAS_A { match self . bits { false => CTL0_ENABLEBIAS_A :: CTL0_ENABLEBIAS_DISABLE , true => CTL0_ENABLEBIAS_A :: CTL0_ENABLEBIAS_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enablebias_disable (& self) -> bool { * self == CTL0_ENABLEBIAS_A :: CTL0_ENABLEBIAS_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enablebias_enable (& self) -> bool { * self == CTL0_ENABLEBIAS_A :: CTL0_ENABLEBIAS_ENABLE } } # [doc = "Field `CTL0_ENABLEBIAS` writer - This bit enables the VREF Bias."] pub type CTL0_ENABLEBIAS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLEBIAS_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLEBIAS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enablebias_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLEBIAS_A :: CTL0_ENABLEBIAS_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enablebias_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLEBIAS_A :: CTL0_ENABLEBIAS_ENABLE) } } # [doc = "Field `CTL0_IBPROG` reader - There bits configure current bias."] pub type CTL0_IBPROG_R = crate :: FieldReader < CTL0_IBPROG_A > ; # [doc = "There bits configure current bias.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_IBPROG_A { # [doc = "0: NOMIBIAS"] CTL0_IBPROG_NOMIBIAS = 0 , # [doc = "1: IBPROG01"] CTL0_IBPROG_IBPROG01 = 1 , # [doc = "2: IBPROG10"] CTL0_IBPROG_IBPROG10 = 2 , # [doc = "3: IBPROG11"] CTL0_IBPROG_IBPROG11 = 3 , } impl From < CTL0_IBPROG_A > for u8 { # [inline (always)] fn from (variant : CTL0_IBPROG_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_IBPROG_A { type Ux = u8 ; } impl CTL0_IBPROG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_IBPROG_A { match self . bits { 0 => CTL0_IBPROG_A :: CTL0_IBPROG_NOMIBIAS , 1 => CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG01 , 2 => CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG10 , 3 => CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG11 , _ => unreachable ! () , } } # [doc = "NOMIBIAS"] # [inline (always)] pub fn is_ctl0_ibprog_nomibias (& self) -> bool { * self == CTL0_IBPROG_A :: CTL0_IBPROG_NOMIBIAS } # [doc = "IBPROG01"] # [inline (always)] pub fn is_ctl0_ibprog_ibprog01 (& self) -> bool { * self == CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG01 } # [doc = "IBPROG10"] # [inline (always)] pub fn is_ctl0_ibprog_ibprog10 (& self) -> bool { * self == CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG10 } # [doc = "IBPROG11"] # [inline (always)] pub fn is_ctl0_ibprog_ibprog11 (& self) -> bool { * self == CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG11 } } # [doc = "Field `CTL0_IBPROG` writer - There bits configure current bias."] pub type CTL0_IBPROG_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CTL0_IBPROG_A > ; impl < 'a , REG , const O : u8 > CTL0_IBPROG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOMIBIAS"] # [inline (always)] pub fn ctl0_ibprog_nomibias (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IBPROG_A :: CTL0_IBPROG_NOMIBIAS) } # [doc = "IBPROG01"] # [inline (always)] pub fn ctl0_ibprog_ibprog01 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG01) } # [doc = "IBPROG10"] # [inline (always)] pub fn ctl0_ibprog_ibprog10 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG10) } # [doc = "IBPROG11"] # [inline (always)] pub fn ctl0_ibprog_ibprog11 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG11) } } # [doc = "Field `CTL0_BUFCONFIG` reader - These bits configure output buffer."] pub type CTL0_BUFCONFIG_R = crate :: BitReader < CTL0_BUFCONFIG_A > ; # [doc = "These bits configure output buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_BUFCONFIG_A { # [doc = "0: HV"] CTL0_BUFCONFIG_OUTPUT2P5V = 0 , # [doc = "1: LV"] CTL0_BUFCONFIG_OUTPUT1P4V = 1 , } impl From < CTL0_BUFCONFIG_A > for bool { # [inline (always)] fn from (variant : CTL0_BUFCONFIG_A) -> Self { variant as u8 != 0 } } impl CTL0_BUFCONFIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_BUFCONFIG_A { match self . bits { false => CTL0_BUFCONFIG_A :: CTL0_BUFCONFIG_OUTPUT2P5V , true => CTL0_BUFCONFIG_A :: CTL0_BUFCONFIG_OUTPUT1P4V , } } # [doc = "HV"] # [inline (always)] pub fn is_ctl0_bufconfig_output2p5v (& self) -> bool { * self == CTL0_BUFCONFIG_A :: CTL0_BUFCONFIG_OUTPUT2P5V } # [doc = "LV"] # [inline (always)] pub fn is_ctl0_bufconfig_output1p4v (& self) -> bool { * self == CTL0_BUFCONFIG_A :: CTL0_BUFCONFIG_OUTPUT1P4V } } # [doc = "Field `CTL0_BUFCONFIG` writer - These bits configure output buffer."] pub type CTL0_BUFCONFIG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_BUFCONFIG_A > ; impl < 'a , REG , const O : u8 > CTL0_BUFCONFIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HV"] # [inline (always)] pub fn ctl0_bufconfig_output2p5v (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_BUFCONFIG_A :: CTL0_BUFCONFIG_OUTPUT2P5V) } # [doc = "LV"] # [inline (always)] pub fn ctl0_bufconfig_output1p4v (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_BUFCONFIG_A :: CTL0_BUFCONFIG_OUTPUT1P4V) } } # [doc = "Field `CTL0_SHMODE` reader - This bit enable sample and hold mode"] pub type CTL0_SHMODE_R = crate :: BitReader < CTL0_SHMODE_A > ; # [doc = "This bit enable sample and hold mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_SHMODE_A { # [doc = "0: DISABLE"] CTL0_SHMODE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_SHMODE_ENABLE = 1 , } impl From < CTL0_SHMODE_A > for bool { # [inline (always)] fn from (variant : CTL0_SHMODE_A) -> Self { variant as u8 != 0 } } impl CTL0_SHMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_SHMODE_A { match self . bits { false => CTL0_SHMODE_A :: CTL0_SHMODE_DISABLE , true => CTL0_SHMODE_A :: CTL0_SHMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_shmode_disable (& self) -> bool { * self == CTL0_SHMODE_A :: CTL0_SHMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_shmode_enable (& self) -> bool { * self == CTL0_SHMODE_A :: CTL0_SHMODE_ENABLE } } # [doc = "Field `CTL0_SHMODE` writer - This bit enable sample and hold mode"] pub type CTL0_SHMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_SHMODE_A > ; impl < 'a , REG , const O : u8 > CTL0_SHMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_shmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SHMODE_A :: CTL0_SHMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_shmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SHMODE_A :: CTL0_SHMODE_ENABLE) } } # [doc = "Field `CTL0_SPARE` reader - These bits are reserved"] pub type CTL0_SPARE_R = crate :: FieldReader ; # [doc = "Field `CTL0_SPARE` writer - These bits are reserved"] pub type CTL0_SPARE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O > ; impl R { # [doc = "Bit 0 - This bit enables the VREF module."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - This bit enables the VREF Bias."] # [inline (always)] pub fn ctl0_enablebias (& self) -> CTL0_ENABLEBIAS_R { CTL0_ENABLEBIAS_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - There bits configure current bias."] # [inline (always)] pub fn ctl0_ibprog (& self) -> CTL0_IBPROG_R { CTL0_IBPROG_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bit 7 - These bits configure output buffer."] # [inline (always)] pub fn ctl0_bufconfig (& self) -> CTL0_BUFCONFIG_R { CTL0_BUFCONFIG_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - This bit enable sample and hold mode"] # [inline (always)] pub fn ctl0_shmode (& self) -> CTL0_SHMODE_R { CTL0_SHMODE_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:12 - These bits are reserved"] # [inline (always)] pub fn ctl0_spare (& self) -> CTL0_SPARE_R { CTL0_SPARE_R :: new (((self . bits >> 9) & 0x0f) as u8) } } impl W { # [doc = "Bit 0 - This bit enables the VREF module."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 1 - This bit enables the VREF Bias."] # [inline (always)] # [must_use] pub fn ctl0_enablebias (& mut self) -> CTL0_ENABLEBIAS_W < CTL0_SPEC , 1 > { CTL0_ENABLEBIAS_W :: new (self) } # [doc = "Bits 2:3 - There bits configure current bias."] # [inline (always)] # [must_use] pub fn ctl0_ibprog (& mut self) -> CTL0_IBPROG_W < CTL0_SPEC , 2 > { CTL0_IBPROG_W :: new (self) } # [doc = "Bit 7 - These bits configure output buffer."] # [inline (always)] # [must_use] pub fn ctl0_bufconfig (& mut self) -> CTL0_BUFCONFIG_W < CTL0_SPEC , 7 > { CTL0_BUFCONFIG_W :: new (self) } # [doc = "Bit 8 - This bit enable sample and hold mode"] # [inline (always)] # [must_use] pub fn ctl0_shmode (& mut self) -> CTL0_SHMODE_W < CTL0_SPEC , 8 > { CTL0_SHMODE_W :: new (self) } # [doc = "Bits 9:12 - These bits are reserved"] # [inline (always)] # [must_use] pub fn ctl0_spare (& mut self) -> CTL0_SPARE_W < CTL0_SPEC , 9 > { CTL0_SPARE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }