1# [doc = "Register `IFLS` reader"] pub type R = crate :: R < IFLS_SPEC > ; # [doc = "Register `IFLS` writer"] pub type W = crate :: W < IFLS_SPEC > ; # [doc = "Field `IFLS_TXIFLSEL` reader - UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used."] pub type IFLS_TXIFLSEL_R = crate :: FieldReader ; # [doc = "Field `IFLS_TXIFLSEL` writer - UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used."] pub type IFLS_TXIFLSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `IFLS_RXIFLSEL` reader - UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used."] pub type IFLS_RXIFLSEL_R = crate :: FieldReader ; # [doc = "Field `IFLS_RXIFLSEL` writer - UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used."] pub type IFLS_RXIFLSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `IFLS_RXTOSEL` reader - UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."] pub type IFLS_RXTOSEL_R = crate :: FieldReader ; # [doc = "Field `IFLS_RXTOSEL` writer - UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."] pub type IFLS_RXTOSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O > ; impl R { # [doc = "Bits 0:2 - UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used."] # [inline (always)] pub fn ifls_txiflsel (& self) -> IFLS_TXIFLSEL_R { IFLS_TXIFLSEL_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used."] # [inline (always)] pub fn ifls_rxiflsel (& self) -> IFLS_RXIFLSEL_R { IFLS_RXIFLSEL_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:11 - UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."] # [inline (always)] pub fn ifls_rxtosel (& self) -> IFLS_RXTOSEL_R { IFLS_RXTOSEL_R :: new (((self . bits >> 8) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:2 - UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used."] # [inline (always)] # [must_use] pub fn ifls_txiflsel (& mut self) -> IFLS_TXIFLSEL_W < IFLS_SPEC , 0 > { IFLS_TXIFLSEL_W :: new (self) } # [doc = "Bits 4:6 - UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used."] # [inline (always)] # [must_use] pub fn ifls_rxiflsel (& mut self) -> IFLS_RXIFLSEL_W < IFLS_SPEC , 4 > { IFLS_RXIFLSEL_W :: new (self) } # [doc = "Bits 8:11 - UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."] # [inline (always)] # [must_use] pub fn ifls_rxtosel (& mut self) -> IFLS_RXTOSEL_W < IFLS_SPEC , 8 > { IFLS_RXTOSEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IFLS_SPEC ; impl crate :: RegisterSpec for IFLS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ifls::R`](R) reader structure"] impl crate :: Readable for IFLS_SPEC { } # [doc = "`write(|w| ..)` method takes [`ifls::W`](W) writer structure"] impl crate :: Writable for IFLS_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IFLS to value 0x22"] impl crate :: Resettable for IFLS_SPEC { const RESET_VALUE : Self :: Ux = 0x22 ; }