1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
#[doc = "Register `FLCTL_BURSTPRG_TIMCTL` reader"]
pub struct R(crate::R<FLCTL_BURSTPRG_TIMCTL_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<FLCTL_BURSTPRG_TIMCTL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<FLCTL_BURSTPRG_TIMCTL_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<FLCTL_BURSTPRG_TIMCTL_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Field `ACTIVE` reader - Length of the Active phase for this operation"]
pub type ACTIVE_R = crate::FieldReader<u32, u32>;
impl R {
    #[doc = "Bits 8:27 - Length of the Active phase for this operation"]
    #[inline(always)]
    pub fn active(&self) -> ACTIVE_R {
        ACTIVE_R::new(((self.bits >> 8) & 0x000f_ffff) as u32)
    }
}
#[doc = "Burst Program Timing Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flctl_burstprg_timctl](index.html) module"]
pub struct FLCTL_BURSTPRG_TIMCTL_SPEC;
impl crate::RegisterSpec for FLCTL_BURSTPRG_TIMCTL_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [flctl_burstprg_timctl::R](R) reader structure"]
impl crate::Readable for FLCTL_BURSTPRG_TIMCTL_SPEC {
    type Reader = R;
}