Struct msp432e4::emac0::status::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn emac_status_rpe(&mut self) -> _EMAC_STATUS_RPEW

Bit 0 - MAC MII Receive Protocol Engine Status

pub fn emac_status_rfcfc(&mut self) -> _EMAC_STATUS_RFCFCW

Bits 1:2 - MAC Receive Frame Controller FIFO Status

pub fn emac_status_rwc(&mut self) -> _EMAC_STATUS_RWCW

Bit 4 - TX/RX Controller RX FIFO Write Controller Active Status

pub fn emac_status_rrc(&mut self) -> _EMAC_STATUS_RRCW

Bits 5:6 - TX/RX Controller Read Controller State

pub fn emac_status_rxf(&mut self) -> _EMAC_STATUS_RXFW

Bits 8:9 - TX/RX Controller RX FIFO Fill-level Status

pub fn emac_status_tpe(&mut self) -> _EMAC_STATUS_TPEW

Bit 16 - MAC MII Transmit Protocol Engine Status

pub fn emac_status_tfc(&mut self) -> _EMAC_STATUS_TFCW

Bits 17:18 - MAC Transmit Frame Controller Status

pub fn emac_status_txpaused(&mut self) -> _EMAC_STATUS_TXPAUSEDW

Bit 19 - MAC Transmitter PAUSE

pub fn emac_status_trc(&mut self) -> _EMAC_STATUS_TRCW

Bits 20:21 - TX/RX Controller's TX FIFO Read Controller Status

pub fn emac_status_twc(&mut self) -> _EMAC_STATUS_TWCW

Bit 22 - TX/RX Controller TX FIFO Write Controller Active Status

pub fn emac_status_txfe(&mut self) -> _EMAC_STATUS_TXFEW

Bit 24 - TX/RX Controller TX FIFO Not Empty Status

pub fn emac_status_txff(&mut self) -> _EMAC_STATUS_TXFFW

Bit 25 - TX/RX Controller TX FIFO Full Status