Struct msp432e4::emac0::status::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn emac_status_rpe(&self) -> EMAC_STATUS_RPER

Bit 0 - MAC MII Receive Protocol Engine Status

pub fn emac_status_rfcfc(&self) -> EMAC_STATUS_RFCFCR

Bits 1:2 - MAC Receive Frame Controller FIFO Status

pub fn emac_status_rwc(&self) -> EMAC_STATUS_RWCR

Bit 4 - TX/RX Controller RX FIFO Write Controller Active Status

pub fn emac_status_rrc(&self) -> EMAC_STATUS_RRCR

Bits 5:6 - TX/RX Controller Read Controller State

pub fn emac_status_rxf(&self) -> EMAC_STATUS_RXFR

Bits 8:9 - TX/RX Controller RX FIFO Fill-level Status

pub fn emac_status_tpe(&self) -> EMAC_STATUS_TPER

Bit 16 - MAC MII Transmit Protocol Engine Status

pub fn emac_status_tfc(&self) -> EMAC_STATUS_TFCR

Bits 17:18 - MAC Transmit Frame Controller Status

pub fn emac_status_txpaused(&self) -> EMAC_STATUS_TXPAUSEDR

Bit 19 - MAC Transmitter PAUSE

pub fn emac_status_trc(&self) -> EMAC_STATUS_TRCR

Bits 20:21 - TX/RX Controller's TX FIFO Read Controller Status

pub fn emac_status_twc(&self) -> EMAC_STATUS_TWCR

Bit 22 - TX/RX Controller TX FIFO Write Controller Active Status

pub fn emac_status_txfe(&self) -> EMAC_STATUS_TXFER

Bit 24 - TX/RX Controller TX FIFO Not Empty Status

pub fn emac_status_txff(&self) -> EMAC_STATUS_TXFFR

Bit 25 - TX/RX Controller TX FIFO Full Status