msp430g2231/adc10/
adc10ctl0.rs

1#[doc = "Register `ADC10CTL0` reader"]
2pub type R = crate::R<ADC10CTL0_SPEC>;
3#[doc = "Register `ADC10CTL0` writer"]
4pub type W = crate::W<ADC10CTL0_SPEC>;
5#[doc = "Field `ADC10SC` reader - ADC10 Start Conversion"]
6pub type ADC10SC_R = crate::BitReader;
7#[doc = "Field `ADC10SC` writer - ADC10 Start Conversion"]
8pub type ADC10SC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
9#[doc = "Field `ENC` reader - ADC10 Enable Conversion"]
10pub type ENC_R = crate::BitReader;
11#[doc = "Field `ENC` writer - ADC10 Enable Conversion"]
12pub type ENC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
13#[doc = "Field `ADC10IFG` reader - ADC10 Interrupt Flag"]
14pub type ADC10IFG_R = crate::BitReader;
15#[doc = "Field `ADC10IFG` writer - ADC10 Interrupt Flag"]
16pub type ADC10IFG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
17#[doc = "Field `ADC10IE` reader - ADC10 Interrupt Enalbe"]
18pub type ADC10IE_R = crate::BitReader;
19#[doc = "Field `ADC10IE` writer - ADC10 Interrupt Enalbe"]
20pub type ADC10IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
21#[doc = "Field `ADC10ON` reader - ADC10 On/Enable"]
22pub type ADC10ON_R = crate::BitReader;
23#[doc = "Field `ADC10ON` writer - ADC10 On/Enable"]
24pub type ADC10ON_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
25#[doc = "Field `REFON` reader - ADC10 Reference on"]
26pub type REFON_R = crate::BitReader;
27#[doc = "Field `REFON` writer - ADC10 Reference on"]
28pub type REFON_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
29#[doc = "Field `REF2_5V` reader - ADC10 Ref 0:1.5V / 1:2.5V"]
30pub type REF2_5V_R = crate::BitReader;
31#[doc = "Field `REF2_5V` writer - ADC10 Ref 0:1.5V / 1:2.5V"]
32pub type REF2_5V_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
33#[doc = "Field `MSC` reader - ADC10 Multiple SampleConversion"]
34pub type MSC_R = crate::BitReader;
35#[doc = "Field `MSC` writer - ADC10 Multiple SampleConversion"]
36pub type MSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
37#[doc = "Field `REFBURST` reader - ADC10 Reference Burst Mode"]
38pub type REFBURST_R = crate::BitReader;
39#[doc = "Field `REFBURST` writer - ADC10 Reference Burst Mode"]
40pub type REFBURST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
41#[doc = "Field `REFOUT` reader - ADC10 Enalbe output of Ref."]
42pub type REFOUT_R = crate::BitReader;
43#[doc = "Field `REFOUT` writer - ADC10 Enalbe output of Ref."]
44pub type REFOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
45#[doc = "Field `ADC10SR` reader - ADC10 Sampling Rate 0:200ksps / 1:50ksps"]
46pub type ADC10SR_R = crate::BitReader;
47#[doc = "Field `ADC10SR` writer - ADC10 Sampling Rate 0:200ksps / 1:50ksps"]
48pub type ADC10SR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
49#[doc = "Field `ADC10SHT` reader - ADC10 Sample Hold Select Bit: 0"]
50pub type ADC10SHT_R = crate::FieldReader<ADC10SHT_A>;
51#[doc = "ADC10 Sample Hold Select Bit: 0\n\nValue on reset: 0"]
52#[derive(Clone, Copy, Debug, PartialEq, Eq)]
53#[repr(u8)]
54pub enum ADC10SHT_A {
55    #[doc = "0: 4 x ADC10CLKs"]
56    ADC10SHT_0 = 0,
57    #[doc = "1: 8 x ADC10CLKs"]
58    ADC10SHT_1 = 1,
59    #[doc = "2: 16 x ADC10CLKs"]
60    ADC10SHT_2 = 2,
61    #[doc = "3: 64 x ADC10CLKs"]
62    ADC10SHT_3 = 3,
63}
64impl From<ADC10SHT_A> for u8 {
65    #[inline(always)]
66    fn from(variant: ADC10SHT_A) -> Self {
67        variant as _
68    }
69}
70impl crate::FieldSpec for ADC10SHT_A {
71    type Ux = u8;
72}
73impl ADC10SHT_R {
74    #[doc = "Get enumerated values variant"]
75    #[inline(always)]
76    pub const fn variant(&self) -> ADC10SHT_A {
77        match self.bits {
78            0 => ADC10SHT_A::ADC10SHT_0,
79            1 => ADC10SHT_A::ADC10SHT_1,
80            2 => ADC10SHT_A::ADC10SHT_2,
81            3 => ADC10SHT_A::ADC10SHT_3,
82            _ => unreachable!(),
83        }
84    }
85    #[doc = "4 x ADC10CLKs"]
86    #[inline(always)]
87    pub fn is_adc10sht_0(&self) -> bool {
88        *self == ADC10SHT_A::ADC10SHT_0
89    }
90    #[doc = "8 x ADC10CLKs"]
91    #[inline(always)]
92    pub fn is_adc10sht_1(&self) -> bool {
93        *self == ADC10SHT_A::ADC10SHT_1
94    }
95    #[doc = "16 x ADC10CLKs"]
96    #[inline(always)]
97    pub fn is_adc10sht_2(&self) -> bool {
98        *self == ADC10SHT_A::ADC10SHT_2
99    }
100    #[doc = "64 x ADC10CLKs"]
101    #[inline(always)]
102    pub fn is_adc10sht_3(&self) -> bool {
103        *self == ADC10SHT_A::ADC10SHT_3
104    }
105}
106#[doc = "Field `ADC10SHT` writer - ADC10 Sample Hold Select Bit: 0"]
107pub type ADC10SHT_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, ADC10SHT_A>;
108impl<'a, REG, const O: u8> ADC10SHT_W<'a, REG, O>
109where
110    REG: crate::Writable + crate::RegisterSpec,
111    REG::Ux: From<u8>,
112{
113    #[doc = "4 x ADC10CLKs"]
114    #[inline(always)]
115    pub fn adc10sht_0(self) -> &'a mut crate::W<REG> {
116        self.variant(ADC10SHT_A::ADC10SHT_0)
117    }
118    #[doc = "8 x ADC10CLKs"]
119    #[inline(always)]
120    pub fn adc10sht_1(self) -> &'a mut crate::W<REG> {
121        self.variant(ADC10SHT_A::ADC10SHT_1)
122    }
123    #[doc = "16 x ADC10CLKs"]
124    #[inline(always)]
125    pub fn adc10sht_2(self) -> &'a mut crate::W<REG> {
126        self.variant(ADC10SHT_A::ADC10SHT_2)
127    }
128    #[doc = "64 x ADC10CLKs"]
129    #[inline(always)]
130    pub fn adc10sht_3(self) -> &'a mut crate::W<REG> {
131        self.variant(ADC10SHT_A::ADC10SHT_3)
132    }
133}
134#[doc = "Field `SREF` reader - ADC10 Reference Select Bit: 0"]
135pub type SREF_R = crate::FieldReader<SREF_A>;
136#[doc = "ADC10 Reference Select Bit: 0\n\nValue on reset: 0"]
137#[derive(Clone, Copy, Debug, PartialEq, Eq)]
138#[repr(u8)]
139pub enum SREF_A {
140    #[doc = "0: VR+ = AVCC and VR- = AVSS"]
141    SREF_0 = 0,
142    #[doc = "1: VR+ = VREF+ and VR- = AVSS"]
143    SREF_1 = 1,
144    #[doc = "2: VR+ = VEREF+ and VR- = AVSS"]
145    SREF_2 = 2,
146    #[doc = "3: VR+ = VEREF+ and VR- = AVSS"]
147    SREF_3 = 3,
148    #[doc = "4: VR+ = AVCC and VR- = VREF-/VEREF-"]
149    SREF_4 = 4,
150    #[doc = "5: VR+ = VREF+ and VR- = VREF-/VEREF-"]
151    SREF_5 = 5,
152    #[doc = "6: VR+ = VEREF+ and VR- = VREF-/VEREF-"]
153    SREF_6 = 6,
154    #[doc = "7: VR+ = VEREF+ and VR- = VREF-/VEREF-"]
155    SREF_7 = 7,
156}
157impl From<SREF_A> for u8 {
158    #[inline(always)]
159    fn from(variant: SREF_A) -> Self {
160        variant as _
161    }
162}
163impl crate::FieldSpec for SREF_A {
164    type Ux = u8;
165}
166impl SREF_R {
167    #[doc = "Get enumerated values variant"]
168    #[inline(always)]
169    pub const fn variant(&self) -> SREF_A {
170        match self.bits {
171            0 => SREF_A::SREF_0,
172            1 => SREF_A::SREF_1,
173            2 => SREF_A::SREF_2,
174            3 => SREF_A::SREF_3,
175            4 => SREF_A::SREF_4,
176            5 => SREF_A::SREF_5,
177            6 => SREF_A::SREF_6,
178            7 => SREF_A::SREF_7,
179            _ => unreachable!(),
180        }
181    }
182    #[doc = "VR+ = AVCC and VR- = AVSS"]
183    #[inline(always)]
184    pub fn is_sref_0(&self) -> bool {
185        *self == SREF_A::SREF_0
186    }
187    #[doc = "VR+ = VREF+ and VR- = AVSS"]
188    #[inline(always)]
189    pub fn is_sref_1(&self) -> bool {
190        *self == SREF_A::SREF_1
191    }
192    #[doc = "VR+ = VEREF+ and VR- = AVSS"]
193    #[inline(always)]
194    pub fn is_sref_2(&self) -> bool {
195        *self == SREF_A::SREF_2
196    }
197    #[doc = "VR+ = VEREF+ and VR- = AVSS"]
198    #[inline(always)]
199    pub fn is_sref_3(&self) -> bool {
200        *self == SREF_A::SREF_3
201    }
202    #[doc = "VR+ = AVCC and VR- = VREF-/VEREF-"]
203    #[inline(always)]
204    pub fn is_sref_4(&self) -> bool {
205        *self == SREF_A::SREF_4
206    }
207    #[doc = "VR+ = VREF+ and VR- = VREF-/VEREF-"]
208    #[inline(always)]
209    pub fn is_sref_5(&self) -> bool {
210        *self == SREF_A::SREF_5
211    }
212    #[doc = "VR+ = VEREF+ and VR- = VREF-/VEREF-"]
213    #[inline(always)]
214    pub fn is_sref_6(&self) -> bool {
215        *self == SREF_A::SREF_6
216    }
217    #[doc = "VR+ = VEREF+ and VR- = VREF-/VEREF-"]
218    #[inline(always)]
219    pub fn is_sref_7(&self) -> bool {
220        *self == SREF_A::SREF_7
221    }
222}
223#[doc = "Field `SREF` writer - ADC10 Reference Select Bit: 0"]
224pub type SREF_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, SREF_A>;
225impl<'a, REG, const O: u8> SREF_W<'a, REG, O>
226where
227    REG: crate::Writable + crate::RegisterSpec,
228    REG::Ux: From<u8>,
229{
230    #[doc = "VR+ = AVCC and VR- = AVSS"]
231    #[inline(always)]
232    pub fn sref_0(self) -> &'a mut crate::W<REG> {
233        self.variant(SREF_A::SREF_0)
234    }
235    #[doc = "VR+ = VREF+ and VR- = AVSS"]
236    #[inline(always)]
237    pub fn sref_1(self) -> &'a mut crate::W<REG> {
238        self.variant(SREF_A::SREF_1)
239    }
240    #[doc = "VR+ = VEREF+ and VR- = AVSS"]
241    #[inline(always)]
242    pub fn sref_2(self) -> &'a mut crate::W<REG> {
243        self.variant(SREF_A::SREF_2)
244    }
245    #[doc = "VR+ = VEREF+ and VR- = AVSS"]
246    #[inline(always)]
247    pub fn sref_3(self) -> &'a mut crate::W<REG> {
248        self.variant(SREF_A::SREF_3)
249    }
250    #[doc = "VR+ = AVCC and VR- = VREF-/VEREF-"]
251    #[inline(always)]
252    pub fn sref_4(self) -> &'a mut crate::W<REG> {
253        self.variant(SREF_A::SREF_4)
254    }
255    #[doc = "VR+ = VREF+ and VR- = VREF-/VEREF-"]
256    #[inline(always)]
257    pub fn sref_5(self) -> &'a mut crate::W<REG> {
258        self.variant(SREF_A::SREF_5)
259    }
260    #[doc = "VR+ = VEREF+ and VR- = VREF-/VEREF-"]
261    #[inline(always)]
262    pub fn sref_6(self) -> &'a mut crate::W<REG> {
263        self.variant(SREF_A::SREF_6)
264    }
265    #[doc = "VR+ = VEREF+ and VR- = VREF-/VEREF-"]
266    #[inline(always)]
267    pub fn sref_7(self) -> &'a mut crate::W<REG> {
268        self.variant(SREF_A::SREF_7)
269    }
270}
271impl R {
272    #[doc = "Bit 0 - ADC10 Start Conversion"]
273    #[inline(always)]
274    pub fn adc10sc(&self) -> ADC10SC_R {
275        ADC10SC_R::new((self.bits & 1) != 0)
276    }
277    #[doc = "Bit 1 - ADC10 Enable Conversion"]
278    #[inline(always)]
279    pub fn enc(&self) -> ENC_R {
280        ENC_R::new(((self.bits >> 1) & 1) != 0)
281    }
282    #[doc = "Bit 2 - ADC10 Interrupt Flag"]
283    #[inline(always)]
284    pub fn adc10ifg(&self) -> ADC10IFG_R {
285        ADC10IFG_R::new(((self.bits >> 2) & 1) != 0)
286    }
287    #[doc = "Bit 3 - ADC10 Interrupt Enalbe"]
288    #[inline(always)]
289    pub fn adc10ie(&self) -> ADC10IE_R {
290        ADC10IE_R::new(((self.bits >> 3) & 1) != 0)
291    }
292    #[doc = "Bit 4 - ADC10 On/Enable"]
293    #[inline(always)]
294    pub fn adc10on(&self) -> ADC10ON_R {
295        ADC10ON_R::new(((self.bits >> 4) & 1) != 0)
296    }
297    #[doc = "Bit 5 - ADC10 Reference on"]
298    #[inline(always)]
299    pub fn refon(&self) -> REFON_R {
300        REFON_R::new(((self.bits >> 5) & 1) != 0)
301    }
302    #[doc = "Bit 6 - ADC10 Ref 0:1.5V / 1:2.5V"]
303    #[inline(always)]
304    pub fn ref2_5v(&self) -> REF2_5V_R {
305        REF2_5V_R::new(((self.bits >> 6) & 1) != 0)
306    }
307    #[doc = "Bit 7 - ADC10 Multiple SampleConversion"]
308    #[inline(always)]
309    pub fn msc(&self) -> MSC_R {
310        MSC_R::new(((self.bits >> 7) & 1) != 0)
311    }
312    #[doc = "Bit 8 - ADC10 Reference Burst Mode"]
313    #[inline(always)]
314    pub fn refburst(&self) -> REFBURST_R {
315        REFBURST_R::new(((self.bits >> 8) & 1) != 0)
316    }
317    #[doc = "Bit 9 - ADC10 Enalbe output of Ref."]
318    #[inline(always)]
319    pub fn refout(&self) -> REFOUT_R {
320        REFOUT_R::new(((self.bits >> 9) & 1) != 0)
321    }
322    #[doc = "Bit 10 - ADC10 Sampling Rate 0:200ksps / 1:50ksps"]
323    #[inline(always)]
324    pub fn adc10sr(&self) -> ADC10SR_R {
325        ADC10SR_R::new(((self.bits >> 10) & 1) != 0)
326    }
327    #[doc = "Bits 11:12 - ADC10 Sample Hold Select Bit: 0"]
328    #[inline(always)]
329    pub fn adc10sht(&self) -> ADC10SHT_R {
330        ADC10SHT_R::new(((self.bits >> 11) & 3) as u8)
331    }
332    #[doc = "Bits 13:15 - ADC10 Reference Select Bit: 0"]
333    #[inline(always)]
334    pub fn sref(&self) -> SREF_R {
335        SREF_R::new(((self.bits >> 13) & 7) as u8)
336    }
337}
338impl W {
339    #[doc = "Bit 0 - ADC10 Start Conversion"]
340    #[inline(always)]
341    #[must_use]
342    pub fn adc10sc(&mut self) -> ADC10SC_W<ADC10CTL0_SPEC, 0> {
343        ADC10SC_W::new(self)
344    }
345    #[doc = "Bit 1 - ADC10 Enable Conversion"]
346    #[inline(always)]
347    #[must_use]
348    pub fn enc(&mut self) -> ENC_W<ADC10CTL0_SPEC, 1> {
349        ENC_W::new(self)
350    }
351    #[doc = "Bit 2 - ADC10 Interrupt Flag"]
352    #[inline(always)]
353    #[must_use]
354    pub fn adc10ifg(&mut self) -> ADC10IFG_W<ADC10CTL0_SPEC, 2> {
355        ADC10IFG_W::new(self)
356    }
357    #[doc = "Bit 3 - ADC10 Interrupt Enalbe"]
358    #[inline(always)]
359    #[must_use]
360    pub fn adc10ie(&mut self) -> ADC10IE_W<ADC10CTL0_SPEC, 3> {
361        ADC10IE_W::new(self)
362    }
363    #[doc = "Bit 4 - ADC10 On/Enable"]
364    #[inline(always)]
365    #[must_use]
366    pub fn adc10on(&mut self) -> ADC10ON_W<ADC10CTL0_SPEC, 4> {
367        ADC10ON_W::new(self)
368    }
369    #[doc = "Bit 5 - ADC10 Reference on"]
370    #[inline(always)]
371    #[must_use]
372    pub fn refon(&mut self) -> REFON_W<ADC10CTL0_SPEC, 5> {
373        REFON_W::new(self)
374    }
375    #[doc = "Bit 6 - ADC10 Ref 0:1.5V / 1:2.5V"]
376    #[inline(always)]
377    #[must_use]
378    pub fn ref2_5v(&mut self) -> REF2_5V_W<ADC10CTL0_SPEC, 6> {
379        REF2_5V_W::new(self)
380    }
381    #[doc = "Bit 7 - ADC10 Multiple SampleConversion"]
382    #[inline(always)]
383    #[must_use]
384    pub fn msc(&mut self) -> MSC_W<ADC10CTL0_SPEC, 7> {
385        MSC_W::new(self)
386    }
387    #[doc = "Bit 8 - ADC10 Reference Burst Mode"]
388    #[inline(always)]
389    #[must_use]
390    pub fn refburst(&mut self) -> REFBURST_W<ADC10CTL0_SPEC, 8> {
391        REFBURST_W::new(self)
392    }
393    #[doc = "Bit 9 - ADC10 Enalbe output of Ref."]
394    #[inline(always)]
395    #[must_use]
396    pub fn refout(&mut self) -> REFOUT_W<ADC10CTL0_SPEC, 9> {
397        REFOUT_W::new(self)
398    }
399    #[doc = "Bit 10 - ADC10 Sampling Rate 0:200ksps / 1:50ksps"]
400    #[inline(always)]
401    #[must_use]
402    pub fn adc10sr(&mut self) -> ADC10SR_W<ADC10CTL0_SPEC, 10> {
403        ADC10SR_W::new(self)
404    }
405    #[doc = "Bits 11:12 - ADC10 Sample Hold Select Bit: 0"]
406    #[inline(always)]
407    #[must_use]
408    pub fn adc10sht(&mut self) -> ADC10SHT_W<ADC10CTL0_SPEC, 11> {
409        ADC10SHT_W::new(self)
410    }
411    #[doc = "Bits 13:15 - ADC10 Reference Select Bit: 0"]
412    #[inline(always)]
413    #[must_use]
414    pub fn sref(&mut self) -> SREF_W<ADC10CTL0_SPEC, 13> {
415        SREF_W::new(self)
416    }
417    #[doc = r" Writes raw bits to the register."]
418    #[doc = r""]
419    #[doc = r" # Safety"]
420    #[doc = r""]
421    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
422    #[inline(always)]
423    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
424        self.bits = bits;
425        self
426    }
427}
428#[doc = "ADC10 Control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc10ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc10ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
429pub struct ADC10CTL0_SPEC;
430impl crate::RegisterSpec for ADC10CTL0_SPEC {
431    type Ux = u16;
432}
433#[doc = "`read()` method returns [`adc10ctl0::R`](R) reader structure"]
434impl crate::Readable for ADC10CTL0_SPEC {}
435#[doc = "`write(|w| ..)` method takes [`adc10ctl0::W`](W) writer structure"]
436impl crate::Writable for ADC10CTL0_SPEC {
437    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
438    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
439}
440#[doc = "`reset()` method sets ADC10CTL0 to value 0"]
441impl crate::Resettable for ADC10CTL0_SPEC {
442    const RESET_VALUE: Self::Ux = 0;
443}
msp430g2231/adc10/adc10ctl0.rs

msp430g2231/adc10/
adc10ctl0.rs
