Struct msp430g2211::generic::W[−][src]

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>[src]

pub unsafe fn bits(&mut self, bits: U) -> &mut Self[src]

Writes raw bits to the register

impl W<u8, Reg<u8, _IE1>>[src]

pub fn wdtie(&mut self) -> WDTIE_W<'_>[src]

Bit 0 - Watchdog Interrupt Enable

pub fn ofie(&mut self) -> OFIE_W<'_>[src]

Bit 1 - Osc. Fault Interrupt Enable

pub fn nmiie(&mut self) -> NMIIE_W<'_>[src]

Bit 4 - NMI Interrupt Enable

pub fn accvie(&mut self) -> ACCVIE_W<'_>[src]

Bit 5 - Flash Access Violation Interrupt Enable

impl W<u8, Reg<u8, _IFG1>>[src]

pub fn wdtifg(&mut self) -> WDTIFG_W<'_>[src]

Bit 0 - Watchdog Interrupt Flag

pub fn ofifg(&mut self) -> OFIFG_W<'_>[src]

Bit 1 - Osc. Fault Interrupt Flag

pub fn porifg(&mut self) -> PORIFG_W<'_>[src]

Bit 2 - Power On Interrupt Flag

pub fn rstifg(&mut self) -> RSTIFG_W<'_>[src]

Bit 3 - Reset Interrupt Flag

pub fn nmiifg(&mut self) -> NMIIFG_W<'_>[src]

Bit 4 - NMI Interrupt Flag

impl W<u8, Reg<u8, _P1IN>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p1in(&mut self) -> P1IN_W<'_>[src]

Bits 0:7 - Port 1 Input register

impl W<u8, Reg<u8, _P1OUT>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p1out(&mut self) -> P1OUT_W<'_>[src]

Bits 0:7 - Port 1 Output register

impl W<u8, Reg<u8, _P1DIR>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p1dir(&mut self) -> P1DIR_W<'_>[src]

Bits 0:7 - Port 1 Direction register

impl W<u8, Reg<u8, _P1IFG>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p1ifg(&mut self) -> P1IFG_W<'_>[src]

Bits 0:7 - Port 1 Interrupt Flag register

impl W<u8, Reg<u8, _P1IES>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p1ies(&mut self) -> P1IES_W<'_>[src]

Bits 0:7 - Port 1 Interrupt Edge Select register

impl W<u8, Reg<u8, _P1IE>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p1ie(&mut self) -> P1IE_W<'_>[src]

Bits 0:7 - Port 1 Interrupt Enable register

impl W<u8, Reg<u8, _P1SEL>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p1sel(&mut self) -> P1SEL_W<'_>[src]

Bits 0:7 - Port 1 Selection register

impl W<u8, Reg<u8, _P1REN>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p1ren(&mut self) -> P1REN_W<'_>[src]

Bits 0:7 - Port 1 Resistor Enable register

impl W<u8, Reg<u8, _P2IN>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p2in(&mut self) -> P2IN_W<'_>[src]

Bits 0:7 - Port 2 Input register

impl W<u8, Reg<u8, _P2OUT>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p2out(&mut self) -> P2OUT_W<'_>[src]

Bits 0:7 - Port 2 Output register

impl W<u8, Reg<u8, _P2DIR>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p2dir(&mut self) -> P2DIR_W<'_>[src]

Bits 0:7 - Port 2 Direction register

impl W<u8, Reg<u8, _P2IFG>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p2ifg(&mut self) -> P2IFG_W<'_>[src]

Bits 0:7 - Port 2 Interrupt Flag register

impl W<u8, Reg<u8, _P2IES>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p2ies(&mut self) -> P2IES_W<'_>[src]

Bits 0:7 - Port 2 Interrupt Edge Select register

impl W<u8, Reg<u8, _P2IE>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p2ie(&mut self) -> P2IE_W<'_>[src]

Bits 0:7 - Port 2 Interrupt Enable register

impl W<u8, Reg<u8, _P2SEL>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p2sel(&mut self) -> P2SEL_W<'_>[src]

Bits 0:7 - Port 2 Selection register

impl W<u8, Reg<u8, _P2REN>>[src]

pub fn p0(&mut self) -> P0_W<'_>[src]

Bit 0 - P0

pub fn p1(&mut self) -> P1_W<'_>[src]

Bit 1 - P1

pub fn p2(&mut self) -> P2_W<'_>[src]

Bit 2 - P2

pub fn p3(&mut self) -> P3_W<'_>[src]

Bit 3 - P3

pub fn p4(&mut self) -> P4_W<'_>[src]

Bit 4 - P4

pub fn p5(&mut self) -> P5_W<'_>[src]

Bit 5 - P5

pub fn p6(&mut self) -> P6_W<'_>[src]

Bit 6 - P6

pub fn p7(&mut self) -> P7_W<'_>[src]

Bit 7 - P7

pub fn p2ren(&mut self) -> P2REN_W<'_>[src]

Bits 0:7 - Port 2 Resistor Enable register

impl W<u8, Reg<u8, _BCSCTL3>>[src]

pub fn lfxt1of(&mut self) -> LFXT1OF_W<'_>[src]

Bit 0 - Low/high Frequency Oscillator Fault Flag

pub fn xt2of(&mut self) -> XT2OF_W<'_>[src]

Bit 1 - High frequency oscillator 2 fault flag

pub fn xcap(&mut self) -> XCAP_W<'_>[src]

Bits 2:3 - XIN/XOUT Cap 0

pub fn lfxt1s(&mut self) -> LFXT1S_W<'_>[src]

Bits 4:5 - Mode 0 for LFXT1 (XTS = 0)

pub fn xt2s(&mut self) -> XT2S_W<'_>[src]

Bits 6:7 - Mode 0 for XT2

impl W<u8, Reg<u8, _DCOCTL>>[src]

pub fn mod0(&mut self) -> MOD0_W<'_>[src]

Bit 0 - Modulation Bit 0

pub fn mod1(&mut self) -> MOD1_W<'_>[src]

Bit 1 - Modulation Bit 1

pub fn mod2(&mut self) -> MOD2_W<'_>[src]

Bit 2 - Modulation Bit 2

pub fn mod3(&mut self) -> MOD3_W<'_>[src]

Bit 3 - Modulation Bit 3

pub fn mod4(&mut self) -> MOD4_W<'_>[src]

Bit 4 - Modulation Bit 4

pub fn dco0(&mut self) -> DCO0_W<'_>[src]

Bit 5 - DCO Select Bit 0

pub fn dco1(&mut self) -> DCO1_W<'_>[src]

Bit 6 - DCO Select Bit 1

pub fn dco2(&mut self) -> DCO2_W<'_>[src]

Bit 7 - DCO Select Bit 2

pub fn dcoctl(&mut self) -> DCOCTL_W<'_>[src]

Bits 0:7 - DCO Clock Frequency Control register

pub fn dco(&mut self) -> DCO_W<'_>[src]

Bits 5:7 - DCO Frequency Select

pub fn mod_(&mut self) -> MOD_W<'_>[src]

Bits 0:4 - Modulator Selection

impl W<u8, Reg<u8, _BCSCTL1>>[src]

pub fn rsel0(&mut self) -> RSEL0_W<'_>[src]

Bit 0 - Range Select Bit 0

pub fn rsel1(&mut self) -> RSEL1_W<'_>[src]

Bit 1 - Range Select Bit 1

pub fn rsel2(&mut self) -> RSEL2_W<'_>[src]

Bit 2 - Range Select Bit 2

pub fn rsel3(&mut self) -> RSEL3_W<'_>[src]

Bit 3 - Range Select Bit 3

pub fn diva(&mut self) -> DIVA_W<'_>[src]

Bits 4:5 - ACLK Divider 0

pub fn xts(&mut self) -> XTS_W<'_>[src]

Bit 6 - LFXTCLK 0:Low Freq. / 1: High Freq.

pub fn xt2off(&mut self) -> XT2OFF_W<'_>[src]

Bit 7 - Enable XT2CLK

pub fn bcsctl1(&mut self) -> BCSCTL1_W<'_>[src]

Bits 0:7 - Basic Clock System Control 1 register

pub fn rsel(&mut self) -> RSEL_W<'_>[src]

Bits 0:3 - Range Select

impl W<u8, Reg<u8, _BCSCTL2>>[src]

pub fn divs(&mut self) -> DIVS_W<'_>[src]

Bits 1:2 - SMCLK Divider 0

pub fn sels(&mut self) -> SELS_W<'_>[src]

Bit 3 - SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK

pub fn divm(&mut self) -> DIVM_W<'_>[src]

Bits 4:5 - MCLK Divider 0

pub fn selm(&mut self) -> SELM_W<'_>[src]

Bits 6:7 - MCLK Source Select 0

impl W<u8, Reg<u8, _CACTL1>>[src]

pub fn caifg(&mut self) -> CAIFG_W<'_>[src]

Bit 0 - Comp. A Interrupt Flag

pub fn caie(&mut self) -> CAIE_W<'_>[src]

Bit 1 - Comp. A Interrupt Enable

pub fn caies(&mut self) -> CAIES_W<'_>[src]

Bit 2 - Comp. A Int. Edge Select: 0:rising / 1:falling

pub fn caon(&mut self) -> CAON_W<'_>[src]

Bit 3 - Comp. A enable

pub fn caref(&mut self) -> CAREF_W<'_>[src]

Bits 4:5 - Comp. A Internal Reference Select 0

pub fn carsel(&mut self) -> CARSEL_W<'_>[src]

Bit 6 - Comp. A Internal Reference Enable

pub fn caex(&mut self) -> CAEX_W<'_>[src]

Bit 7 - Comp. A Exchange Inputs

impl W<u8, Reg<u8, _CACTL2>>[src]

pub fn caout(&mut self) -> CAOUT_W<'_>[src]

Bit 0 - Comp. A Output

pub fn caf(&mut self) -> CAF_W<'_>[src]

Bit 1 - Comp. A Enable Output Filter

pub fn p2ca0(&mut self) -> P2CA0_W<'_>[src]

Bit 2 - Comp. A +Terminal Multiplexer

pub fn p2ca1(&mut self) -> P2CA1_W<'_>[src]

Bit 3 - Comp. A -Terminal Multiplexer

pub fn p2ca2(&mut self) -> P2CA2_W<'_>[src]

Bit 4 - Comp. A -Terminal Multiplexer

pub fn p2ca3(&mut self) -> P2CA3_W<'_>[src]

Bit 5 - Comp. A -Terminal Multiplexer

pub fn p2ca4(&mut self) -> P2CA4_W<'_>[src]

Bit 6 - Comp. A +Terminal Multiplexer

pub fn cashort(&mut self) -> CASHORT_W<'_>[src]

Bit 7 - Comp. A Short + and - Terminals

pub fn p2ca(&mut self) -> P2CA_W<'_>[src]

Bits 2:6 - Comparator A +/-Terminal Multiplexer register

impl W<u8, Reg<u8, _CAPD>>[src]

pub fn capd0(&mut self) -> CAPD0_W<'_>[src]

Bit 0 - Comp. A Disable Input Buffer of Port Register .0

pub fn capd1(&mut self) -> CAPD1_W<'_>[src]

Bit 1 - Comp. A Disable Input Buffer of Port Register .1

pub fn capd2(&mut self) -> CAPD2_W<'_>[src]

Bit 2 - Comp. A Disable Input Buffer of Port Register .2

pub fn capd3(&mut self) -> CAPD3_W<'_>[src]

Bit 3 - Comp. A Disable Input Buffer of Port Register .3

pub fn capd4(&mut self) -> CAPD4_W<'_>[src]

Bit 4 - Comp. A Disable Input Buffer of Port Register .4

pub fn capd5(&mut self) -> CAPD5_W<'_>[src]

Bit 5 - Comp. A Disable Input Buffer of Port Register .5

pub fn capd6(&mut self) -> CAPD6_W<'_>[src]

Bit 6 - Comp. A Disable Input Buffer of Port Register .6

pub fn capd7(&mut self) -> CAPD7_W<'_>[src]

Bit 7 - Comp. A Disable Input Buffer of Port Register .7

pub fn capd(&mut self) -> CAPD_W<'_>[src]

Bits 0:7 - Comparator A Port Disable register

impl W<u8, Reg<u8, _CALDCO_1MHZ>>[src]

pub fn caldco_1mhz(&mut self) -> CALDCO_1MHZ_W<'_>[src]

Bits 0:7 - DCOCTL Calibration Data register

impl W<u8, Reg<u8, _CALBC1_1MHZ>>[src]

pub fn calbc1_1mhz(&mut self) -> CALBC1_1MHZ_W<'_>[src]

Bits 0:7 - BCSCTL1 Calibration Data register

impl W<u16, Reg<u16, _WDTCTL>>[src]

pub fn wdtis0(&mut self) -> WDTIS0_W<'_>[src]

Bit 0 - WDTIS0

pub fn wdtis1(&mut self) -> WDTIS1_W<'_>[src]

Bit 1 - WDTIS1

pub fn wdtssel(&mut self) -> WDTSSEL_W<'_>[src]

Bit 2 - WDTSSEL

pub fn wdtcntcl(&mut self) -> WDTCNTCL_W<'_>[src]

Bit 3 - WDTCNTCL

pub fn wdttmsel(&mut self) -> WDTTMSEL_W<'_>[src]

Bit 4 - WDTTMSEL

pub fn wdtnmi(&mut self) -> WDTNMI_W<'_>[src]

Bit 5 - WDTNMI

pub fn wdtnmies(&mut self) -> WDTNMIES_W<'_>[src]

Bit 6 - WDTNMIES

pub fn wdthold(&mut self) -> WDTHOLD_W<'_>[src]

Bit 7 - WDTHOLD

pub fn wdtpw(&mut self) -> WDTPW_W<'_>[src]

Bits 8:15 - Watchdog Timer Password

impl W<u16, Reg<u16, _FCTL1>>[src]

pub fn erase(&mut self) -> ERASE_W<'_>[src]

Bit 1 - Enable bit for Flash segment erase

pub fn meras(&mut self) -> MERAS_W<'_>[src]

Bit 2 - Enable bit for Flash mass erase

pub fn wrt(&mut self) -> WRT_W<'_>[src]

Bit 6 - Enable bit for Flash write

pub fn blkwrt(&mut self) -> BLKWRT_W<'_>[src]

Bit 7 - Enable bit for Flash segment write

pub fn fwkey(&mut self) -> FWKEY_W<'_>[src]

Bits 8:15 - FCTL1 Password

impl W<u16, Reg<u16, _FCTL2>>[src]

pub fn fn0(&mut self) -> FN0_W<'_>[src]

Bit 0 - Divide Flash clock by 1 to 64 using FN0 to FN5 according to:

pub fn fn1(&mut self) -> FN1_W<'_>[src]

Bit 1 - 32FN5 + 16FN4 + 8FN3 + 4FN2 + 2*FN1 + FN0 + 1

pub fn fn2(&mut self) -> FN2_W<'_>[src]

Bit 2 - FN2

pub fn fn3(&mut self) -> FN3_W<'_>[src]

Bit 3 - FN3

pub fn fn4(&mut self) -> FN4_W<'_>[src]

Bit 4 - FN4

pub fn fn5(&mut self) -> FN5_W<'_>[src]

Bit 5 - FN5

pub fn fssel(&mut self) -> FSSEL_W<'_>[src]

Bits 6:7 - Flash clock select 0 / / to distinguish from USART SSELx

pub fn fwkey(&mut self) -> FWKEY_W<'_>[src]

Bits 8:15 - FCTL2 Password

pub fn fn_(&mut self) -> FN_W<'_>[src]

Bits 0:5 - Flash Controller Clock Divider

impl W<u16, Reg<u16, _FCTL3>>[src]

pub fn busy(&mut self) -> BUSY_W<'_>[src]

Bit 0 - Flash busy: 1

pub fn keyv(&mut self) -> KEYV_W<'_>[src]

Bit 1 - Flash Key violation flag

pub fn accvifg(&mut self) -> ACCVIFG_W<'_>[src]

Bit 2 - Flash Access violation flag

pub fn wait(&mut self) -> WAIT_W<'_>[src]

Bit 3 - Wait flag for segment write

pub fn lock(&mut self) -> LOCK_W<'_>[src]

Bit 4 - Lock bit: 1 - Flash is locked (read only)

pub fn emex(&mut self) -> EMEX_W<'_>[src]

Bit 5 - Flash Emergency Exit

pub fn locka(&mut self) -> LOCKA_W<'_>[src]

Bit 6 - Segment A Lock bit: read = 1 - Segment is locked (read only)

pub fn fail(&mut self) -> FAIL_W<'_>[src]

Bit 7 - Last Program or Erase failed

pub fn fwkey(&mut self) -> FWKEY_W<'_>[src]

Bits 8:15 - FCTL3 Password

impl W<u16, Reg<u16, _TACTL>>[src]

pub fn taifg(&mut self) -> TAIFG_W<'_>[src]

Bit 0 - Timer A counter interrupt flag

pub fn taie(&mut self) -> TAIE_W<'_>[src]

Bit 1 - Timer A counter interrupt enable

pub fn taclr(&mut self) -> TACLR_W<'_>[src]

Bit 2 - Timer A counter clear

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 4:5 - Timer A mode control 1

pub fn id(&mut self) -> ID_W<'_>[src]

Bits 6:7 - Timer A clock input divider 1

pub fn tassel(&mut self) -> TASSEL_W<'_>[src]

Bits 8:9 - Timer A clock source select 1

impl W<u16, Reg<u16, _TACCTL0>>[src]

pub fn ccifg(&mut self) -> CCIFG_W<'_>[src]

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>[src]

Bit 1 - Capture/compare overflow flag

pub fn out(&mut self) -> OUT_W<'_>[src]

Bit 2 - PWM Output signal if output mode 0

pub fn cci(&mut self) -> CCI_W<'_>[src]

Bit 3 - Capture input signal (read)

pub fn ccie(&mut self) -> CCIE_W<'_>[src]

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>[src]

Bits 5:7 - Output mode 2

pub fn cap(&mut self) -> CAP_W<'_>[src]

Bit 8 - Capture mode: 1 /Compare mode : 0

pub fn scci(&mut self) -> SCCI_W<'_>[src]

Bit 10 - Latched capture signal (read)

pub fn scs(&mut self) -> SCS_W<'_>[src]

Bit 11 - Capture sychronize

pub fn ccis(&mut self) -> CCIS_W<'_>[src]

Bits 12:13 - Capture input select 1

pub fn cm(&mut self) -> CM_W<'_>[src]

Bits 14:15 - Capture mode 1

impl W<u16, Reg<u16, _TACCTL1>>[src]

pub fn ccifg(&mut self) -> CCIFG_W<'_>[src]

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>[src]

Bit 1 - Capture/compare overflow flag

pub fn out(&mut self) -> OUT_W<'_>[src]

Bit 2 - PWM Output signal if output mode 0

pub fn cci(&mut self) -> CCI_W<'_>[src]

Bit 3 - Capture input signal (read)

pub fn ccie(&mut self) -> CCIE_W<'_>[src]

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>[src]

Bits 5:7 - Output mode 2

pub fn cap(&mut self) -> CAP_W<'_>[src]

Bit 8 - Capture mode: 1 /Compare mode : 0

pub fn scci(&mut self) -> SCCI_W<'_>[src]

Bit 10 - Latched capture signal (read)

pub fn scs(&mut self) -> SCS_W<'_>[src]

Bit 11 - Capture sychronize

pub fn ccis(&mut self) -> CCIS_W<'_>[src]

Bits 12:13 - Capture input select 1

pub fn cm(&mut self) -> CM_W<'_>[src]

Bits 14:15 - Capture mode 1

impl W<u16, Reg<u16, _TAIV>>[src]

pub fn taiv(&mut self) -> TAIV_W<'_>[src]

Bits 0:3 - Timer A Interrupt Vector value

impl W<u16, Reg<u16, _TAR>>[src]

pub fn tar(&mut self) -> TAR_W<'_>[src]

Bits 0:15 - Timer A Counter Register

impl W<u16, Reg<u16, _TACCR0>>[src]

pub fn taccr0(&mut self) -> TACCR0_W<'_>[src]

Bits 0:15 - Timer A Capture/Compare register 0

impl W<u16, Reg<u16, _TACCR1>>[src]

pub fn taccr1(&mut self) -> TACCR1_W<'_>[src]

Bits 0:15 - Timer A Capture/Compare register 1

Auto Trait Implementations

impl<U, REG> Send for W<U, REG> where
    REG: Send,
    U: Send, 

impl<U, REG> Sync for W<U, REG> where
    REG: Sync,
    U: Sync, 

impl<U, REG> Unpin for W<U, REG> where
    REG: Unpin,
    U: Unpin, 

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.