Struct msp430g2211::generic::R

pub struct R<U, T> { /* fields omitted */ }

Register/field reader

Result of the read method of a register. Also it can be used in the modify method

Implementations

impl<U, T> R<U, T> where
    U: Copy, 

pub fn bits(&self) -> U

Read raw bits from register/field

impl<FI> R<bool, FI>

pub fn bit(&self) -> bool

Value of the field as raw bits

pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0)

pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1)

impl R<u8, Reg<u8, _IE1>>

pub fn wdtie(&self) -> WDTIE_R

Bit 0 - Watchdog Interrupt Enable

pub fn ofie(&self) -> OFIE_R

Bit 1 - Osc. Fault Interrupt Enable

pub fn nmiie(&self) -> NMIIE_R

Bit 4 - NMI Interrupt Enable

pub fn accvie(&self) -> ACCVIE_R

Bit 5 - Flash Access Violation Interrupt Enable

impl R<u8, Reg<u8, _IFG1>>

pub fn wdtifg(&self) -> WDTIFG_R

Bit 0 - Watchdog Interrupt Flag

pub fn ofifg(&self) -> OFIFG_R

Bit 1 - Osc. Fault Interrupt Flag

pub fn porifg(&self) -> PORIFG_R

Bit 2 - Power On Interrupt Flag

pub fn rstifg(&self) -> RSTIFG_R

Bit 3 - Reset Interrupt Flag

pub fn nmiifg(&self) -> NMIIFG_R

Bit 4 - NMI Interrupt Flag

impl R<u8, Reg<u8, _P1IN>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p1in(&self) -> P1IN_R

Bits 0:7 - Port 1 Input register

impl R<u8, Reg<u8, _P1OUT>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p1out(&self) -> P1OUT_R

Bits 0:7 - Port 1 Output register

impl R<u8, Reg<u8, _P1DIR>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p1dir(&self) -> P1DIR_R

Bits 0:7 - Port 1 Direction register

impl R<u8, Reg<u8, _P1IFG>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p1ifg(&self) -> P1IFG_R

Bits 0:7 - Port 1 Interrupt Flag register

impl R<u8, Reg<u8, _P1IES>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p1ies(&self) -> P1IES_R

Bits 0:7 - Port 1 Interrupt Edge Select register

impl R<u8, Reg<u8, _P1IE>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p1ie(&self) -> P1IE_R

Bits 0:7 - Port 1 Interrupt Enable register

impl R<u8, Reg<u8, _P1SEL>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p1sel(&self) -> P1SEL_R

Bits 0:7 - Port 1 Selection register

impl R<u8, Reg<u8, _P1REN>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p1ren(&self) -> P1REN_R

Bits 0:7 - Port 1 Resistor Enable register

impl R<u8, Reg<u8, _P2IN>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p2in(&self) -> P2IN_R

Bits 0:7 - Port 2 Input register

impl R<u8, Reg<u8, _P2OUT>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p2out(&self) -> P2OUT_R

Bits 0:7 - Port 2 Output register

impl R<u8, Reg<u8, _P2DIR>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p2dir(&self) -> P2DIR_R

Bits 0:7 - Port 2 Direction register

impl R<u8, Reg<u8, _P2IFG>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p2ifg(&self) -> P2IFG_R

Bits 0:7 - Port 2 Interrupt Flag register

impl R<u8, Reg<u8, _P2IES>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p2ies(&self) -> P2IES_R

Bits 0:7 - Port 2 Interrupt Edge Select register

impl R<u8, Reg<u8, _P2IE>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p2ie(&self) -> P2IE_R

Bits 0:7 - Port 2 Interrupt Enable register

impl R<u8, Reg<u8, _P2SEL>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p2sel(&self) -> P2SEL_R

Bits 0:7 - Port 2 Selection register

impl R<u8, Reg<u8, _P2REN>>

pub fn p0(&self) -> P0_R

Bit 0 - P0

pub fn p1(&self) -> P1_R

Bit 1 - P1

pub fn p2(&self) -> P2_R

Bit 2 - P2

pub fn p3(&self) -> P3_R

Bit 3 - P3

pub fn p4(&self) -> P4_R

Bit 4 - P4

pub fn p5(&self) -> P5_R

Bit 5 - P5

pub fn p6(&self) -> P6_R

Bit 6 - P6

pub fn p7(&self) -> P7_R

Bit 7 - P7

pub fn p2ren(&self) -> P2REN_R

Bits 0:7 - Port 2 Resistor Enable register

impl R<u8, XCAP_A>

pub fn variant(&self) -> XCAP_A

Get enumerated values variant

pub fn is_xcap_0(&self) -> bool

Checks if the value of the field is XCAP_0

pub fn is_xcap_1(&self) -> bool

Checks if the value of the field is XCAP_1

pub fn is_xcap_2(&self) -> bool

Checks if the value of the field is XCAP_2

pub fn is_xcap_3(&self) -> bool

Checks if the value of the field is XCAP_3

impl R<u8, LFXT1S_A>

pub fn variant(&self) -> LFXT1S_A

Get enumerated values variant

pub fn is_lfxt1s_0(&self) -> bool

Checks if the value of the field is LFXT1S_0

pub fn is_lfxt1s_1(&self) -> bool

Checks if the value of the field is LFXT1S_1

pub fn is_lfxt1s_2(&self) -> bool

Checks if the value of the field is LFXT1S_2

pub fn is_lfxt1s_3(&self) -> bool

Checks if the value of the field is LFXT1S_3

impl R<u8, XT2S_A>

pub fn variant(&self) -> XT2S_A

Get enumerated values variant

pub fn is_xt2s_0(&self) -> bool

Checks if the value of the field is XT2S_0

pub fn is_xt2s_1(&self) -> bool

Checks if the value of the field is XT2S_1

pub fn is_xt2s_2(&self) -> bool

Checks if the value of the field is XT2S_2

pub fn is_xt2s_3(&self) -> bool

Checks if the value of the field is XT2S_3

impl R<u8, Reg<u8, _BCSCTL3>>

pub fn lfxt1of(&self) -> LFXT1OF_R

Bit 0 - Low/high Frequency Oscillator Fault Flag

pub fn xt2of(&self) -> XT2OF_R

Bit 1 - High frequency oscillator 2 fault flag

pub fn xcap(&self) -> XCAP_R

Bits 2:3 - XIN/XOUT Cap 0

pub fn lfxt1s(&self) -> LFXT1S_R

Bits 4:5 - Mode 0 for LFXT1 (XTS = 0)

pub fn xt2s(&self) -> XT2S_R

Bits 6:7 - Mode 0 for XT2

impl R<u8, Reg<u8, _DCOCTL>>

pub fn mod0(&self) -> MOD0_R

Bit 0 - Modulation Bit 0

pub fn mod1(&self) -> MOD1_R

Bit 1 - Modulation Bit 1

pub fn mod2(&self) -> MOD2_R

Bit 2 - Modulation Bit 2

pub fn mod3(&self) -> MOD3_R

Bit 3 - Modulation Bit 3

pub fn mod4(&self) -> MOD4_R

Bit 4 - Modulation Bit 4

pub fn dco0(&self) -> DCO0_R

Bit 5 - DCO Select Bit 0

pub fn dco1(&self) -> DCO1_R

Bit 6 - DCO Select Bit 1

pub fn dco2(&self) -> DCO2_R

Bit 7 - DCO Select Bit 2

pub fn dcoctl(&self) -> DCOCTL_R

Bits 0:7 - DCO Clock Frequency Control register

pub fn dco(&self) -> DCO_R

Bits 5:7 - DCO Frequency Select

pub fn mod_(&self) -> MOD_R

Bits 0:4 - Modulator Selection

impl R<u8, DIVA_A>

pub fn variant(&self) -> DIVA_A

Get enumerated values variant

pub fn is_diva_0(&self) -> bool

Checks if the value of the field is DIVA_0

pub fn is_diva_1(&self) -> bool

Checks if the value of the field is DIVA_1

pub fn is_diva_2(&self) -> bool

Checks if the value of the field is DIVA_2

pub fn is_diva_3(&self) -> bool

Checks if the value of the field is DIVA_3

impl R<u8, Reg<u8, _BCSCTL1>>

pub fn rsel0(&self) -> RSEL0_R

Bit 0 - Range Select Bit 0

pub fn rsel1(&self) -> RSEL1_R

Bit 1 - Range Select Bit 1

pub fn rsel2(&self) -> RSEL2_R

Bit 2 - Range Select Bit 2

pub fn rsel3(&self) -> RSEL3_R

Bit 3 - Range Select Bit 3

pub fn diva(&self) -> DIVA_R

Bits 4:5 - ACLK Divider 0

pub fn xts(&self) -> XTS_R

Bit 6 - LFXTCLK 0:Low Freq. / 1: High Freq.

pub fn xt2off(&self) -> XT2OFF_R

Bit 7 - Enable XT2CLK

pub fn bcsctl1(&self) -> BCSCTL1_R

Bits 0:7 - Basic Clock System Control 1 register

pub fn rsel(&self) -> RSEL_R

Bits 0:3 - Range Select

impl R<u8, DIVS_A>

pub fn variant(&self) -> DIVS_A

Get enumerated values variant

pub fn is_divs_0(&self) -> bool

Checks if the value of the field is DIVS_0

pub fn is_divs_1(&self) -> bool

Checks if the value of the field is DIVS_1

pub fn is_divs_2(&self) -> bool

Checks if the value of the field is DIVS_2

pub fn is_divs_3(&self) -> bool

Checks if the value of the field is DIVS_3

impl R<u8, DIVM_A>

pub fn variant(&self) -> DIVM_A

Get enumerated values variant

pub fn is_divm_0(&self) -> bool

Checks if the value of the field is DIVM_0

pub fn is_divm_1(&self) -> bool

Checks if the value of the field is DIVM_1

pub fn is_divm_2(&self) -> bool

Checks if the value of the field is DIVM_2

pub fn is_divm_3(&self) -> bool

Checks if the value of the field is DIVM_3

impl R<u8, SELM_A>

pub fn variant(&self) -> SELM_A

Get enumerated values variant

pub fn is_selm_0(&self) -> bool

Checks if the value of the field is SELM_0

pub fn is_selm_1(&self) -> bool

Checks if the value of the field is SELM_1

pub fn is_selm_2(&self) -> bool

Checks if the value of the field is SELM_2

pub fn is_selm_3(&self) -> bool

Checks if the value of the field is SELM_3

impl R<u8, Reg<u8, _BCSCTL2>>

pub fn divs(&self) -> DIVS_R

Bits 1:2 - SMCLK Divider 0

pub fn sels(&self) -> SELS_R

Bit 3 - SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK

pub fn divm(&self) -> DIVM_R

Bits 4:5 - MCLK Divider 0

pub fn selm(&self) -> SELM_R

Bits 6:7 - MCLK Source Select 0

impl R<u8, CAREF_A>

pub fn variant(&self) -> CAREF_A

Get enumerated values variant

pub fn is_caref_0(&self) -> bool

Checks if the value of the field is CAREF_0

pub fn is_caref_1(&self) -> bool

Checks if the value of the field is CAREF_1

pub fn is_caref_2(&self) -> bool

Checks if the value of the field is CAREF_2

pub fn is_caref_3(&self) -> bool

Checks if the value of the field is CAREF_3

impl R<u8, Reg<u8, _CACTL1>>

pub fn caifg(&self) -> CAIFG_R

Bit 0 - Comp. A Interrupt Flag

pub fn caie(&self) -> CAIE_R

Bit 1 - Comp. A Interrupt Enable

pub fn caies(&self) -> CAIES_R

Bit 2 - Comp. A Int. Edge Select: 0:rising / 1:falling

pub fn caon(&self) -> CAON_R

Bit 3 - Comp. A enable

pub fn caref(&self) -> CAREF_R

Bits 4:5 - Comp. A Internal Reference Select 0

pub fn carsel(&self) -> CARSEL_R

Bit 6 - Comp. A Internal Reference Enable

pub fn caex(&self) -> CAEX_R

Bit 7 - Comp. A Exchange Inputs

impl R<u8, Reg<u8, _CACTL2>>

pub fn caout(&self) -> CAOUT_R

Bit 0 - Comp. A Output

pub fn caf(&self) -> CAF_R

Bit 1 - Comp. A Enable Output Filter

pub fn p2ca0(&self) -> P2CA0_R

Bit 2 - Comp. A +Terminal Multiplexer

pub fn p2ca1(&self) -> P2CA1_R

Bit 3 - Comp. A -Terminal Multiplexer

pub fn p2ca2(&self) -> P2CA2_R

Bit 4 - Comp. A -Terminal Multiplexer

pub fn p2ca3(&self) -> P2CA3_R

Bit 5 - Comp. A -Terminal Multiplexer

pub fn p2ca4(&self) -> P2CA4_R

Bit 6 - Comp. A +Terminal Multiplexer

pub fn cashort(&self) -> CASHORT_R

Bit 7 - Comp. A Short + and - Terminals

pub fn p2ca(&self) -> P2CA_R

Bits 2:6 - Comparator A +/-Terminal Multiplexer register

impl R<u8, Reg<u8, _CAPD>>

pub fn capd0(&self) -> CAPD0_R

Bit 0 - Comp. A Disable Input Buffer of Port Register .0

pub fn capd1(&self) -> CAPD1_R

Bit 1 - Comp. A Disable Input Buffer of Port Register .1

pub fn capd2(&self) -> CAPD2_R

Bit 2 - Comp. A Disable Input Buffer of Port Register .2

pub fn capd3(&self) -> CAPD3_R

Bit 3 - Comp. A Disable Input Buffer of Port Register .3

pub fn capd4(&self) -> CAPD4_R

Bit 4 - Comp. A Disable Input Buffer of Port Register .4

pub fn capd5(&self) -> CAPD5_R

Bit 5 - Comp. A Disable Input Buffer of Port Register .5

pub fn capd6(&self) -> CAPD6_R

Bit 6 - Comp. A Disable Input Buffer of Port Register .6

pub fn capd7(&self) -> CAPD7_R

Bit 7 - Comp. A Disable Input Buffer of Port Register .7

pub fn capd(&self) -> CAPD_R

Bits 0:7 - Comparator A Port Disable register

impl R<u8, Reg<u8, _CALDCO_1MHZ>>

pub fn caldco_1mhz(&self) -> CALDCO_1MHZ_R

Bits 0:7 - DCOCTL Calibration Data register

impl R<u8, Reg<u8, _CALBC1_1MHZ>>

pub fn calbc1_1mhz(&self) -> CALBC1_1MHZ_R

Bits 0:7 - BCSCTL1 Calibration Data register

impl R<u8, WDTPW_A>

pub fn variant(&self) -> Variant<u8, WDTPW_A>

Get enumerated values variant

pub fn is_password(&self) -> bool

Checks if the value of the field is PASSWORD

impl R<u16, Reg<u16, _WDTCTL>>

pub fn wdtis0(&self) -> WDTIS0_R

Bit 0 - WDTIS0

pub fn wdtis1(&self) -> WDTIS1_R

Bit 1 - WDTIS1

pub fn wdtssel(&self) -> WDTSSEL_R

Bit 2 - WDTSSEL

pub fn wdtcntcl(&self) -> WDTCNTCL_R

Bit 3 - WDTCNTCL

pub fn wdttmsel(&self) -> WDTTMSEL_R

Bit 4 - WDTTMSEL

pub fn wdtnmi(&self) -> WDTNMI_R

Bit 5 - WDTNMI

pub fn wdtnmies(&self) -> WDTNMIES_R

Bit 6 - WDTNMIES

pub fn wdthold(&self) -> WDTHOLD_R

Bit 7 - WDTHOLD

pub fn wdtpw(&self) -> WDTPW_R

Bits 8:15 - Watchdog Timer Password

impl R<u8, FWKEY_A>

pub fn variant(&self) -> Variant<u8, FWKEY_A>

Get enumerated values variant

pub fn is_password(&self) -> bool

Checks if the value of the field is PASSWORD

impl R<u16, Reg<u16, _FCTL1>>

pub fn erase(&self) -> ERASE_R

Bit 1 - Enable bit for Flash segment erase

pub fn meras(&self) -> MERAS_R

Bit 2 - Enable bit for Flash mass erase

pub fn wrt(&self) -> WRT_R

Bit 6 - Enable bit for Flash write

pub fn blkwrt(&self) -> BLKWRT_R

Bit 7 - Enable bit for Flash segment write

pub fn fwkey(&self) -> FWKEY_R

Bits 8:15 - FCTL1 Password

impl R<u8, FSSEL_A>

pub fn variant(&self) -> FSSEL_A

Get enumerated values variant

pub fn is_fssel_0(&self) -> bool

Checks if the value of the field is FSSEL_0

pub fn is_fssel_1(&self) -> bool

Checks if the value of the field is FSSEL_1

pub fn is_fssel_2(&self) -> bool

Checks if the value of the field is FSSEL_2

pub fn is_fssel_3(&self) -> bool

Checks if the value of the field is FSSEL_3

impl R<u8, FWKEY_A>

pub fn variant(&self) -> Variant<u8, FWKEY_A>

Get enumerated values variant

pub fn is_password(&self) -> bool

Checks if the value of the field is PASSWORD

impl R<u16, Reg<u16, _FCTL2>>

pub fn fn0(&self) -> FN0_R

Bit 0 - Divide Flash clock by 1 to 64 using FN0 to FN5 according to:

pub fn fn1(&self) -> FN1_R

Bit 1 - 32FN5 + 16FN4 + 8FN3 + 4FN2 + 2*FN1 + FN0 + 1

pub fn fn2(&self) -> FN2_R

Bit 2 - FN2

pub fn fn3(&self) -> FN3_R

Bit 3 - FN3

pub fn fn4(&self) -> FN4_R

Bit 4 - FN4

pub fn fn5(&self) -> FN5_R

Bit 5 - FN5

pub fn fssel(&self) -> FSSEL_R

Bits 6:7 - Flash clock select 0 / / to distinguish from USART SSELx

pub fn fwkey(&self) -> FWKEY_R

Bits 8:15 - FCTL2 Password

pub fn fn_(&self) -> FN_R

Bits 0:5 - Flash Controller Clock Divider

impl R<u8, FWKEY_A>

pub fn variant(&self) -> Variant<u8, FWKEY_A>

Get enumerated values variant

pub fn is_password(&self) -> bool

Checks if the value of the field is PASSWORD

impl R<u16, Reg<u16, _FCTL3>>

pub fn busy(&self) -> BUSY_R

Bit 0 - Flash busy: 1

pub fn keyv(&self) -> KEYV_R

Bit 1 - Flash Key violation flag

pub fn accvifg(&self) -> ACCVIFG_R

Bit 2 - Flash Access violation flag

pub fn wait(&self) -> WAIT_R

Bit 3 - Wait flag for segment write

pub fn lock(&self) -> LOCK_R

Bit 4 - Lock bit: 1 - Flash is locked (read only)

pub fn emex(&self) -> EMEX_R

Bit 5 - Flash Emergency Exit

pub fn locka(&self) -> LOCKA_R

Bit 6 - Segment A Lock bit: read = 1 - Segment is locked (read only)

pub fn fail(&self) -> FAIL_R

Bit 7 - Last Program or Erase failed

pub fn fwkey(&self) -> FWKEY_R

Bits 8:15 - FCTL3 Password

impl R<u8, MC_A>

pub fn variant(&self) -> MC_A

Get enumerated values variant

pub fn is_mc_0(&self) -> bool

Checks if the value of the field is MC_0

pub fn is_mc_1(&self) -> bool

Checks if the value of the field is MC_1

pub fn is_mc_2(&self) -> bool

Checks if the value of the field is MC_2

pub fn is_mc_3(&self) -> bool

Checks if the value of the field is MC_3

impl R<u8, ID_A>

pub fn variant(&self) -> ID_A

Get enumerated values variant

pub fn is_id_0(&self) -> bool

Checks if the value of the field is ID_0

pub fn is_id_1(&self) -> bool

Checks if the value of the field is ID_1

pub fn is_id_2(&self) -> bool

Checks if the value of the field is ID_2

pub fn is_id_3(&self) -> bool

Checks if the value of the field is ID_3

impl R<u8, TASSEL_A>

pub fn variant(&self) -> TASSEL_A

Get enumerated values variant

pub fn is_tassel_0(&self) -> bool

Checks if the value of the field is TASSEL_0

pub fn is_tassel_1(&self) -> bool

Checks if the value of the field is TASSEL_1

pub fn is_tassel_2(&self) -> bool

Checks if the value of the field is TASSEL_2

pub fn is_tassel_3(&self) -> bool

Checks if the value of the field is TASSEL_3

impl R<u16, Reg<u16, _TACTL>>

pub fn taifg(&self) -> TAIFG_R

Bit 0 - Timer A counter interrupt flag

pub fn taie(&self) -> TAIE_R

Bit 1 - Timer A counter interrupt enable

pub fn taclr(&self) -> TACLR_R

Bit 2 - Timer A counter clear

pub fn mc(&self) -> MC_R

Bits 4:5 - Timer A mode control 1

pub fn id(&self) -> ID_R

Bits 6:7 - Timer A clock input divider 1

pub fn tassel(&self) -> TASSEL_R

Bits 8:9 - Timer A clock source select 1

impl R<u8, OUTMOD_A>

pub fn variant(&self) -> OUTMOD_A

Get enumerated values variant

pub fn is_outmod_0(&self) -> bool

Checks if the value of the field is OUTMOD_0

pub fn is_outmod_1(&self) -> bool

Checks if the value of the field is OUTMOD_1

pub fn is_outmod_2(&self) -> bool

Checks if the value of the field is OUTMOD_2

pub fn is_outmod_3(&self) -> bool

Checks if the value of the field is OUTMOD_3

pub fn is_outmod_4(&self) -> bool

Checks if the value of the field is OUTMOD_4

pub fn is_outmod_5(&self) -> bool

Checks if the value of the field is OUTMOD_5

pub fn is_outmod_6(&self) -> bool

Checks if the value of the field is OUTMOD_6

pub fn is_outmod_7(&self) -> bool

Checks if the value of the field is OUTMOD_7

impl R<u8, CCIS_A>

pub fn variant(&self) -> CCIS_A

Get enumerated values variant

pub fn is_ccis_0(&self) -> bool

Checks if the value of the field is CCIS_0

pub fn is_ccis_1(&self) -> bool

Checks if the value of the field is CCIS_1

pub fn is_ccis_2(&self) -> bool

Checks if the value of the field is CCIS_2

pub fn is_ccis_3(&self) -> bool

Checks if the value of the field is CCIS_3

impl R<u8, CM_A>

pub fn variant(&self) -> CM_A

Get enumerated values variant

pub fn is_cm_0(&self) -> bool

Checks if the value of the field is CM_0

pub fn is_cm_1(&self) -> bool

Checks if the value of the field is CM_1

pub fn is_cm_2(&self) -> bool

Checks if the value of the field is CM_2

pub fn is_cm_3(&self) -> bool

Checks if the value of the field is CM_3

impl R<u16, Reg<u16, _TACCTL0>>

pub fn ccifg(&self) -> CCIFG_R

Bit 0 - Capture/compare interrupt flag

pub fn cov(&self) -> COV_R

Bit 1 - Capture/compare overflow flag

pub fn out(&self) -> OUT_R

Bit 2 - PWM Output signal if output mode 0

pub fn cci(&self) -> CCI_R

Bit 3 - Capture input signal (read)

pub fn ccie(&self) -> CCIE_R

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&self) -> OUTMOD_R

Bits 5:7 - Output mode 2

pub fn cap(&self) -> CAP_R

Bit 8 - Capture mode: 1 /Compare mode : 0

pub fn scci(&self) -> SCCI_R

Bit 10 - Latched capture signal (read)

pub fn scs(&self) -> SCS_R

Bit 11 - Capture sychronize

pub fn ccis(&self) -> CCIS_R

Bits 12:13 - Capture input select 1

pub fn cm(&self) -> CM_R

Bits 14:15 - Capture mode 1

impl R<u8, OUTMOD_A>

pub fn variant(&self) -> OUTMOD_A

Get enumerated values variant

pub fn is_outmod_0(&self) -> bool

Checks if the value of the field is OUTMOD_0

pub fn is_outmod_1(&self) -> bool

Checks if the value of the field is OUTMOD_1

pub fn is_outmod_2(&self) -> bool

Checks if the value of the field is OUTMOD_2

pub fn is_outmod_3(&self) -> bool

Checks if the value of the field is OUTMOD_3

pub fn is_outmod_4(&self) -> bool

Checks if the value of the field is OUTMOD_4

pub fn is_outmod_5(&self) -> bool

Checks if the value of the field is OUTMOD_5

pub fn is_outmod_6(&self) -> bool

Checks if the value of the field is OUTMOD_6

pub fn is_outmod_7(&self) -> bool

Checks if the value of the field is OUTMOD_7

impl R<u8, CCIS_A>

pub fn variant(&self) -> CCIS_A

Get enumerated values variant

pub fn is_ccis_0(&self) -> bool

Checks if the value of the field is CCIS_0

pub fn is_ccis_1(&self) -> bool

Checks if the value of the field is CCIS_1

pub fn is_ccis_2(&self) -> bool

Checks if the value of the field is CCIS_2

pub fn is_ccis_3(&self) -> bool

Checks if the value of the field is CCIS_3

impl R<u8, CM_A>

pub fn variant(&self) -> CM_A

Get enumerated values variant

pub fn is_cm_0(&self) -> bool

Checks if the value of the field is CM_0

pub fn is_cm_1(&self) -> bool

Checks if the value of the field is CM_1

pub fn is_cm_2(&self) -> bool

Checks if the value of the field is CM_2

pub fn is_cm_3(&self) -> bool

Checks if the value of the field is CM_3

impl R<u16, Reg<u16, _TACCTL1>>

pub fn ccifg(&self) -> CCIFG_R

Bit 0 - Capture/compare interrupt flag

pub fn cov(&self) -> COV_R

Bit 1 - Capture/compare overflow flag

pub fn out(&self) -> OUT_R

Bit 2 - PWM Output signal if output mode 0

pub fn cci(&self) -> CCI_R

Bit 3 - Capture input signal (read)

pub fn ccie(&self) -> CCIE_R

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&self) -> OUTMOD_R

Bits 5:7 - Output mode 2

pub fn cap(&self) -> CAP_R

Bit 8 - Capture mode: 1 /Compare mode : 0

pub fn scci(&self) -> SCCI_R

Bit 10 - Latched capture signal (read)

pub fn scs(&self) -> SCS_R

Bit 11 - Capture sychronize

pub fn ccis(&self) -> CCIS_R

Bits 12:13 - Capture input select 1

pub fn cm(&self) -> CM_R

Bits 14:15 - Capture mode 1

impl R<u8, TAIV_A>

pub fn variant(&self) -> Variant<u8, TAIV_A>

Get enumerated values variant

pub fn is_none(&self) -> bool

Checks if the value of the field is NONE

pub fn is_taccr1(&self) -> bool

Checks if the value of the field is TACCR1

pub fn is_taifg(&self) -> bool

Checks if the value of the field is TAIFG

impl R<u16, Reg<u16, _TAIV>>

pub fn taiv(&self) -> TAIV_R

Bits 0:3 - Timer A Interrupt Vector value

impl R<u16, Reg<u16, _TAR>>

pub fn tar(&self) -> TAR_R

Bits 0:15 - Timer A Counter Register

impl R<u16, Reg<u16, _TACCR0>>

pub fn taccr0(&self) -> TACCR0_R

Bits 0:15 - Timer A Capture/Compare register 0

impl R<u16, Reg<u16, _TACCR1>>

pub fn taccr1(&self) -> TACCR1_R

Bits 0:15 - Timer A Capture/Compare register 1

Trait Implementations

impl<U, T, FI> PartialEq<FI> for R<U, T> where
    U: PartialEq,
    FI: Copy + Into<U>, 

fn eq(&self, other: &FI) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]pub fn ne(&self, other: &Rhs) -> bool

This method tests for !=.