Struct msp430fr6972::usci_b1_spi_mode::RegisterBlock[−][src]

#[repr(C)]
pub struct RegisterBlock {
    pub ucb1ctl1_spi: Reg<UCB1CTL1_SPI_SPEC>,
    pub ucb1ctl0_spi: Reg<UCB1CTL0_SPI_SPEC>,
    pub ucb1br0_spi: Reg<UCB1BR0_SPI_SPEC>,
    pub ucb1br1_spi: Reg<UCB1BR1_SPI_SPEC>,
    pub ucb1rxbuf_spi: Reg<UCB1RXBUF_SPI_SPEC>,
    pub ucb1txbuf_spi: Reg<UCB1TXBUF_SPI_SPEC>,
    pub ucb1ie_spi: Reg<UCB1IE_SPI_SPEC>,
    pub ucb1ifg_spi: Reg<UCB1IFG_SPI_SPEC>,
    pub ucb1iv_spi: Reg<UCB1IV_SPI_SPEC>,
    // some fields omitted
}

Register block

Fields

ucb1ctl1_spi: Reg<UCB1CTL1_SPI_SPEC>

0x00 - USCI B1 Control Register 1

ucb1ctl0_spi: Reg<UCB1CTL0_SPI_SPEC>

0x01 - USCI B1 Control Register 0

ucb1br0_spi: Reg<UCB1BR0_SPI_SPEC>

0x06 - USCI B1 Baud Rate 0

ucb1br1_spi: Reg<UCB1BR1_SPI_SPEC>

0x07 - USCI B1 Baud Rate 1

ucb1rxbuf_spi: Reg<UCB1RXBUF_SPI_SPEC>

0x0c - USCI B1 Receive Buffer

ucb1txbuf_spi: Reg<UCB1TXBUF_SPI_SPEC>

0x0e - USCI B1 Transmit Buffer

ucb1ie_spi: Reg<UCB1IE_SPI_SPEC>

0x2a - USCI B1 Interrupt Enable Register

ucb1ifg_spi: Reg<UCB1IFG_SPI_SPEC>

0x2c - USCI B1 Interrupt Flags Register

ucb1iv_spi: Reg<UCB1IV_SPI_SPEC>

0x2e - USCI B1 Interrupt Vector Register

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