Struct msp430fr6972::dma::dmactl0::DMA1TSEL_W [−][src]
pub struct DMA1TSEL_W<'a> { /* fields omitted */ }
Field DMA1TSEL
writer - DMA channel 1 transfer select bit 0
Implementations
impl<'a> DMA1TSEL_W<'a>
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impl<'a> DMA1TSEL_W<'a>
[src]pub fn variant(self, variant: DMA1TSEL_A) -> &'a mut W
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pub fn variant(self, variant: DMA1TSEL_A) -> &'a mut W
[src]Writes variant
to the field
pub fn dma1tsel_0(self) -> &'a mut W
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pub fn dma1tsel_0(self) -> &'a mut W
[src]DMA channel 1 transfer select 0: DMA_REQ (sw)
pub fn dma1tsel_1(self) -> &'a mut W
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pub fn dma1tsel_1(self) -> &'a mut W
[src]DMA channel 1 transfer select 1:
pub fn dma1tsel_2(self) -> &'a mut W
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pub fn dma1tsel_2(self) -> &'a mut W
[src]DMA channel 1 transfer select 2:
pub fn dma1tsel_3(self) -> &'a mut W
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pub fn dma1tsel_3(self) -> &'a mut W
[src]DMA channel 1 transfer select 3:
pub fn dma1tsel_4(self) -> &'a mut W
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pub fn dma1tsel_4(self) -> &'a mut W
[src]DMA channel 1 transfer select 4:
pub fn dma1tsel_5(self) -> &'a mut W
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pub fn dma1tsel_5(self) -> &'a mut W
[src]DMA channel 1 transfer select 5:
pub fn dma1tsel_6(self) -> &'a mut W
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pub fn dma1tsel_6(self) -> &'a mut W
[src]DMA channel 1 transfer select 6:
pub fn dma1tsel_7(self) -> &'a mut W
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pub fn dma1tsel_7(self) -> &'a mut W
[src]DMA channel 1 transfer select 7:
pub fn dma1tsel_8(self) -> &'a mut W
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pub fn dma1tsel_8(self) -> &'a mut W
[src]DMA channel 1 transfer select 8:
pub fn dma1tsel_9(self) -> &'a mut W
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pub fn dma1tsel_9(self) -> &'a mut W
[src]DMA channel 1 transfer select 9:
pub fn dma1tsel_10(self) -> &'a mut W
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pub fn dma1tsel_10(self) -> &'a mut W
[src]DMA channel 1 transfer select 10:
pub fn dma1tsel_11(self) -> &'a mut W
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pub fn dma1tsel_11(self) -> &'a mut W
[src]DMA channel 1 transfer select 11:
pub fn dma1tsel_12(self) -> &'a mut W
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pub fn dma1tsel_12(self) -> &'a mut W
[src]DMA channel 1 transfer select 12:
pub fn dma1tsel_13(self) -> &'a mut W
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pub fn dma1tsel_13(self) -> &'a mut W
[src]DMA channel 1 transfer select 13:
pub fn dma1tsel_14(self) -> &'a mut W
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pub fn dma1tsel_14(self) -> &'a mut W
[src]DMA channel 1 transfer select 14:
pub fn dma1tsel_15(self) -> &'a mut W
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pub fn dma1tsel_15(self) -> &'a mut W
[src]DMA channel 1 transfer select 15:
pub fn dma1tsel_16(self) -> &'a mut W
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pub fn dma1tsel_16(self) -> &'a mut W
[src]DMA channel 1 transfer select 16:
pub fn dma1tsel_17(self) -> &'a mut W
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pub fn dma1tsel_17(self) -> &'a mut W
[src]DMA channel 1 transfer select 17:
pub fn dma1tsel_18(self) -> &'a mut W
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pub fn dma1tsel_18(self) -> &'a mut W
[src]DMA channel 1 transfer select 18:
pub fn dma1tsel_19(self) -> &'a mut W
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pub fn dma1tsel_19(self) -> &'a mut W
[src]DMA channel 1 transfer select 19:
pub fn dma1tsel_20(self) -> &'a mut W
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pub fn dma1tsel_20(self) -> &'a mut W
[src]DMA channel 1 transfer select 20:
pub fn dma1tsel_21(self) -> &'a mut W
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pub fn dma1tsel_21(self) -> &'a mut W
[src]DMA channel 1 transfer select 21:
pub fn dma1tsel_22(self) -> &'a mut W
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pub fn dma1tsel_22(self) -> &'a mut W
[src]DMA channel 1 transfer select 22:
pub fn dma1tsel_23(self) -> &'a mut W
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pub fn dma1tsel_23(self) -> &'a mut W
[src]DMA channel 1 transfer select 23:
pub fn dma1tsel_24(self) -> &'a mut W
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pub fn dma1tsel_24(self) -> &'a mut W
[src]DMA channel 1 transfer select 24:
pub fn dma1tsel_25(self) -> &'a mut W
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pub fn dma1tsel_25(self) -> &'a mut W
[src]DMA channel 1 transfer select 25:
pub fn dma1tsel_26(self) -> &'a mut W
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pub fn dma1tsel_26(self) -> &'a mut W
[src]DMA channel 1 transfer select 26:
pub fn dma1tsel_27(self) -> &'a mut W
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pub fn dma1tsel_27(self) -> &'a mut W
[src]DMA channel 1 transfer select 27:
pub fn dma1tsel_28(self) -> &'a mut W
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pub fn dma1tsel_28(self) -> &'a mut W
[src]DMA channel 1 transfer select 28:
pub fn dma1tsel_29(self) -> &'a mut W
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pub fn dma1tsel_29(self) -> &'a mut W
[src]DMA channel 1 transfer select 29:
pub fn dma1tsel_30(self) -> &'a mut W
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pub fn dma1tsel_30(self) -> &'a mut W
[src]DMA channel 1 transfer select 30: previous DMA channel DMA0IFG
pub fn dma1tsel_31(self) -> &'a mut W
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pub fn dma1tsel_31(self) -> &'a mut W
[src]DMA channel 1 transfer select 31: ext. Trigger (DMAE0)