Struct msp430fr6972::adc12::adc12ctl1::R [−][src]
pub struct R(_);
Register ADC12CTL1
reader
Implementations
impl R
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impl R
[src]pub fn adc12busy(&self) -> ADC12BUSY_R
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pub fn adc12busy(&self) -> ADC12BUSY_R
[src]Bit 0 - ADC12 Busy
pub fn adc12conseq(&self) -> ADC12CONSEQ_R
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pub fn adc12conseq(&self) -> ADC12CONSEQ_R
[src]Bits 1:2 - ADC12 Conversion Sequence Select Bit: 0
pub fn adc12ssel(&self) -> ADC12SSEL_R
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pub fn adc12ssel(&self) -> ADC12SSEL_R
[src]Bits 3:4 - ADC12 Clock Source Select Bit: 0
pub fn adc12div(&self) -> ADC12DIV_R
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pub fn adc12div(&self) -> ADC12DIV_R
[src]Bits 5:7 - ADC12 Clock Divider Select Bit: 0
pub fn adc12issh(&self) -> ADC12ISSH_R
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pub fn adc12issh(&self) -> ADC12ISSH_R
[src]Bit 8 - ADC12 Invert Sample Hold Signal
pub fn adc12shp(&self) -> ADC12SHP_R
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pub fn adc12shp(&self) -> ADC12SHP_R
[src]Bit 9 - ADC12 Sample/Hold Pulse Mode
pub fn adc12shs(&self) -> ADC12SHS_R
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pub fn adc12shs(&self) -> ADC12SHS_R
[src]Bits 10:12 - ADC12 Sample/Hold Source Bit: 0
pub fn adc12pdiv(&self) -> ADC12PDIV_R
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pub fn adc12pdiv(&self) -> ADC12PDIV_R
[src]Bits 13:14 - ADC12 Predivider Bit: 0
Methods from Deref<Target = R<ADC12CTL1_SPEC>>
Trait Implementations
impl From<R<ADC12CTL1_SPEC>> for R
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impl From<R<ADC12CTL1_SPEC>> for R
[src]fn from(reader: R<ADC12CTL1_SPEC>) -> Self
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fn from(reader: R<ADC12CTL1_SPEC>) -> Self
[src]Performs the conversion.