1#![feature(abi_msp430_interrupt)]
2#![doc = "Peripheral access API for MSP430FR5994 microcontrollers (generated using svd2rust v0.36.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
3#![allow(non_camel_case_types)]
4#![allow(non_snake_case)]
5#![no_std]
6#![cfg_attr(docsrs, feature(doc_auto_cfg))]
7#[allow(unused_imports)]
8use generic::*;
9#[doc = "Common register and bit access and modify traits"]
10pub mod generic;
11#[cfg(feature = "rt")]
12extern "msp430-interrupt" {
13 fn LEA();
14 fn PORT8();
15 fn PORT7();
16 fn EUSCI_B3();
17 fn EUSCI_B2();
18 fn EUSCI_B1();
19 fn EUSCI_A3();
20 fn EUSCI_A2();
21 fn PORT6();
22 fn PORT5();
23 fn TIMER4_A1();
24 fn TIMER4_A0();
25 fn AES256();
26 fn RTC_C();
27 fn PORT4();
28 fn PORT3();
29 fn TIMER3_A1();
30 fn TIMER3_A0();
31 fn PORT2();
32 fn TIMER2_A1();
33 fn TIMER2_A0();
34 fn PORT1();
35 fn TIMER1_A1();
36 fn TIMER1_A0();
37 fn DMA();
38 fn EUSCI_A1();
39 fn TIMER0_A1();
40 fn TIMER0_A0();
41 fn ADC12_B();
42 fn EUSCI_B0();
43 fn EUSCI_A0();
44 fn WDT();
45 fn TIMER0_B1();
46 fn TIMER0_B0();
47 fn COMP_E();
48 fn UNMI();
49 fn SYSNMI();
50}
51#[doc(hidden)]
52#[repr(C)]
53pub union Vector {
54 _handler: unsafe extern "msp430-interrupt" fn(),
55 _reserved: u16,
56}
57#[cfg(feature = "rt")]
58#[doc(hidden)]
59#[link_section = ".vector_table.interrupts"]
60#[no_mangle]
61#[used]
62pub static __INTERRUPTS: [Vector; 63] = [
63 Vector {_reserved : 0}, Vector {_reserved : 0},
65 Vector {_reserved : 0},
66 Vector {_reserved : 0},
67 Vector {_reserved : 0},
68 Vector {_reserved : 0},
69 Vector {_reserved : 0},
70 Vector {_reserved : 0},
71 Vector {_reserved : 0},
72 Vector {_reserved : 0},
73
74 Vector {_reserved : 0}, Vector {_reserved : 0},
76 Vector {_reserved : 0},
77 Vector {_reserved : 0},
78 Vector {_reserved : 0},
79 Vector {_reserved : 0},
80 Vector {_reserved : 0},
81 Vector {_reserved : 0},
82 Vector {_reserved : 0},
83 Vector {_reserved : 0},
84
85 Vector {_reserved : 0}, Vector {_reserved : 0},
87 Vector {_reserved : 0},
88 Vector {_reserved : 0},
89 Vector {_reserved : 0},
90 Vector {_reserved : 0},
91
92 Vector { _handler: LEA },
93 Vector { _handler: PORT8 },
94 Vector { _handler: PORT7 },
95 Vector { _handler: EUSCI_B3 },
96 Vector { _handler: EUSCI_B2 },
97 Vector { _handler: EUSCI_B1 },
98 Vector { _handler: EUSCI_A3 },
99 Vector { _handler: EUSCI_A2 },
100 Vector { _handler: PORT6 },
101 Vector { _handler: PORT5 },
102 Vector { _handler: TIMER4_A1 },
103 Vector { _handler: TIMER4_A0 },
104 Vector { _handler: AES256 },
105 Vector { _handler: RTC_C },
106 Vector { _handler: PORT4 },
107 Vector { _handler: PORT3 },
108 Vector { _handler: TIMER3_A1 },
109 Vector { _handler: TIMER3_A0 },
110 Vector { _handler: PORT2 },
111 Vector { _handler: TIMER2_A1 },
112 Vector { _handler: TIMER2_A0 },
113 Vector { _handler: PORT1 },
114 Vector { _handler: TIMER1_A1 },
115 Vector { _handler: TIMER1_A0 },
116 Vector { _handler: DMA },
117 Vector { _handler: EUSCI_A1 },
118 Vector { _handler: TIMER0_A1 },
119 Vector { _handler: TIMER0_A0 },
120 Vector { _handler: ADC12_B },
121 Vector { _handler: EUSCI_B0 },
122 Vector { _handler: EUSCI_A0 },
123 Vector { _handler: WDT },
124 Vector { _handler: TIMER0_B1 },
125 Vector { _handler: TIMER0_B0 },
126 Vector { _handler: COMP_E },
127 Vector { _handler: UNMI },
128 Vector { _handler: SYSNMI },
129];
130#[doc = r"Enumeration of all the interrupts. This enum is seldom used in application or library crates. It is present primarily for documenting the device's implemented interrupts."]
131#[derive(Copy, Clone, Debug, PartialEq, Eq)]
132#[repr(u16)]
133pub enum Interrupt {
134 #[doc = "17 - 0xFFB4"]
135 LEA = 17,
136 #[doc = "18 - 0xFFB6"]
137 PORT8 = 18,
138 #[doc = "19 - 0xFFB8"]
139 PORT7 = 19,
140 #[doc = "20 - 0xFFBA"]
141 EUSCI_B3 = 20,
142 #[doc = "21 - 0xFFBC"]
143 EUSCI_B2 = 21,
144 #[doc = "22 - 0xFFBE"]
145 EUSCI_B1 = 22,
146 #[doc = "23 - 0xFFC0"]
147 EUSCI_A3 = 23,
148 #[doc = "24 - 0xFFC2"]
149 EUSCI_A2 = 24,
150 #[doc = "25 - 0xFFC4"]
151 PORT6 = 25,
152 #[doc = "26 - 0xFFC6"]
153 PORT5 = 26,
154 #[doc = "27 - 0xFFC8"]
155 TIMER4_A1 = 27,
156 #[doc = "28 - 0xFFCA"]
157 TIMER4_A0 = 28,
158 #[doc = "29 - 0xFFCC"]
159 AES256 = 29,
160 #[doc = "30 - 0xFFCE"]
161 RTC_C = 30,
162 #[doc = "31 - 0xFFD0"]
163 PORT4 = 31,
164 #[doc = "32 - 0xFFD2"]
165 PORT3 = 32,
166 #[doc = "33 - 0xFFD4"]
167 TIMER3_A1 = 33,
168 #[doc = "34 - 0xFFD6"]
169 TIMER3_A0 = 34,
170 #[doc = "35 - 0xFFD8"]
171 PORT2 = 35,
172 #[doc = "36 - 0xFFDA"]
173 TIMER2_A1 = 36,
174 #[doc = "37 - 0xFFDC"]
175 TIMER2_A0 = 37,
176 #[doc = "38 - 0xFFDE"]
177 PORT1 = 38,
178 #[doc = "39 - 0xFFE0"]
179 TIMER1_A1 = 39,
180 #[doc = "40 - 0xFFE2"]
181 TIMER1_A0 = 40,
182 #[doc = "41 - 0xFFE4"]
183 DMA = 41,
184 #[doc = "42 - 0xFFE6"]
185 EUSCI_A1 = 42,
186 #[doc = "43 - 0xFFE8"]
187 TIMER0_A1 = 43,
188 #[doc = "44 - 0xFFEA"]
189 TIMER0_A0 = 44,
190 #[doc = "45 - 0xFFEC"]
191 ADC12_B = 45,
192 #[doc = "46 - 0xFFEE"]
193 EUSCI_B0 = 46,
194 #[doc = "47 - 0xFFF0"]
195 EUSCI_A0 = 47,
196 #[doc = "48 - 0xFFF2"]
197 WDT = 48,
198 #[doc = "49 - 0xFFF4"]
199 TIMER0_B1 = 49,
200 #[doc = "50 - 0xFFF6"]
201 TIMER0_B0 = 50,
202 #[doc = "51 - 0xFFF8"]
203 COMP_E = 51,
204 #[doc = "52 - 0xFFFA"]
205 UNMI = 52,
206 #[doc = "53 - 0xFFFC"]
207 SYSNMI = 53,
208}
209#[doc = "P1"]
210pub type P1 = crate::Periph<p1::RegisterBlock, 0x0200>;
211impl core::fmt::Debug for P1 {
212 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
213 f.debug_struct("P1").finish()
214 }
215}
216#[doc = "P1"]
217pub mod p1;
218#[doc = "P2"]
219pub type P2 = crate::Periph<p2::RegisterBlock, 0x0200>;
220impl core::fmt::Debug for P2 {
221 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
222 f.debug_struct("P2").finish()
223 }
224}
225#[doc = "P2"]
226pub mod p2;
227#[doc = "P3"]
228pub type P3 = crate::Periph<p3::RegisterBlock, 0x0220>;
229impl core::fmt::Debug for P3 {
230 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
231 f.debug_struct("P3").finish()
232 }
233}
234#[doc = "P3"]
235pub mod p3;
236#[doc = "P4"]
237pub type P4 = crate::Periph<p4::RegisterBlock, 0x0220>;
238impl core::fmt::Debug for P4 {
239 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
240 f.debug_struct("P4").finish()
241 }
242}
243#[doc = "P4"]
244pub mod p4;
245#[doc = "P5"]
246pub type P5 = crate::Periph<p5::RegisterBlock, 0x0240>;
247impl core::fmt::Debug for P5 {
248 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
249 f.debug_struct("P5").finish()
250 }
251}
252#[doc = "P5"]
253pub mod p5;
254#[doc = "P6"]
255pub type P6 = crate::Periph<p6::RegisterBlock, 0x0240>;
256impl core::fmt::Debug for P6 {
257 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
258 f.debug_struct("P6").finish()
259 }
260}
261#[doc = "P6"]
262pub mod p6;
263#[doc = "P7"]
264pub type P7 = crate::Periph<p7::RegisterBlock, 0x0260>;
265impl core::fmt::Debug for P7 {
266 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
267 f.debug_struct("P7").finish()
268 }
269}
270#[doc = "P7"]
271pub mod p7;
272#[doc = "P8"]
273pub type P8 = crate::Periph<p8::RegisterBlock, 0x0260>;
274impl core::fmt::Debug for P8 {
275 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
276 f.debug_struct("P8").finish()
277 }
278}
279#[doc = "P8"]
280pub mod p8;
281#[doc = "P9"]
282pub type P9 = crate::Periph<p9::RegisterBlock, 0x0280>;
283impl core::fmt::Debug for P9 {
284 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
285 f.debug_struct("P9").finish()
286 }
287}
288#[doc = "P9"]
289pub mod p9;
290#[doc = "RTC_C"]
291pub type RtcC = crate::Periph<rtc_c::RegisterBlock, 0x04a0>;
292impl core::fmt::Debug for RtcC {
293 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
294 f.debug_struct("RtcC").finish()
295 }
296}
297#[doc = "RTC_C"]
298pub mod rtc_c;
299#[doc = "SFR"]
300pub type Sfr = crate::Periph<sfr::RegisterBlock, 0x0100>;
301impl core::fmt::Debug for Sfr {
302 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
303 f.debug_struct("Sfr").finish()
304 }
305}
306#[doc = "SFR"]
307pub mod sfr;
308#[doc = "PMM"]
309pub type Pmm = crate::Periph<pmm::RegisterBlock, 0x0120>;
310impl core::fmt::Debug for Pmm {
311 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
312 f.debug_struct("Pmm").finish()
313 }
314}
315#[doc = "PMM"]
316pub mod pmm;
317#[doc = "FRCTL_A"]
318pub type FrctlA = crate::Periph<frctl_a::RegisterBlock, 0x0140>;
319impl core::fmt::Debug for FrctlA {
320 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
321 f.debug_struct("FrctlA").finish()
322 }
323}
324#[doc = "FRCTL_A"]
325pub mod frctl_a;
326#[doc = "CRC"]
327pub type Crc = crate::Periph<crc::RegisterBlock, 0x0150>;
328impl core::fmt::Debug for Crc {
329 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
330 f.debug_struct("Crc").finish()
331 }
332}
333#[doc = "CRC"]
334pub mod crc;
335#[doc = "RAMCTL"]
336pub type Ramctl = crate::Periph<ramctl::RegisterBlock, 0x0158>;
337impl core::fmt::Debug for Ramctl {
338 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
339 f.debug_struct("Ramctl").finish()
340 }
341}
342#[doc = "RAMCTL"]
343pub mod ramctl;
344#[doc = "WDT_A"]
345pub type WdtA = crate::Periph<wdt_a::RegisterBlock, 0x015c>;
346impl core::fmt::Debug for WdtA {
347 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
348 f.debug_struct("WdtA").finish()
349 }
350}
351#[doc = "WDT_A"]
352pub mod wdt_a;
353#[doc = "CS"]
354pub type Cs = crate::Periph<cs::RegisterBlock, 0x0160>;
355impl core::fmt::Debug for Cs {
356 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
357 f.debug_struct("Cs").finish()
358 }
359}
360#[doc = "CS"]
361pub mod cs;
362#[doc = "SYS"]
363pub type Sys = crate::Periph<sys::RegisterBlock, 0x0180>;
364impl core::fmt::Debug for Sys {
365 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
366 f.debug_struct("Sys").finish()
367 }
368}
369#[doc = "SYS"]
370pub mod sys;
371#[doc = "REF_A"]
372pub type RefA = crate::Periph<ref_a::RegisterBlock, 0x01b0>;
373impl core::fmt::Debug for RefA {
374 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
375 f.debug_struct("RefA").finish()
376 }
377}
378#[doc = "REF_A"]
379pub mod ref_a;
380#[doc = "PJ"]
381pub type Pj = crate::Periph<pj::RegisterBlock, 0x0320>;
382impl core::fmt::Debug for Pj {
383 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
384 f.debug_struct("Pj").finish()
385 }
386}
387#[doc = "PJ"]
388pub mod pj;
389#[doc = "TA0"]
390pub type Ta0 = crate::Periph<ta0::RegisterBlock, 0x0340>;
391impl core::fmt::Debug for Ta0 {
392 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
393 f.debug_struct("Ta0").finish()
394 }
395}
396#[doc = "TA0"]
397pub mod ta0;
398#[doc = "TA1"]
399pub type Ta1 = crate::Periph<ta1::RegisterBlock, 0x0380>;
400impl core::fmt::Debug for Ta1 {
401 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
402 f.debug_struct("Ta1").finish()
403 }
404}
405#[doc = "TA1"]
406pub mod ta1;
407#[doc = "TB0"]
408pub type Tb0 = crate::Periph<tb0::RegisterBlock, 0x03c0>;
409impl core::fmt::Debug for Tb0 {
410 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
411 f.debug_struct("Tb0").finish()
412 }
413}
414#[doc = "TB0"]
415pub mod tb0;
416#[doc = "TA2"]
417pub type Ta2 = crate::Periph<ta2::RegisterBlock, 0x0400>;
418impl core::fmt::Debug for Ta2 {
419 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
420 f.debug_struct("Ta2").finish()
421 }
422}
423#[doc = "TA2"]
424pub mod ta2;
425#[doc = "CAPTIO0"]
426pub type Captio0 = crate::Periph<captio0::RegisterBlock, 0x043e>;
427impl core::fmt::Debug for Captio0 {
428 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
429 f.debug_struct("Captio0").finish()
430 }
431}
432#[doc = "CAPTIO0"]
433pub mod captio0;
434#[doc = "TA3"]
435pub type Ta3 = crate::Periph<ta3::RegisterBlock, 0x0440>;
436impl core::fmt::Debug for Ta3 {
437 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
438 f.debug_struct("Ta3").finish()
439 }
440}
441#[doc = "TA3"]
442pub mod ta3;
443#[doc = "CAPTIO1"]
444pub type Captio1 = crate::Periph<captio1::RegisterBlock, 0x047e>;
445impl core::fmt::Debug for Captio1 {
446 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
447 f.debug_struct("Captio1").finish()
448 }
449}
450#[doc = "CAPTIO1"]
451pub mod captio1;
452#[doc = "MPY32"]
453pub type Mpy32 = crate::Periph<mpy32::RegisterBlock, 0x04c0>;
454impl core::fmt::Debug for Mpy32 {
455 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
456 f.debug_struct("Mpy32").finish()
457 }
458}
459#[doc = "MPY32"]
460pub mod mpy32;
461#[doc = "DMA"]
462pub type Dma = crate::Periph<dma::RegisterBlock, 0x0500>;
463impl core::fmt::Debug for Dma {
464 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
465 f.debug_struct("Dma").finish()
466 }
467}
468#[doc = "DMA"]
469pub mod dma;
470#[doc = "MPU"]
471pub type Mpu = crate::Periph<mpu::RegisterBlock, 0x05a0>;
472impl core::fmt::Debug for Mpu {
473 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
474 f.debug_struct("Mpu").finish()
475 }
476}
477#[doc = "MPU"]
478pub mod mpu;
479#[doc = "eUSCI_A0"]
480pub type EUsciA0 = crate::Periph<e_usci_a0::RegisterBlock, 0x05c0>;
481impl core::fmt::Debug for EUsciA0 {
482 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
483 f.debug_struct("EUsciA0").finish()
484 }
485}
486#[doc = "eUSCI_A0"]
487pub mod e_usci_a0;
488#[doc = "eUSCI_A1"]
489pub type EUsciA1 = crate::Periph<e_usci_a1::RegisterBlock, 0x05e0>;
490impl core::fmt::Debug for EUsciA1 {
491 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
492 f.debug_struct("EUsciA1").finish()
493 }
494}
495#[doc = "eUSCI_A1"]
496pub mod e_usci_a1;
497#[doc = "eUSCI_A2"]
498pub type EUsciA2 = crate::Periph<e_usci_a2::RegisterBlock, 0x0600>;
499impl core::fmt::Debug for EUsciA2 {
500 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
501 f.debug_struct("EUsciA2").finish()
502 }
503}
504#[doc = "eUSCI_A2"]
505pub mod e_usci_a2;
506#[doc = "eUSCI_A3"]
507pub type EUsciA3 = crate::Periph<e_usci_a3::RegisterBlock, 0x0620>;
508impl core::fmt::Debug for EUsciA3 {
509 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
510 f.debug_struct("EUsciA3").finish()
511 }
512}
513#[doc = "eUSCI_A3"]
514pub mod e_usci_a3;
515#[doc = "eUSCI_B0"]
516pub type EUsciB0 = crate::Periph<e_usci_b0::RegisterBlock, 0x0640>;
517impl core::fmt::Debug for EUsciB0 {
518 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
519 f.debug_struct("EUsciB0").finish()
520 }
521}
522#[doc = "eUSCI_B0"]
523pub mod e_usci_b0;
524#[doc = "eUSCI_B1"]
525pub type EUsciB1 = crate::Periph<e_usci_b1::RegisterBlock, 0x0680>;
526impl core::fmt::Debug for EUsciB1 {
527 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
528 f.debug_struct("EUsciB1").finish()
529 }
530}
531#[doc = "eUSCI_B1"]
532pub mod e_usci_b1;
533#[doc = "eUSCI_B2"]
534pub type EUsciB2 = crate::Periph<e_usci_b2::RegisterBlock, 0x06c0>;
535impl core::fmt::Debug for EUsciB2 {
536 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
537 f.debug_struct("EUsciB2").finish()
538 }
539}
540#[doc = "eUSCI_B2"]
541pub mod e_usci_b2;
542#[doc = "eUSCI_B3"]
543pub type EUsciB3 = crate::Periph<e_usci_b3::RegisterBlock, 0x0700>;
544impl core::fmt::Debug for EUsciB3 {
545 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
546 f.debug_struct("EUsciB3").finish()
547 }
548}
549#[doc = "eUSCI_B3"]
550pub mod e_usci_b3;
551#[doc = "TA4"]
552pub type Ta4 = crate::Periph<ta4::RegisterBlock, 0x07c0>;
553impl core::fmt::Debug for Ta4 {
554 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
555 f.debug_struct("Ta4").finish()
556 }
557}
558#[doc = "TA4"]
559pub mod ta4;
560#[doc = "ADC12_B"]
561pub type Adc12B = crate::Periph<adc12_b::RegisterBlock, 0x0800>;
562impl core::fmt::Debug for Adc12B {
563 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
564 f.debug_struct("Adc12B").finish()
565 }
566}
567#[doc = "ADC12_B"]
568pub mod adc12_b;
569#[doc = "COMP_E"]
570pub type CompE = crate::Periph<comp_e::RegisterBlock, 0x08c0>;
571impl core::fmt::Debug for CompE {
572 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
573 f.debug_struct("CompE").finish()
574 }
575}
576#[doc = "COMP_E"]
577pub mod comp_e;
578#[doc = "CRC32"]
579pub type Crc32 = crate::Periph<crc32::RegisterBlock, 0x0980>;
580impl core::fmt::Debug for Crc32 {
581 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
582 f.debug_struct("Crc32").finish()
583 }
584}
585#[doc = "CRC32"]
586pub mod crc32;
587#[doc = "AES256"]
588pub type Aes256 = crate::Periph<aes256::RegisterBlock, 0x09c0>;
589impl core::fmt::Debug for Aes256 {
590 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
591 f.debug_struct("Aes256").finish()
592 }
593}
594#[doc = "AES256"]
595pub mod aes256;
596#[doc = "LEA"]
597pub type Lea = crate::Periph<lea::RegisterBlock, 0x0a80>;
598impl core::fmt::Debug for Lea {
599 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
600 f.debug_struct("Lea").finish()
601 }
602}
603#[doc = "LEA"]
604pub mod lea;
605#[unsafe(no_mangle)]
606static mut DEVICE_PERIPHERALS: bool = false;
607#[doc = r" All the peripherals."]
608#[allow(non_snake_case)]
609pub struct Peripherals {
610 #[doc = "P1"]
611 pub p1: P1,
612 #[doc = "P2"]
613 pub p2: P2,
614 #[doc = "P3"]
615 pub p3: P3,
616 #[doc = "P4"]
617 pub p4: P4,
618 #[doc = "P5"]
619 pub p5: P5,
620 #[doc = "P6"]
621 pub p6: P6,
622 #[doc = "P7"]
623 pub p7: P7,
624 #[doc = "P8"]
625 pub p8: P8,
626 #[doc = "P9"]
627 pub p9: P9,
628 #[doc = "RTC_C"]
629 pub rtc_c: RtcC,
630 #[doc = "SFR"]
631 pub sfr: Sfr,
632 #[doc = "PMM"]
633 pub pmm: Pmm,
634 #[doc = "FRCTL_A"]
635 pub frctl_a: FrctlA,
636 #[doc = "CRC"]
637 pub crc: Crc,
638 #[doc = "RAMCTL"]
639 pub ramctl: Ramctl,
640 #[doc = "WDT_A"]
641 pub wdt_a: WdtA,
642 #[doc = "CS"]
643 pub cs: Cs,
644 #[doc = "SYS"]
645 pub sys: Sys,
646 #[doc = "REF_A"]
647 pub ref_a: RefA,
648 #[doc = "PJ"]
649 pub pj: Pj,
650 #[doc = "TA0"]
651 pub ta0: Ta0,
652 #[doc = "TA1"]
653 pub ta1: Ta1,
654 #[doc = "TB0"]
655 pub tb0: Tb0,
656 #[doc = "TA2"]
657 pub ta2: Ta2,
658 #[doc = "CAPTIO0"]
659 pub captio0: Captio0,
660 #[doc = "TA3"]
661 pub ta3: Ta3,
662 #[doc = "CAPTIO1"]
663 pub captio1: Captio1,
664 #[doc = "MPY32"]
665 pub mpy32: Mpy32,
666 #[doc = "DMA"]
667 pub dma: Dma,
668 #[doc = "MPU"]
669 pub mpu: Mpu,
670 #[doc = "E_USCI_A0"]
671 pub e_usci_a0: EUsciA0,
672 #[doc = "E_USCI_A1"]
673 pub e_usci_a1: EUsciA1,
674 #[doc = "E_USCI_A2"]
675 pub e_usci_a2: EUsciA2,
676 #[doc = "E_USCI_A3"]
677 pub e_usci_a3: EUsciA3,
678 #[doc = "E_USCI_B0"]
679 pub e_usci_b0: EUsciB0,
680 #[doc = "E_USCI_B1"]
681 pub e_usci_b1: EUsciB1,
682 #[doc = "E_USCI_B2"]
683 pub e_usci_b2: EUsciB2,
684 #[doc = "E_USCI_B3"]
685 pub e_usci_b3: EUsciB3,
686 #[doc = "TA4"]
687 pub ta4: Ta4,
688 #[doc = "ADC12_B"]
689 pub adc12_b: Adc12B,
690 #[doc = "COMP_E"]
691 pub comp_e: CompE,
692 #[doc = "CRC32"]
693 pub crc32: Crc32,
694 #[doc = "AES256"]
695 pub aes256: Aes256,
696 #[doc = "LEA"]
697 pub lea: Lea,
698}
699impl Peripherals {
700 #[doc = r" Returns all the peripherals *once*."]
701 #[cfg(feature = "critical-section")]
702 #[inline]
703 pub fn take() -> Option<Self> {
704 critical_section::with(|_| {
705 if unsafe { DEVICE_PERIPHERALS } {
706 return None;
707 }
708 Some(unsafe { Peripherals::steal() })
709 })
710 }
711 #[doc = r" Unchecked version of `Peripherals::take`."]
712 #[doc = r""]
713 #[doc = r" # Safety"]
714 #[doc = r""]
715 #[doc = r" Each of the returned peripherals must be used at most once."]
716 #[inline]
717 pub unsafe fn steal() -> Self {
718 DEVICE_PERIPHERALS = true;
719 Peripherals {
720 p1: P1::steal(),
721 p2: P2::steal(),
722 p3: P3::steal(),
723 p4: P4::steal(),
724 p5: P5::steal(),
725 p6: P6::steal(),
726 p7: P7::steal(),
727 p8: P8::steal(),
728 p9: P9::steal(),
729 rtc_c: RtcC::steal(),
730 sfr: Sfr::steal(),
731 pmm: Pmm::steal(),
732 frctl_a: FrctlA::steal(),
733 crc: Crc::steal(),
734 ramctl: Ramctl::steal(),
735 wdt_a: WdtA::steal(),
736 cs: Cs::steal(),
737 sys: Sys::steal(),
738 ref_a: RefA::steal(),
739 pj: Pj::steal(),
740 ta0: Ta0::steal(),
741 ta1: Ta1::steal(),
742 tb0: Tb0::steal(),
743 ta2: Ta2::steal(),
744 captio0: Captio0::steal(),
745 ta3: Ta3::steal(),
746 captio1: Captio1::steal(),
747 mpy32: Mpy32::steal(),
748 dma: Dma::steal(),
749 mpu: Mpu::steal(),
750 e_usci_a0: EUsciA0::steal(),
751 e_usci_a1: EUsciA1::steal(),
752 e_usci_a2: EUsciA2::steal(),
753 e_usci_a3: EUsciA3::steal(),
754 e_usci_b0: EUsciB0::steal(),
755 e_usci_b1: EUsciB1::steal(),
756 e_usci_b2: EUsciB2::steal(),
757 e_usci_b3: EUsciB3::steal(),
758 ta4: Ta4::steal(),
759 adc12_b: Adc12B::steal(),
760 comp_e: CompE::steal(),
761 crc32: Crc32::steal(),
762 aes256: Aes256::steal(),
763 lea: Lea::steal(),
764 }
765 }
766}