[−][src]Struct msp430fr4133::generic::W
Implementations
impl<U, REG> W<U, REG>[src]
impl W<u8, Reg<u8, _P1IN>>[src]
pub fn p1in0(&mut self) -> P1IN0_W[src]
Bit 0 - P1IN0
pub fn p1in1(&mut self) -> P1IN1_W[src]
Bit 1 - P1IN1
pub fn p1in2(&mut self) -> P1IN2_W[src]
Bit 2 - P1IN2
pub fn p1in3(&mut self) -> P1IN3_W[src]
Bit 3 - P1IN3
pub fn p1in4(&mut self) -> P1IN4_W[src]
Bit 4 - P1IN4
pub fn p1in5(&mut self) -> P1IN5_W[src]
Bit 5 - P1IN5
pub fn p1in6(&mut self) -> P1IN6_W[src]
Bit 6 - P1IN6
pub fn p1in7(&mut self) -> P1IN7_W[src]
Bit 7 - P1IN7
impl W<u8, Reg<u8, _P2IN>>[src]
pub fn p2in0(&mut self) -> P2IN0_W[src]
Bit 0 - P2IN0
pub fn p2in1(&mut self) -> P2IN1_W[src]
Bit 1 - P2IN1
pub fn p2in2(&mut self) -> P2IN2_W[src]
Bit 2 - P2IN2
pub fn p2in3(&mut self) -> P2IN3_W[src]
Bit 3 - P2IN3
pub fn p2in4(&mut self) -> P2IN4_W[src]
Bit 4 - P2IN4
pub fn p2in5(&mut self) -> P2IN5_W[src]
Bit 5 - P2IN5
pub fn p2in6(&mut self) -> P2IN6_W[src]
Bit 6 - P2IN6
pub fn p2in7(&mut self) -> P2IN7_W[src]
Bit 7 - P2IN7
impl W<u8, Reg<u8, _P1OUT>>[src]
pub fn p1out0(&mut self) -> P1OUT0_W[src]
Bit 0 - P1OUT0
pub fn p1out1(&mut self) -> P1OUT1_W[src]
Bit 1 - P1OUT1
pub fn p1out2(&mut self) -> P1OUT2_W[src]
Bit 2 - P1OUT2
pub fn p1out3(&mut self) -> P1OUT3_W[src]
Bit 3 - P1OUT3
pub fn p1out4(&mut self) -> P1OUT4_W[src]
Bit 4 - P1OUT4
pub fn p1out5(&mut self) -> P1OUT5_W[src]
Bit 5 - P1OUT5
pub fn p1out6(&mut self) -> P1OUT6_W[src]
Bit 6 - P1OUT6
pub fn p1out7(&mut self) -> P1OUT7_W[src]
Bit 7 - P1OUT7
impl W<u8, Reg<u8, _P2OUT>>[src]
pub fn p2out0(&mut self) -> P2OUT0_W[src]
Bit 0 - P2OUT0
pub fn p2out1(&mut self) -> P2OUT1_W[src]
Bit 1 - P2OUT1
pub fn p2out2(&mut self) -> P2OUT2_W[src]
Bit 2 - P2OUT2
pub fn p2out3(&mut self) -> P2OUT3_W[src]
Bit 3 - P2OUT3
pub fn p2out4(&mut self) -> P2OUT4_W[src]
Bit 4 - P2OUT4
pub fn p2out5(&mut self) -> P2OUT5_W[src]
Bit 5 - P2OUT5
pub fn p2out6(&mut self) -> P2OUT6_W[src]
Bit 6 - P2OUT6
pub fn p2out7(&mut self) -> P2OUT7_W[src]
Bit 7 - P2OUT7
impl W<u8, Reg<u8, _P1DIR>>[src]
pub fn p1dir0(&mut self) -> P1DIR0_W[src]
Bit 0 - P1DIR0
pub fn p1dir1(&mut self) -> P1DIR1_W[src]
Bit 1 - P1DIR1
pub fn p1dir2(&mut self) -> P1DIR2_W[src]
Bit 2 - P1DIR2
pub fn p1dir3(&mut self) -> P1DIR3_W[src]
Bit 3 - P1DIR3
pub fn p1dir4(&mut self) -> P1DIR4_W[src]
Bit 4 - P1DIR4
pub fn p1dir5(&mut self) -> P1DIR5_W[src]
Bit 5 - P1DIR5
pub fn p1dir6(&mut self) -> P1DIR6_W[src]
Bit 6 - P1DIR6
pub fn p1dir7(&mut self) -> P1DIR7_W[src]
Bit 7 - P1DIR7
impl W<u8, Reg<u8, _P2DIR>>[src]
pub fn p2dir0(&mut self) -> P2DIR0_W[src]
Bit 0 - P2DIR0
pub fn p2dir1(&mut self) -> P2DIR1_W[src]
Bit 1 - P2DIR1
pub fn p2dir2(&mut self) -> P2DIR2_W[src]
Bit 2 - P2DIR2
pub fn p2dir3(&mut self) -> P2DIR3_W[src]
Bit 3 - P2DIR3
pub fn p2dir4(&mut self) -> P2DIR4_W[src]
Bit 4 - P2DIR4
pub fn p2dir5(&mut self) -> P2DIR5_W[src]
Bit 5 - P2DIR5
pub fn p2dir6(&mut self) -> P2DIR6_W[src]
Bit 6 - P2DIR6
pub fn p2dir7(&mut self) -> P2DIR7_W[src]
Bit 7 - P2DIR7
impl W<u8, Reg<u8, _P1REN>>[src]
pub fn p1ren0(&mut self) -> P1REN0_W[src]
Bit 0 - P1REN0
pub fn p1ren1(&mut self) -> P1REN1_W[src]
Bit 1 - P1REN1
pub fn p1ren2(&mut self) -> P1REN2_W[src]
Bit 2 - P1REN2
pub fn p1ren3(&mut self) -> P1REN3_W[src]
Bit 3 - P1REN3
pub fn p1ren4(&mut self) -> P1REN4_W[src]
Bit 4 - P1REN4
pub fn p1ren5(&mut self) -> P1REN5_W[src]
Bit 5 - P1REN5
pub fn p1ren6(&mut self) -> P1REN6_W[src]
Bit 6 - P1REN6
pub fn p1ren7(&mut self) -> P1REN7_W[src]
Bit 7 - P1REN7
impl W<u8, Reg<u8, _P2REN>>[src]
pub fn p2ren0(&mut self) -> P2REN0_W[src]
Bit 0 - P2REN0
pub fn p2ren1(&mut self) -> P2REN1_W[src]
Bit 1 - P2REN1
pub fn p2ren2(&mut self) -> P2REN2_W[src]
Bit 2 - P2REN2
pub fn p2ren3(&mut self) -> P2REN3_W[src]
Bit 3 - P2REN3
pub fn p2ren4(&mut self) -> P2REN4_W[src]
Bit 4 - P2REN4
pub fn p2ren5(&mut self) -> P2REN5_W[src]
Bit 5 - P2REN5
pub fn p2ren6(&mut self) -> P2REN6_W[src]
Bit 6 - P2REN6
pub fn p2ren7(&mut self) -> P2REN7_W[src]
Bit 7 - P2REN7
impl W<u8, Reg<u8, _P1SEL0>>[src]
pub fn p1sel0_0(&mut self) -> P1SEL0_0_W[src]
Bit 0 - P1SEL0_0
pub fn p1sel0_1(&mut self) -> P1SEL0_1_W[src]
Bit 1 - P1SEL0_1
pub fn p1sel0_2(&mut self) -> P1SEL0_2_W[src]
Bit 2 - P1SEL0_2
pub fn p1sel0_3(&mut self) -> P1SEL0_3_W[src]
Bit 3 - P1SEL0_3
pub fn p1sel0_4(&mut self) -> P1SEL0_4_W[src]
Bit 4 - P1SEL0_4
pub fn p1sel0_5(&mut self) -> P1SEL0_5_W[src]
Bit 5 - P1SEL0_5
pub fn p1sel0_6(&mut self) -> P1SEL0_6_W[src]
Bit 6 - P1SEL0_6
pub fn p1sel0_7(&mut self) -> P1SEL0_7_W[src]
Bit 7 - P1SEL0_7
impl W<u8, Reg<u8, _P2SEL0>>[src]
pub fn p2sel0_0(&mut self) -> P2SEL0_0_W[src]
Bit 0 - P2SEL0_0
pub fn p2sel0_1(&mut self) -> P2SEL0_1_W[src]
Bit 1 - P2SEL0_1
pub fn p2sel0_2(&mut self) -> P2SEL0_2_W[src]
Bit 2 - P2SEL0_2
pub fn p2sel0_3(&mut self) -> P2SEL0_3_W[src]
Bit 3 - P2SEL0_3
pub fn p2sel0_4(&mut self) -> P2SEL0_4_W[src]
Bit 4 - P2SEL0_4
pub fn p2sel0_5(&mut self) -> P2SEL0_5_W[src]
Bit 5 - P2SEL0_5
pub fn p2sel0_6(&mut self) -> P2SEL0_6_W[src]
Bit 6 - P2SEL0_6
pub fn p2sel0_7(&mut self) -> P2SEL0_7_W[src]
Bit 7 - P2SEL0_7
impl W<u8, Reg<u8, _P1IES>>[src]
pub fn p1ies0(&mut self) -> P1IES0_W[src]
Bit 0 - P1IES0
pub fn p1ies1(&mut self) -> P1IES1_W[src]
Bit 1 - P1IES1
pub fn p1ies2(&mut self) -> P1IES2_W[src]
Bit 2 - P1IES2
pub fn p1ies3(&mut self) -> P1IES3_W[src]
Bit 3 - P1IES3
pub fn p1ies4(&mut self) -> P1IES4_W[src]
Bit 4 - P1IES4
pub fn p1ies5(&mut self) -> P1IES5_W[src]
Bit 5 - P1IES5
pub fn p1ies6(&mut self) -> P1IES6_W[src]
Bit 6 - P1IES6
pub fn p1ies7(&mut self) -> P1IES7_W[src]
Bit 7 - P1IES7
impl W<u8, Reg<u8, _P2IES>>[src]
pub fn p2ies0(&mut self) -> P2IES0_W[src]
Bit 0 - P2IES0
pub fn p2ies1(&mut self) -> P2IES1_W[src]
Bit 1 - P2IES1
pub fn p2ies2(&mut self) -> P2IES2_W[src]
Bit 2 - P2IES2
pub fn p2ies3(&mut self) -> P2IES3_W[src]
Bit 3 - P2IES3
pub fn p2ies4(&mut self) -> P2IES4_W[src]
Bit 4 - P2IES4
pub fn p2ies5(&mut self) -> P2IES5_W[src]
Bit 5 - P2IES5
pub fn p2ies6(&mut self) -> P2IES6_W[src]
Bit 6 - P2IES6
pub fn p2ies7(&mut self) -> P2IES7_W[src]
Bit 7 - P2IES7
impl W<u8, Reg<u8, _P1IE>>[src]
pub fn p1ie0(&mut self) -> P1IE0_W[src]
Bit 0 - P1IE0
pub fn p1ie1(&mut self) -> P1IE1_W[src]
Bit 1 - P1IE1
pub fn p1ie2(&mut self) -> P1IE2_W[src]
Bit 2 - P1IE2
pub fn p1ie3(&mut self) -> P1IE3_W[src]
Bit 3 - P1IE3
pub fn p1ie4(&mut self) -> P1IE4_W[src]
Bit 4 - P1IE4
pub fn p1ie5(&mut self) -> P1IE5_W[src]
Bit 5 - P1IE5
pub fn p1ie6(&mut self) -> P1IE6_W[src]
Bit 6 - P1IE6
pub fn p1ie7(&mut self) -> P1IE7_W[src]
Bit 7 - P1IE7
impl W<u8, Reg<u8, _P2IE>>[src]
pub fn p2ie0(&mut self) -> P2IE0_W[src]
Bit 0 - P2IE0
pub fn p2ie1(&mut self) -> P2IE1_W[src]
Bit 1 - P2IE1
pub fn p2ie2(&mut self) -> P2IE2_W[src]
Bit 2 - P2IE2
pub fn p2ie3(&mut self) -> P2IE3_W[src]
Bit 3 - P2IE3
pub fn p2ie4(&mut self) -> P2IE4_W[src]
Bit 4 - P2IE4
pub fn p2ie5(&mut self) -> P2IE5_W[src]
Bit 5 - P2IE5
pub fn p2ie6(&mut self) -> P2IE6_W[src]
Bit 6 - P2IE6
pub fn p2ie7(&mut self) -> P2IE7_W[src]
Bit 7 - P2IE7
impl W<u8, Reg<u8, _P1IFG>>[src]
pub fn p1ifg0(&mut self) -> P1IFG0_W[src]
Bit 0 - P1IFG0
pub fn p1ifg1(&mut self) -> P1IFG1_W[src]
Bit 1 - P1IFG1
pub fn p1ifg2(&mut self) -> P1IFG2_W[src]
Bit 2 - P1IFG2
pub fn p1ifg3(&mut self) -> P1IFG3_W[src]
Bit 3 - P1IFG3
pub fn p1ifg4(&mut self) -> P1IFG4_W[src]
Bit 4 - P1IFG4
pub fn p1ifg5(&mut self) -> P1IFG5_W[src]
Bit 5 - P1IFG5
pub fn p1ifg6(&mut self) -> P1IFG6_W[src]
Bit 6 - P1IFG6
pub fn p1ifg7(&mut self) -> P1IFG7_W[src]
Bit 7 - P1IFG7
impl W<u8, Reg<u8, _P2IFG>>[src]
pub fn p2ifg0(&mut self) -> P2IFG0_W[src]
Bit 0 - P2IFG0
pub fn p2ifg1(&mut self) -> P2IFG1_W[src]
Bit 1 - P2IFG1
pub fn p2ifg2(&mut self) -> P2IFG2_W[src]
Bit 2 - P2IFG2
pub fn p2ifg3(&mut self) -> P2IFG3_W[src]
Bit 3 - P2IFG3
pub fn p2ifg4(&mut self) -> P2IFG4_W[src]
Bit 4 - P2IFG4
pub fn p2ifg5(&mut self) -> P2IFG5_W[src]
Bit 5 - P2IFG5
pub fn p2ifg6(&mut self) -> P2IFG6_W[src]
Bit 6 - P2IFG6
pub fn p2ifg7(&mut self) -> P2IFG7_W[src]
Bit 7 - P2IFG7
impl W<u8, Reg<u8, _P3IN>>[src]
pub fn p3in0(&mut self) -> P3IN0_W[src]
Bit 0 - P3IN0
pub fn p3in1(&mut self) -> P3IN1_W[src]
Bit 1 - P3IN1
pub fn p3in2(&mut self) -> P3IN2_W[src]
Bit 2 - P3IN2
pub fn p3in3(&mut self) -> P3IN3_W[src]
Bit 3 - P3IN3
pub fn p3in4(&mut self) -> P3IN4_W[src]
Bit 4 - P3IN4
pub fn p3in5(&mut self) -> P3IN5_W[src]
Bit 5 - P3IN5
pub fn p3in6(&mut self) -> P3IN6_W[src]
Bit 6 - P3IN6
pub fn p3in7(&mut self) -> P3IN7_W[src]
Bit 7 - P3IN7
impl W<u8, Reg<u8, _P4IN>>[src]
pub fn p4in0(&mut self) -> P4IN0_W[src]
Bit 0 - P4IN0
pub fn p4in1(&mut self) -> P4IN1_W[src]
Bit 1 - P4IN1
pub fn p4in2(&mut self) -> P4IN2_W[src]
Bit 2 - P4IN2
pub fn p4in3(&mut self) -> P4IN3_W[src]
Bit 3 - P4IN3
pub fn p4in4(&mut self) -> P4IN4_W[src]
Bit 4 - P4IN4
pub fn p4in5(&mut self) -> P4IN5_W[src]
Bit 5 - P4IN5
pub fn p4in6(&mut self) -> P4IN6_W[src]
Bit 6 - P4IN6
pub fn p4in7(&mut self) -> P4IN7_W[src]
Bit 7 - P4IN7
impl W<u8, Reg<u8, _P3OUT>>[src]
pub fn p3out0(&mut self) -> P3OUT0_W[src]
Bit 0 - P3OUT0
pub fn p3out1(&mut self) -> P3OUT1_W[src]
Bit 1 - P3OUT1
pub fn p3out2(&mut self) -> P3OUT2_W[src]
Bit 2 - P3OUT2
pub fn p3out3(&mut self) -> P3OUT3_W[src]
Bit 3 - P3OUT3
pub fn p3out4(&mut self) -> P3OUT4_W[src]
Bit 4 - P3OUT4
pub fn p3out5(&mut self) -> P3OUT5_W[src]
Bit 5 - P3OUT5
pub fn p3out6(&mut self) -> P3OUT6_W[src]
Bit 6 - P3OUT6
pub fn p3out7(&mut self) -> P3OUT7_W[src]
Bit 7 - P3OUT7
impl W<u8, Reg<u8, _P4OUT>>[src]
pub fn p4out0(&mut self) -> P4OUT0_W[src]
Bit 0 - P4OUT0
pub fn p4out1(&mut self) -> P4OUT1_W[src]
Bit 1 - P4OUT1
pub fn p4out2(&mut self) -> P4OUT2_W[src]
Bit 2 - P4OUT2
pub fn p4out3(&mut self) -> P4OUT3_W[src]
Bit 3 - P4OUT3
pub fn p4out4(&mut self) -> P4OUT4_W[src]
Bit 4 - P4OUT4
pub fn p4out5(&mut self) -> P4OUT5_W[src]
Bit 5 - P4OUT5
pub fn p4out6(&mut self) -> P4OUT6_W[src]
Bit 6 - P4OUT6
pub fn p4out7(&mut self) -> P4OUT7_W[src]
Bit 7 - P4OUT7
impl W<u8, Reg<u8, _P3DIR>>[src]
pub fn p3dir0(&mut self) -> P3DIR0_W[src]
Bit 0 - P3DIR0
pub fn p3dir1(&mut self) -> P3DIR1_W[src]
Bit 1 - P3DIR1
pub fn p3dir2(&mut self) -> P3DIR2_W[src]
Bit 2 - P3DIR2
pub fn p3dir3(&mut self) -> P3DIR3_W[src]
Bit 3 - P3DIR3
pub fn p3dir4(&mut self) -> P3DIR4_W[src]
Bit 4 - P3DIR4
pub fn p3dir5(&mut self) -> P3DIR5_W[src]
Bit 5 - P3DIR5
pub fn p3dir6(&mut self) -> P3DIR6_W[src]
Bit 6 - P3DIR6
pub fn p3dir7(&mut self) -> P3DIR7_W[src]
Bit 7 - P3DIR7
impl W<u8, Reg<u8, _P4DIR>>[src]
pub fn p4dir0(&mut self) -> P4DIR0_W[src]
Bit 0 - P4DIR0
pub fn p4dir1(&mut self) -> P4DIR1_W[src]
Bit 1 - P4DIR1
pub fn p4dir2(&mut self) -> P4DIR2_W[src]
Bit 2 - P4DIR2
pub fn p4dir3(&mut self) -> P4DIR3_W[src]
Bit 3 - P4DIR3
pub fn p4dir4(&mut self) -> P4DIR4_W[src]
Bit 4 - P4DIR4
pub fn p4dir5(&mut self) -> P4DIR5_W[src]
Bit 5 - P4DIR5
pub fn p4dir6(&mut self) -> P4DIR6_W[src]
Bit 6 - P4DIR6
pub fn p4dir7(&mut self) -> P4DIR7_W[src]
Bit 7 - P4DIR7
impl W<u8, Reg<u8, _P3REN>>[src]
pub fn p3ren0(&mut self) -> P3REN0_W[src]
Bit 0 - P3REN0
pub fn p3ren1(&mut self) -> P3REN1_W[src]
Bit 1 - P3REN1
pub fn p3ren2(&mut self) -> P3REN2_W[src]
Bit 2 - P3REN2
pub fn p3ren3(&mut self) -> P3REN3_W[src]
Bit 3 - P3REN3
pub fn p3ren4(&mut self) -> P3REN4_W[src]
Bit 4 - P3REN4
pub fn p3ren5(&mut self) -> P3REN5_W[src]
Bit 5 - P3REN5
pub fn p3ren6(&mut self) -> P3REN6_W[src]
Bit 6 - P3REN6
pub fn p3ren7(&mut self) -> P3REN7_W[src]
Bit 7 - P3REN7
impl W<u8, Reg<u8, _P4REN>>[src]
pub fn p4ren0(&mut self) -> P4REN0_W[src]
Bit 0 - P4REN0
pub fn p4ren1(&mut self) -> P4REN1_W[src]
Bit 1 - P4REN1
pub fn p4ren2(&mut self) -> P4REN2_W[src]
Bit 2 - P4REN2
pub fn p4ren3(&mut self) -> P4REN3_W[src]
Bit 3 - P4REN3
pub fn p4ren4(&mut self) -> P4REN4_W[src]
Bit 4 - P4REN4
pub fn p4ren5(&mut self) -> P4REN5_W[src]
Bit 5 - P4REN5
pub fn p4ren6(&mut self) -> P4REN6_W[src]
Bit 6 - P4REN6
pub fn p4ren7(&mut self) -> P4REN7_W[src]
Bit 7 - P4REN7
impl W<u8, Reg<u8, _P3SEL0>>[src]
pub fn p3sel0_0(&mut self) -> P3SEL0_0_W[src]
Bit 0 - P3SEL0_0
pub fn p3sel0_1(&mut self) -> P3SEL0_1_W[src]
Bit 1 - P3SEL0_1
pub fn p3sel0_2(&mut self) -> P3SEL0_2_W[src]
Bit 2 - P3SEL0_2
pub fn p3sel0_3(&mut self) -> P3SEL0_3_W[src]
Bit 3 - P3SEL0_3
pub fn p3sel0_4(&mut self) -> P3SEL0_4_W[src]
Bit 4 - P3SEL0_4
pub fn p3sel0_5(&mut self) -> P3SEL0_5_W[src]
Bit 5 - P3SEL0_5
pub fn p3sel0_6(&mut self) -> P3SEL0_6_W[src]
Bit 6 - P3SEL0_6
pub fn p3sel0_7(&mut self) -> P3SEL0_7_W[src]
Bit 7 - P3SEL0_7
impl W<u8, Reg<u8, _P4SEL0>>[src]
pub fn p4sel0_0(&mut self) -> P4SEL0_0_W[src]
Bit 0 - P4SEL0_0
pub fn p4sel0_1(&mut self) -> P4SEL0_1_W[src]
Bit 1 - P4SEL0_1
pub fn p4sel0_2(&mut self) -> P4SEL0_2_W[src]
Bit 2 - P4SEL0_2
pub fn p4sel0_3(&mut self) -> P4SEL0_3_W[src]
Bit 3 - P4SEL0_3
pub fn p4sel0_4(&mut self) -> P4SEL0_4_W[src]
Bit 4 - P4SEL0_4
pub fn p4sel0_5(&mut self) -> P4SEL0_5_W[src]
Bit 5 - P4SEL0_5
pub fn p4sel0_6(&mut self) -> P4SEL0_6_W[src]
Bit 6 - P4SEL0_6
pub fn p4sel0_7(&mut self) -> P4SEL0_7_W[src]
Bit 7 - P4SEL0_7
impl W<u8, Reg<u8, _P5IN>>[src]
pub fn p5in0(&mut self) -> P5IN0_W[src]
Bit 0 - P5IN0
pub fn p5in1(&mut self) -> P5IN1_W[src]
Bit 1 - P5IN1
pub fn p5in2(&mut self) -> P5IN2_W[src]
Bit 2 - P5IN2
pub fn p5in3(&mut self) -> P5IN3_W[src]
Bit 3 - P5IN3
pub fn p5in4(&mut self) -> P5IN4_W[src]
Bit 4 - P5IN4
pub fn p5in5(&mut self) -> P5IN5_W[src]
Bit 5 - P5IN5
pub fn p5in6(&mut self) -> P5IN6_W[src]
Bit 6 - P5IN6
pub fn p5in7(&mut self) -> P5IN7_W[src]
Bit 7 - P5IN7
impl W<u8, Reg<u8, _P6IN>>[src]
pub fn p6in0(&mut self) -> P6IN0_W[src]
Bit 0 - P6IN0
pub fn p6in1(&mut self) -> P6IN1_W[src]
Bit 1 - P6IN1
pub fn p6in2(&mut self) -> P6IN2_W[src]
Bit 2 - P6IN2
pub fn p6in3(&mut self) -> P6IN3_W[src]
Bit 3 - P6IN3
pub fn p6in4(&mut self) -> P6IN4_W[src]
Bit 4 - P6IN4
pub fn p6in5(&mut self) -> P6IN5_W[src]
Bit 5 - P6IN5
pub fn p6in6(&mut self) -> P6IN6_W[src]
Bit 6 - P6IN6
pub fn p6in7(&mut self) -> P6IN7_W[src]
Bit 7 - P6IN7
impl W<u8, Reg<u8, _P5OUT>>[src]
pub fn p5out0(&mut self) -> P5OUT0_W[src]
Bit 0 - P5OUT0
pub fn p5out1(&mut self) -> P5OUT1_W[src]
Bit 1 - P5OUT1
pub fn p5out2(&mut self) -> P5OUT2_W[src]
Bit 2 - P5OUT2
pub fn p5out3(&mut self) -> P5OUT3_W[src]
Bit 3 - P5OUT3
pub fn p5out4(&mut self) -> P5OUT4_W[src]
Bit 4 - P5OUT4
pub fn p5out5(&mut self) -> P5OUT5_W[src]
Bit 5 - P5OUT5
pub fn p5out6(&mut self) -> P5OUT6_W[src]
Bit 6 - P5OUT6
pub fn p5out7(&mut self) -> P5OUT7_W[src]
Bit 7 - P5OUT7
impl W<u8, Reg<u8, _P6OUT>>[src]
pub fn p6out0(&mut self) -> P6OUT0_W[src]
Bit 0 - P6OUT0
pub fn p6out1(&mut self) -> P6OUT1_W[src]
Bit 1 - P6OUT1
pub fn p6out2(&mut self) -> P6OUT2_W[src]
Bit 2 - P6OUT2
pub fn p6out3(&mut self) -> P6OUT3_W[src]
Bit 3 - P6OUT3
pub fn p6out4(&mut self) -> P6OUT4_W[src]
Bit 4 - P6OUT4
pub fn p6out5(&mut self) -> P6OUT5_W[src]
Bit 5 - P6OUT5
pub fn p6out6(&mut self) -> P6OUT6_W[src]
Bit 6 - P6OUT6
pub fn p6out7(&mut self) -> P6OUT7_W[src]
Bit 7 - P6OUT7
impl W<u8, Reg<u8, _P5DIR>>[src]
pub fn p5dir0(&mut self) -> P5DIR0_W[src]
Bit 0 - P5DIR0
pub fn p5dir1(&mut self) -> P5DIR1_W[src]
Bit 1 - P5DIR1
pub fn p5dir2(&mut self) -> P5DIR2_W[src]
Bit 2 - P5DIR2
pub fn p5dir3(&mut self) -> P5DIR3_W[src]
Bit 3 - P5DIR3
pub fn p5dir4(&mut self) -> P5DIR4_W[src]
Bit 4 - P5DIR4
pub fn p5dir5(&mut self) -> P5DIR5_W[src]
Bit 5 - P5DIR5
pub fn p5dir6(&mut self) -> P5DIR6_W[src]
Bit 6 - P5DIR6
pub fn p5dir7(&mut self) -> P5DIR7_W[src]
Bit 7 - P5DIR7
impl W<u8, Reg<u8, _P6DIR>>[src]
pub fn p6dir0(&mut self) -> P6DIR0_W[src]
Bit 0 - P6DIR0
pub fn p6dir1(&mut self) -> P6DIR1_W[src]
Bit 1 - P6DIR1
pub fn p6dir2(&mut self) -> P6DIR2_W[src]
Bit 2 - P6DIR2
pub fn p6dir3(&mut self) -> P6DIR3_W[src]
Bit 3 - P6DIR3
pub fn p6dir4(&mut self) -> P6DIR4_W[src]
Bit 4 - P6DIR4
pub fn p6dir5(&mut self) -> P6DIR5_W[src]
Bit 5 - P6DIR5
pub fn p6dir6(&mut self) -> P6DIR6_W[src]
Bit 6 - P6DIR6
pub fn p6dir7(&mut self) -> P6DIR7_W[src]
Bit 7 - P6DIR7
impl W<u8, Reg<u8, _P5REN>>[src]
pub fn p5ren0(&mut self) -> P5REN0_W[src]
Bit 0 - P5REN0
pub fn p5ren1(&mut self) -> P5REN1_W[src]
Bit 1 - P5REN1
pub fn p5ren2(&mut self) -> P5REN2_W[src]
Bit 2 - P5REN2
pub fn p5ren3(&mut self) -> P5REN3_W[src]
Bit 3 - P5REN3
pub fn p5ren4(&mut self) -> P5REN4_W[src]
Bit 4 - P5REN4
pub fn p5ren5(&mut self) -> P5REN5_W[src]
Bit 5 - P5REN5
pub fn p5ren6(&mut self) -> P5REN6_W[src]
Bit 6 - P5REN6
pub fn p5ren7(&mut self) -> P5REN7_W[src]
Bit 7 - P5REN7
impl W<u8, Reg<u8, _P6REN>>[src]
pub fn p6ren0(&mut self) -> P6REN0_W[src]
Bit 0 - P6REN0
pub fn p6ren1(&mut self) -> P6REN1_W[src]
Bit 1 - P6REN1
pub fn p6ren2(&mut self) -> P6REN2_W[src]
Bit 2 - P6REN2
pub fn p6ren3(&mut self) -> P6REN3_W[src]
Bit 3 - P6REN3
pub fn p6ren4(&mut self) -> P6REN4_W[src]
Bit 4 - P6REN4
pub fn p6ren5(&mut self) -> P6REN5_W[src]
Bit 5 - P6REN5
pub fn p6ren6(&mut self) -> P6REN6_W[src]
Bit 6 - P6REN6
pub fn p6ren7(&mut self) -> P6REN7_W[src]
Bit 7 - P6REN7
impl W<u8, Reg<u8, _P5SEL0>>[src]
pub fn p5sel0_0(&mut self) -> P5SEL0_0_W[src]
Bit 0 - P5SEL0_0
pub fn p5sel0_1(&mut self) -> P5SEL0_1_W[src]
Bit 1 - P5SEL0_1
pub fn p5sel0_2(&mut self) -> P5SEL0_2_W[src]
Bit 2 - P5SEL0_2
pub fn p5sel0_3(&mut self) -> P5SEL0_3_W[src]
Bit 3 - P5SEL0_3
pub fn p5sel0_4(&mut self) -> P5SEL0_4_W[src]
Bit 4 - P5SEL0_4
pub fn p5sel0_5(&mut self) -> P5SEL0_5_W[src]
Bit 5 - P5SEL0_5
pub fn p5sel0_6(&mut self) -> P5SEL0_6_W[src]
Bit 6 - P5SEL0_6
pub fn p5sel0_7(&mut self) -> P5SEL0_7_W[src]
Bit 7 - P5SEL0_7
impl W<u8, Reg<u8, _P6SEL0>>[src]
pub fn p6sel0_0(&mut self) -> P6SEL0_0_W[src]
Bit 0 - P6SEL0_0
pub fn p6sel0_1(&mut self) -> P6SEL0_1_W[src]
Bit 1 - P6SEL0_1
pub fn p6sel0_2(&mut self) -> P6SEL0_2_W[src]
Bit 2 - P6SEL0_2
pub fn p6sel0_3(&mut self) -> P6SEL0_3_W[src]
Bit 3 - P6SEL0_3
pub fn p6sel0_4(&mut self) -> P6SEL0_4_W[src]
Bit 4 - P6SEL0_4
pub fn p6sel0_5(&mut self) -> P6SEL0_5_W[src]
Bit 5 - P6SEL0_5
pub fn p6sel0_6(&mut self) -> P6SEL0_6_W[src]
Bit 6 - P6SEL0_6
pub fn p6sel0_7(&mut self) -> P6SEL0_7_W[src]
Bit 7 - P6SEL0_7
impl W<u8, Reg<u8, _P7IN>>[src]
pub fn p7in0(&mut self) -> P7IN0_W[src]
Bit 0 - P7IN0
pub fn p7in1(&mut self) -> P7IN1_W[src]
Bit 1 - P7IN1
pub fn p7in2(&mut self) -> P7IN2_W[src]
Bit 2 - P7IN2
pub fn p7in3(&mut self) -> P7IN3_W[src]
Bit 3 - P7IN3
pub fn p7in4(&mut self) -> P7IN4_W[src]
Bit 4 - P7IN4
pub fn p7in5(&mut self) -> P7IN5_W[src]
Bit 5 - P7IN5
pub fn p7in6(&mut self) -> P7IN6_W[src]
Bit 6 - P7IN6
pub fn p7in7(&mut self) -> P7IN7_W[src]
Bit 7 - P7IN7
impl W<u8, Reg<u8, _P8IN>>[src]
pub fn p8in0(&mut self) -> P8IN0_W[src]
Bit 0 - P8IN0
pub fn p8in1(&mut self) -> P8IN1_W[src]
Bit 1 - P8IN1
pub fn p8in2(&mut self) -> P8IN2_W[src]
Bit 2 - P8IN2
pub fn p8in3(&mut self) -> P8IN3_W[src]
Bit 3 - P8IN3
pub fn p8in4(&mut self) -> P8IN4_W[src]
Bit 4 - P8IN4
pub fn p8in5(&mut self) -> P8IN5_W[src]
Bit 5 - P8IN5
pub fn p8in6(&mut self) -> P8IN6_W[src]
Bit 6 - P8IN6
pub fn p8in7(&mut self) -> P8IN7_W[src]
Bit 7 - P8IN7
impl W<u8, Reg<u8, _P7OUT>>[src]
pub fn p7out0(&mut self) -> P7OUT0_W[src]
Bit 0 - P7OUT0
pub fn p7out1(&mut self) -> P7OUT1_W[src]
Bit 1 - P7OUT1
pub fn p7out2(&mut self) -> P7OUT2_W[src]
Bit 2 - P7OUT2
pub fn p7out3(&mut self) -> P7OUT3_W[src]
Bit 3 - P7OUT3
pub fn p7out4(&mut self) -> P7OUT4_W[src]
Bit 4 - P7OUT4
pub fn p7out5(&mut self) -> P7OUT5_W[src]
Bit 5 - P7OUT5
pub fn p7out6(&mut self) -> P7OUT6_W[src]
Bit 6 - P7OUT6
pub fn p7out7(&mut self) -> P7OUT7_W[src]
Bit 7 - P7OUT7
impl W<u8, Reg<u8, _P8OUT>>[src]
pub fn p8out0(&mut self) -> P8OUT0_W[src]
Bit 0 - P8OUT0
pub fn p8out1(&mut self) -> P8OUT1_W[src]
Bit 1 - P8OUT1
pub fn p8out2(&mut self) -> P8OUT2_W[src]
Bit 2 - P8OUT2
pub fn p8out3(&mut self) -> P8OUT3_W[src]
Bit 3 - P8OUT3
pub fn p8out4(&mut self) -> P8OUT4_W[src]
Bit 4 - P8OUT4
pub fn p8out5(&mut self) -> P8OUT5_W[src]
Bit 5 - P8OUT5
pub fn p8out6(&mut self) -> P8OUT6_W[src]
Bit 6 - P8OUT6
pub fn p8out7(&mut self) -> P8OUT7_W[src]
Bit 7 - P8OUT7
impl W<u8, Reg<u8, _P7DIR>>[src]
pub fn p7dir0(&mut self) -> P7DIR0_W[src]
Bit 0 - P7DIR0
pub fn p7dir1(&mut self) -> P7DIR1_W[src]
Bit 1 - P7DIR1
pub fn p7dir2(&mut self) -> P7DIR2_W[src]
Bit 2 - P7DIR2
pub fn p7dir3(&mut self) -> P7DIR3_W[src]
Bit 3 - P7DIR3
pub fn p7dir4(&mut self) -> P7DIR4_W[src]
Bit 4 - P7DIR4
pub fn p7dir5(&mut self) -> P7DIR5_W[src]
Bit 5 - P7DIR5
pub fn p7dir6(&mut self) -> P7DIR6_W[src]
Bit 6 - P7DIR6
pub fn p7dir7(&mut self) -> P7DIR7_W[src]
Bit 7 - P7DIR7
impl W<u8, Reg<u8, _P8DIR>>[src]
pub fn p8dir0(&mut self) -> P8DIR0_W[src]
Bit 0 - P8DIR0
pub fn p8dir1(&mut self) -> P8DIR1_W[src]
Bit 1 - P8DIR1
pub fn p8dir2(&mut self) -> P8DIR2_W[src]
Bit 2 - P8DIR2
pub fn p8dir3(&mut self) -> P8DIR3_W[src]
Bit 3 - P8DIR3
pub fn p8dir4(&mut self) -> P8DIR4_W[src]
Bit 4 - P8DIR4
pub fn p8dir5(&mut self) -> P8DIR5_W[src]
Bit 5 - P8DIR5
pub fn p8dir6(&mut self) -> P8DIR6_W[src]
Bit 6 - P8DIR6
pub fn p8dir7(&mut self) -> P8DIR7_W[src]
Bit 7 - P8DIR7
impl W<u8, Reg<u8, _P7REN>>[src]
pub fn p7ren0(&mut self) -> P7REN0_W[src]
Bit 0 - P7REN0
pub fn p7ren1(&mut self) -> P7REN1_W[src]
Bit 1 - P7REN1
pub fn p7ren2(&mut self) -> P7REN2_W[src]
Bit 2 - P7REN2
pub fn p7ren3(&mut self) -> P7REN3_W[src]
Bit 3 - P7REN3
pub fn p7ren4(&mut self) -> P7REN4_W[src]
Bit 4 - P7REN4
pub fn p7ren5(&mut self) -> P7REN5_W[src]
Bit 5 - P7REN5
pub fn p7ren6(&mut self) -> P7REN6_W[src]
Bit 6 - P7REN6
pub fn p7ren7(&mut self) -> P7REN7_W[src]
Bit 7 - P7REN7
impl W<u8, Reg<u8, _P8REN>>[src]
pub fn p8ren0(&mut self) -> P8REN0_W[src]
Bit 0 - P8REN0
pub fn p8ren1(&mut self) -> P8REN1_W[src]
Bit 1 - P8REN1
pub fn p8ren2(&mut self) -> P8REN2_W[src]
Bit 2 - P8REN2
pub fn p8ren3(&mut self) -> P8REN3_W[src]
Bit 3 - P8REN3
pub fn p8ren4(&mut self) -> P8REN4_W[src]
Bit 4 - P8REN4
pub fn p8ren5(&mut self) -> P8REN5_W[src]
Bit 5 - P8REN5
pub fn p8ren6(&mut self) -> P8REN6_W[src]
Bit 6 - P8REN6
pub fn p8ren7(&mut self) -> P8REN7_W[src]
Bit 7 - P8REN7
impl W<u8, Reg<u8, _P7SEL0>>[src]
pub fn p7sel0_0(&mut self) -> P7SEL0_0_W[src]
Bit 0 - P7SEL0_0
pub fn p7sel0_1(&mut self) -> P7SEL0_1_W[src]
Bit 1 - P7SEL0_1
pub fn p7sel0_2(&mut self) -> P7SEL0_2_W[src]
Bit 2 - P7SEL0_2
pub fn p7sel0_3(&mut self) -> P7SEL0_3_W[src]
Bit 3 - P7SEL0_3
pub fn p7sel0_4(&mut self) -> P7SEL0_4_W[src]
Bit 4 - P7SEL0_4
pub fn p7sel0_5(&mut self) -> P7SEL0_5_W[src]
Bit 5 - P7SEL0_5
pub fn p7sel0_6(&mut self) -> P7SEL0_6_W[src]
Bit 6 - P7SEL0_6
pub fn p7sel0_7(&mut self) -> P7SEL0_7_W[src]
Bit 7 - P7SEL0_7
impl W<u8, Reg<u8, _P8SEL0>>[src]
pub fn p8sel0_0(&mut self) -> P8SEL0_0_W[src]
Bit 0 - P8SEL0_0
pub fn p8sel0_1(&mut self) -> P8SEL0_1_W[src]
Bit 1 - P8SEL0_1
pub fn p8sel0_2(&mut self) -> P8SEL0_2_W[src]
Bit 2 - P8SEL0_2
pub fn p8sel0_3(&mut self) -> P8SEL0_3_W[src]
Bit 3 - P8SEL0_3
pub fn p8sel0_4(&mut self) -> P8SEL0_4_W[src]
Bit 4 - P8SEL0_4
pub fn p8sel0_5(&mut self) -> P8SEL0_5_W[src]
Bit 5 - P8SEL0_5
pub fn p8sel0_6(&mut self) -> P8SEL0_6_W[src]
Bit 6 - P8SEL0_6
pub fn p8sel0_7(&mut self) -> P8SEL0_7_W[src]
Bit 7 - P8SEL0_7
impl W<u8, Reg<u8, _UCA0STATW>>[src]
pub fn ucbusy(&mut self) -> UCBUSY_W[src]
Bit 0 - USCI Busy Flag
pub fn ucaddr(&mut self) -> UCADDR_W[src]
Bit 1 - USCI Address received Flag
pub fn ucrxerr(&mut self) -> UCRXERR_W[src]
Bit 2 - USCI RX Error Flag
pub fn ucbrk(&mut self) -> UCBRK_W[src]
Bit 3 - USCI Break received
pub fn ucpe(&mut self) -> UCPE_W[src]
Bit 4 - USCI Parity Error Flag
pub fn ucoe(&mut self) -> UCOE_W[src]
Bit 5 - USCI Overrun Error Flag
pub fn ucfe(&mut self) -> UCFE_W[src]
Bit 6 - USCI Frame Error Flag
pub fn uclisten(&mut self) -> UCLISTEN_W[src]
Bit 7 - USCI Listen mode
impl W<u8, Reg<u8, _UCA0ABCTL>>[src]
pub fn ucabden(&mut self) -> UCABDEN_W[src]
Bit 0 - Auto Baud Rate detect enable
pub fn ucbtoe(&mut self) -> UCBTOE_W[src]
Bit 2 - Break Timeout error
pub fn ucstoe(&mut self) -> UCSTOE_W[src]
Bit 3 - Sync-Field Timeout error
pub fn ucdelim0(&mut self) -> UCDELIM0_W[src]
Bit 4 - Break Sync Delimiter 0
pub fn ucdelim1(&mut self) -> UCDELIM1_W[src]
Bit 5 - Break Sync Delimiter 1
impl W<u16, Reg<u16, _UCA0CTLW1>>[src]
impl W<u16, Reg<u16, _UCA0MCTLW>>[src]
pub fn ucos16(&mut self) -> UCOS16_W[src]
Bit 0 - USCI 16-times Oversampling enable
pub fn ucbrf(&mut self) -> UCBRF_W[src]
Bits 4:7 - USCI First Stage Modulation Select 3
pub fn ucbrs0(&mut self) -> UCBRS0_W[src]
Bit 8 - USCI Second Stage Modulation Select 0
pub fn ucbrs1(&mut self) -> UCBRS1_W[src]
Bit 9 - USCI Second Stage Modulation Select 1
pub fn ucbrs2(&mut self) -> UCBRS2_W[src]
Bit 10 - USCI Second Stage Modulation Select 2
pub fn ucbrs3(&mut self) -> UCBRS3_W[src]
Bit 11 - USCI Second Stage Modulation Select 3
pub fn ucbrs4(&mut self) -> UCBRS4_W[src]
Bit 12 - USCI Second Stage Modulation Select 4
pub fn ucbrs5(&mut self) -> UCBRS5_W[src]
Bit 13 - USCI Second Stage Modulation Select 5
pub fn ucbrs6(&mut self) -> UCBRS6_W[src]
Bit 14 - USCI Second Stage Modulation Select 6
pub fn ucbrs7(&mut self) -> UCBRS7_W[src]
Bit 15 - USCI Second Stage Modulation Select 7
impl W<u8, Reg<u8, _UCA0STATW_SPI>>[src]
pub fn ucbusy(&mut self) -> UCBUSY_W[src]
Bit 0 - USCI Busy Flag
pub fn ucoe(&mut self) -> UCOE_W[src]
Bit 5 - USCI Overrun Error Flag
pub fn ucfe(&mut self) -> UCFE_W[src]
Bit 6 - USCI Frame Error Flag
pub fn uclisten(&mut self) -> UCLISTEN_W[src]
Bit 7 - USCI Listen mode
impl W<u8, Reg<u8, _UCA0IE_SPI>>[src]
pub fn ucrxie(&mut self) -> UCRXIE_W[src]
Bit 0 - USCI Receive Interrupt Enable
pub fn uctxie(&mut self) -> UCTXIE_W[src]
Bit 1 - USCI Transmit Interrupt Enable
impl W<u8, Reg<u8, _UCA0IFG_SPI>>[src]
pub fn ucrxifg(&mut self) -> UCRXIFG_W[src]
Bit 0 - SPI Receive Interrupt Flag
pub fn uctxifg(&mut self) -> UCTXIFG_W[src]
Bit 1 - SPI Transmit Interrupt Flag
impl W<u8, Reg<u8, _UCB0STAT_I2C>>[src]
pub fn ucbbusy(&mut self) -> UCBBUSY_W[src]
Bit 4 - Bus Busy Flag
pub fn ucgc(&mut self) -> UCGC_W[src]
Bit 5 - General Call address received Flag
pub fn ucscllow(&mut self) -> UCSCLLOW_W[src]
Bit 6 - SCL low
impl W<u8, Reg<u8, _UCB0BCNT_I2C>>[src]
pub fn ucbcnt0(&mut self) -> UCBCNT0_W[src]
Bit 0 - USCI Byte Counter Bit 0
pub fn ucbcnt1(&mut self) -> UCBCNT1_W[src]
Bit 1 - USCI Byte Counter Bit 1
pub fn ucbcnt2(&mut self) -> UCBCNT2_W[src]
Bit 2 - USCI Byte Counter Bit 2
pub fn ucbcnt3(&mut self) -> UCBCNT3_W[src]
Bit 3 - USCI Byte Counter Bit 3
pub fn ucbcnt4(&mut self) -> UCBCNT4_W[src]
Bit 4 - USCI Byte Counter Bit 4
pub fn ucbcnt5(&mut self) -> UCBCNT5_W[src]
Bit 5 - USCI Byte Counter Bit 5
pub fn ucbcnt6(&mut self) -> UCBCNT6_W[src]
Bit 6 - USCI Byte Counter Bit 6
pub fn ucbcnt7(&mut self) -> UCBCNT7_W[src]
Bit 7 - USCI Byte Counter Bit 7
impl W<u16, Reg<u16, _UCB0CTLW1>>[src]
pub fn ucglit(&mut self) -> UCGLIT_W[src]
Bits 0:1 - USCI Deglitch time Bit: 1
pub fn ucastp(&mut self) -> UCASTP_W[src]
Bits 2:3 - USCI Automatic Stop condition generation Bit: 1
pub fn ucswack(&mut self) -> UCSWACK_W[src]
Bit 4 - USCI Software controlled ACK
pub fn ucstpnack(&mut self) -> UCSTPNACK_W[src]
Bit 5 - USCI Acknowledge Stop last byte
pub fn ucclto(&mut self) -> UCCLTO_W[src]
Bits 6:7 - USCI Clock low timeout Bit: 1
pub fn ucetxint(&mut self) -> UCETXINT_W[src]
Bit 8 - USCI Early UCTXIFG0
impl W<u16, Reg<u16, _UCB0I2COA0>>[src]
pub fn ucoa0(&mut self) -> UCOA0_W[src]
Bit 0 - I2C Own Address Bit 0
pub fn ucoa1(&mut self) -> UCOA1_W[src]
Bit 1 - I2C Own Address Bit 1
pub fn ucoa2(&mut self) -> UCOA2_W[src]
Bit 2 - I2C Own Address Bit 2
pub fn ucoa3(&mut self) -> UCOA3_W[src]
Bit 3 - I2C Own Address Bit 3
pub fn ucoa4(&mut self) -> UCOA4_W[src]
Bit 4 - I2C Own Address Bit 4
pub fn ucoa5(&mut self) -> UCOA5_W[src]
Bit 5 - I2C Own Address Bit 5
pub fn ucoa6(&mut self) -> UCOA6_W[src]
Bit 6 - I2C Own Address Bit 6
pub fn ucoa7(&mut self) -> UCOA7_W[src]
Bit 7 - I2C Own Address Bit 7
pub fn ucoa8(&mut self) -> UCOA8_W[src]
Bit 8 - I2C Own Address Bit 8
pub fn ucoa9(&mut self) -> UCOA9_W[src]
Bit 9 - I2C Own Address Bit 9
pub fn ucoaen(&mut self) -> UCOAEN_W[src]
Bit 10 - I2C Own Address enable
pub fn ucgcen(&mut self) -> UCGCEN_W[src]
Bit 15 - I2C General Call enable
impl W<u16, Reg<u16, _UCB0I2COA1>>[src]
pub fn ucoa0(&mut self) -> UCOA0_W[src]
Bit 0 - I2C Own Address Bit 0
pub fn ucoa1(&mut self) -> UCOA1_W[src]
Bit 1 - I2C Own Address Bit 1
pub fn ucoa2(&mut self) -> UCOA2_W[src]
Bit 2 - I2C Own Address Bit 2
pub fn ucoa3(&mut self) -> UCOA3_W[src]
Bit 3 - I2C Own Address Bit 3
pub fn ucoa4(&mut self) -> UCOA4_W[src]
Bit 4 - I2C Own Address Bit 4
pub fn ucoa5(&mut self) -> UCOA5_W[src]
Bit 5 - I2C Own Address Bit 5
pub fn ucoa6(&mut self) -> UCOA6_W[src]
Bit 6 - I2C Own Address Bit 6
pub fn ucoa7(&mut self) -> UCOA7_W[src]
Bit 7 - I2C Own Address Bit 7
pub fn ucoa8(&mut self) -> UCOA8_W[src]
Bit 8 - I2C Own Address Bit 8
pub fn ucoa9(&mut self) -> UCOA9_W[src]
Bit 9 - I2C Own Address Bit 9
pub fn ucoaen(&mut self) -> UCOAEN_W[src]
Bit 10 - I2C Own Address enable
impl W<u16, Reg<u16, _UCB0I2COA2>>[src]
pub fn ucoa0(&mut self) -> UCOA0_W[src]
Bit 0 - I2C Own Address Bit 0
pub fn ucoa1(&mut self) -> UCOA1_W[src]
Bit 1 - I2C Own Address Bit 1
pub fn ucoa2(&mut self) -> UCOA2_W[src]
Bit 2 - I2C Own Address Bit 2
pub fn ucoa3(&mut self) -> UCOA3_W[src]
Bit 3 - I2C Own Address Bit 3
pub fn ucoa4(&mut self) -> UCOA4_W[src]
Bit 4 - I2C Own Address Bit 4
pub fn ucoa5(&mut self) -> UCOA5_W[src]
Bit 5 - I2C Own Address Bit 5
pub fn ucoa6(&mut self) -> UCOA6_W[src]
Bit 6 - I2C Own Address Bit 6
pub fn ucoa7(&mut self) -> UCOA7_W[src]
Bit 7 - I2C Own Address Bit 7
pub fn ucoa8(&mut self) -> UCOA8_W[src]
Bit 8 - I2C Own Address Bit 8
pub fn ucoa9(&mut self) -> UCOA9_W[src]
Bit 9 - I2C Own Address Bit 9
pub fn ucoaen(&mut self) -> UCOAEN_W[src]
Bit 10 - I2C Own Address enable
impl W<u16, Reg<u16, _UCB0I2COA3>>[src]
pub fn ucoa0(&mut self) -> UCOA0_W[src]
Bit 0 - I2C Own Address Bit 0
pub fn ucoa1(&mut self) -> UCOA1_W[src]
Bit 1 - I2C Own Address Bit 1
pub fn ucoa2(&mut self) -> UCOA2_W[src]
Bit 2 - I2C Own Address Bit 2
pub fn ucoa3(&mut self) -> UCOA3_W[src]
Bit 3 - I2C Own Address Bit 3
pub fn ucoa4(&mut self) -> UCOA4_W[src]
Bit 4 - I2C Own Address Bit 4
pub fn ucoa5(&mut self) -> UCOA5_W[src]
Bit 5 - I2C Own Address Bit 5
pub fn ucoa6(&mut self) -> UCOA6_W[src]
Bit 6 - I2C Own Address Bit 6
pub fn ucoa7(&mut self) -> UCOA7_W[src]
Bit 7 - I2C Own Address Bit 7
pub fn ucoa8(&mut self) -> UCOA8_W[src]
Bit 8 - I2C Own Address Bit 8
pub fn ucoa9(&mut self) -> UCOA9_W[src]
Bit 9 - I2C Own Address Bit 9
pub fn ucoaen(&mut self) -> UCOAEN_W[src]
Bit 10 - I2C Own Address enable
impl W<u16, Reg<u16, _UCB0ADDRX>>[src]
pub fn ucaddrx0(&mut self) -> UCADDRX0_W[src]
Bit 0 - I2C Receive Address Bit 0
pub fn ucaddrx1(&mut self) -> UCADDRX1_W[src]
Bit 1 - I2C Receive Address Bit 1
pub fn ucaddrx2(&mut self) -> UCADDRX2_W[src]
Bit 2 - I2C Receive Address Bit 2
pub fn ucaddrx3(&mut self) -> UCADDRX3_W[src]
Bit 3 - I2C Receive Address Bit 3
pub fn ucaddrx4(&mut self) -> UCADDRX4_W[src]
Bit 4 - I2C Receive Address Bit 4
pub fn ucaddrx5(&mut self) -> UCADDRX5_W[src]
Bit 5 - I2C Receive Address Bit 5
pub fn ucaddrx6(&mut self) -> UCADDRX6_W[src]
Bit 6 - I2C Receive Address Bit 6
pub fn ucaddrx7(&mut self) -> UCADDRX7_W[src]
Bit 7 - I2C Receive Address Bit 7
pub fn ucaddrx8(&mut self) -> UCADDRX8_W[src]
Bit 8 - I2C Receive Address Bit 8
pub fn ucaddrx9(&mut self) -> UCADDRX9_W[src]
Bit 9 - I2C Receive Address Bit 9
impl W<u16, Reg<u16, _UCB0ADDMASK>>[src]
pub fn ucaddmask0(&mut self) -> UCADDMASK0_W[src]
Bit 0 - I2C Address Mask Bit 0
pub fn ucaddmask1(&mut self) -> UCADDMASK1_W[src]
Bit 1 - I2C Address Mask Bit 1
pub fn ucaddmask2(&mut self) -> UCADDMASK2_W[src]
Bit 2 - I2C Address Mask Bit 2
pub fn ucaddmask3(&mut self) -> UCADDMASK3_W[src]
Bit 3 - I2C Address Mask Bit 3
pub fn ucaddmask4(&mut self) -> UCADDMASK4_W[src]
Bit 4 - I2C Address Mask Bit 4
pub fn ucaddmask5(&mut self) -> UCADDMASK5_W[src]
Bit 5 - I2C Address Mask Bit 5
pub fn ucaddmask6(&mut self) -> UCADDMASK6_W[src]
Bit 6 - I2C Address Mask Bit 6
pub fn ucaddmask7(&mut self) -> UCADDMASK7_W[src]
Bit 7 - I2C Address Mask Bit 7
pub fn ucaddmask8(&mut self) -> UCADDMASK8_W[src]
Bit 8 - I2C Address Mask Bit 8
pub fn ucaddmask9(&mut self) -> UCADDMASK9_W[src]
Bit 9 - I2C Address Mask Bit 9
impl W<u16, Reg<u16, _UCB0I2CSA>>[src]
pub fn ucsa0(&mut self) -> UCSA0_W[src]
Bit 0 - I2C Slave Address Bit 0
pub fn ucsa1(&mut self) -> UCSA1_W[src]
Bit 1 - I2C Slave Address Bit 1
pub fn ucsa2(&mut self) -> UCSA2_W[src]
Bit 2 - I2C Slave Address Bit 2
pub fn ucsa3(&mut self) -> UCSA3_W[src]
Bit 3 - I2C Slave Address Bit 3
pub fn ucsa4(&mut self) -> UCSA4_W[src]
Bit 4 - I2C Slave Address Bit 4
pub fn ucsa5(&mut self) -> UCSA5_W[src]
Bit 5 - I2C Slave Address Bit 5
pub fn ucsa6(&mut self) -> UCSA6_W[src]
Bit 6 - I2C Slave Address Bit 6
pub fn ucsa7(&mut self) -> UCSA7_W[src]
Bit 7 - I2C Slave Address Bit 7
pub fn ucsa8(&mut self) -> UCSA8_W[src]
Bit 8 - I2C Slave Address Bit 8
pub fn ucsa9(&mut self) -> UCSA9_W[src]
Bit 9 - I2C Slave Address Bit 9
impl W<u16, Reg<u16, _UCB0IE_I2C>>[src]
pub fn ucrxie0(&mut self) -> UCRXIE0_W[src]
Bit 0 - I2C Receive Interrupt Enable 0
pub fn uctxie0(&mut self) -> UCTXIE0_W[src]
Bit 1 - I2C Transmit Interrupt Enable 0
pub fn ucsttie(&mut self) -> UCSTTIE_W[src]
Bit 2 - I2C START Condition interrupt enable
pub fn ucstpie(&mut self) -> UCSTPIE_W[src]
Bit 3 - I2C STOP Condition interrupt enable
pub fn ucalie(&mut self) -> UCALIE_W[src]
Bit 4 - I2C Arbitration Lost interrupt enable
pub fn ucnackie(&mut self) -> UCNACKIE_W[src]
Bit 5 - I2C NACK Condition interrupt enable
pub fn ucbcntie(&mut self) -> UCBCNTIE_W[src]
Bit 6 - I2C Automatic stop assertion interrupt enable
pub fn uccltoie(&mut self) -> UCCLTOIE_W[src]
Bit 7 - I2C Clock Low Timeout interrupt enable
pub fn ucrxie1(&mut self) -> UCRXIE1_W[src]
Bit 8 - I2C Receive Interrupt Enable 1
pub fn uctxie1(&mut self) -> UCTXIE1_W[src]
Bit 9 - I2C Transmit Interrupt Enable 1
pub fn ucrxie2(&mut self) -> UCRXIE2_W[src]
Bit 10 - I2C Receive Interrupt Enable 2
pub fn uctxie2(&mut self) -> UCTXIE2_W[src]
Bit 11 - I2C Transmit Interrupt Enable 2
pub fn ucrxie3(&mut self) -> UCRXIE3_W[src]
Bit 12 - I2C Receive Interrupt Enable 3
pub fn uctxie3(&mut self) -> UCTXIE3_W[src]
Bit 13 - I2C Transmit Interrupt Enable 3
pub fn ucbit9ie(&mut self) -> UCBIT9IE_W[src]
Bit 14 - I2C Bit 9 Position Interrupt Enable 3
impl W<u16, Reg<u16, _UCB0IFG_I2C>>[src]
pub fn ucrxifg0(&mut self) -> UCRXIFG0_W[src]
Bit 0 - I2C Receive Interrupt Flag 0
pub fn uctxifg0(&mut self) -> UCTXIFG0_W[src]
Bit 1 - I2C Transmit Interrupt Flag 0
pub fn ucsttifg(&mut self) -> UCSTTIFG_W[src]
Bit 2 - I2C START Condition interrupt Flag
pub fn ucstpifg(&mut self) -> UCSTPIFG_W[src]
Bit 3 - I2C STOP Condition interrupt Flag
pub fn ucalifg(&mut self) -> UCALIFG_W[src]
Bit 4 - I2C Arbitration Lost interrupt Flag
pub fn ucnackifg(&mut self) -> UCNACKIFG_W[src]
Bit 5 - I2C NACK Condition interrupt Flag
pub fn ucbcntifg(&mut self) -> UCBCNTIFG_W[src]
Bit 6 - I2C Byte counter interrupt flag
pub fn uccltoifg(&mut self) -> UCCLTOIFG_W[src]
Bit 7 - I2C Clock low Timeout interrupt Flag
pub fn ucrxifg1(&mut self) -> UCRXIFG1_W[src]
Bit 8 - I2C Receive Interrupt Flag 1
pub fn uctxifg1(&mut self) -> UCTXIFG1_W[src]
Bit 9 - I2C Transmit Interrupt Flag 1
pub fn ucrxifg2(&mut self) -> UCRXIFG2_W[src]
Bit 10 - I2C Receive Interrupt Flag 2
pub fn uctxifg2(&mut self) -> UCTXIFG2_W[src]
Bit 11 - I2C Transmit Interrupt Flag 2
pub fn ucrxifg3(&mut self) -> UCRXIFG3_W[src]
Bit 12 - I2C Receive Interrupt Flag 3
pub fn uctxifg3(&mut self) -> UCTXIFG3_W[src]
Bit 13 - I2C Transmit Interrupt Flag 3
pub fn ucbit9ifg(&mut self) -> UCBIT9IFG_W[src]
Bit 14 - I2C Bit 9 Possition Interrupt Flag 3
impl W<u16, Reg<u16, _UCB0IE_SPI>>[src]
pub fn ucrxie(&mut self) -> UCRXIE_W[src]
Bit 0 - USCI Receive Interrupt Enable
pub fn uctxie(&mut self) -> UCTXIE_W[src]
Bit 1 - USCI Transmit Interrupt Enable
impl W<u16, Reg<u16, _UCB0IFG_SPI>>[src]
pub fn ucrxifg(&mut self) -> UCRXIFG_W[src]
Bit 0 - SPI Receive Interrupt Flag
pub fn uctxifg(&mut self) -> UCTXIFG_W[src]
Bit 1 - SPI Transmit Interrupt Flag
impl W<u16, Reg<u16, _SFRIE1>>[src]
pub fn wdtie(&mut self) -> WDTIE_W[src]
Bit 0 - WDT Interrupt Enable
pub fn ofie(&mut self) -> OFIE_W[src]
Bit 1 - Osc Fault Enable
pub fn vmaie(&mut self) -> VMAIE_W[src]
Bit 3 - Vacant Memory Interrupt Enable
pub fn nmiie(&mut self) -> NMIIE_W[src]
Bit 4 - NMI Interrupt Enable
pub fn jmbinie(&mut self) -> JMBINIE_W[src]
Bit 6 - JTAG Mail Box input Interrupt Enable
pub fn jmboutie(&mut self) -> JMBOUTIE_W[src]
Bit 7 - JTAG Mail Box output Interrupt Enable
impl W<u16, Reg<u16, _SFRIFG1>>[src]
pub fn wdtifg(&mut self) -> WDTIFG_W[src]
Bit 0 - WDT Interrupt Flag
pub fn ofifg(&mut self) -> OFIFG_W[src]
Bit 1 - Osc Fault Flag
pub fn vmaifg(&mut self) -> VMAIFG_W[src]
Bit 3 - Vacant Memory Interrupt Flag
pub fn nmiifg(&mut self) -> NMIIFG_W[src]
Bit 4 - NMI Interrupt Flag
pub fn jmbinifg(&mut self) -> JMBINIFG_W[src]
Bit 6 - JTAG Mail Box input Interrupt Flag
pub fn jmboutifg(&mut self) -> JMBOUTIFG_W[src]
Bit 7 - JTAG Mail Box output Interrupt Flag
impl W<u16, Reg<u16, _SFRRPCR>>[src]
pub fn sysnmi(&mut self) -> SYSNMI_W[src]
Bit 0 - NMI select
pub fn sysnmiies(&mut self) -> SYSNMIIES_W[src]
Bit 1 - NMI edge select
pub fn sysrstup(&mut self) -> SYSRSTUP_W[src]
Bit 2 - RESET Pin pull down/up select
pub fn sysrstre(&mut self) -> SYSRSTRE_W[src]
Bit 3 - RESET Pin Resistor enable
impl W<u16, Reg<u16, _PMMCTL0>>[src]
pub fn pmmswbor(&mut self) -> PMMSWBOR_W[src]
Bit 2 - PMM Software BOR
pub fn pmmswpor(&mut self) -> PMMSWPOR_W[src]
Bit 3 - PMM Software POR
pub fn pmmregoff(&mut self) -> PMMREGOFF_W[src]
Bit 4 - PMM Turn Regulator off
pub fn svshe(&mut self) -> SVSHE_W[src]
Bit 6 - SVS high side enable
pub fn pmmpw(&mut self) -> PMMPW_W[src]
Bits 8:15 - PMM Password
impl W<u16, Reg<u16, _PMMCTL2>>[src]
pub fn intrefen(&mut self) -> INTREFEN_W[src]
Bit 0 - Internal Reference Enable
pub fn extrefen(&mut self) -> EXTREFEN_W[src]
Bit 1 - External Reference output Enable
pub fn tsensoren(&mut self) -> TSENSOREN_W[src]
Bit 3 - Temperature Sensor Enable
pub fn refgenact(&mut self) -> REFGENACT_W[src]
Bit 8 - REF Reference generator active
pub fn refbgact(&mut self) -> REFBGACT_W[src]
Bit 9 - REF Reference bandgap active
pub fn bgmode(&mut self) -> BGMODE_W[src]
Bit 11 - REF Bandgap mode
pub fn refgenrdy(&mut self) -> REFGENRDY_W[src]
Bit 12 - REF Reference generator ready
pub fn refbgrdy(&mut self) -> REFBGRDY_W[src]
Bit 13 - REF Reference bandgap ready
pub fn refgen(&mut self) -> REFGEN_W[src]
Bit 6 - Reference generator trigger. If written with a 1, the generation of the variable reference voltage is started. When the reference voltage request is set, this bit is cleared by hardware or writing 0.
pub fn refbgen(&mut self) -> REFBGEN_W[src]
Bit 7 - Bandgap and bandgap buffer trigger. If written with a 1, the generation of the buffered bandgap voltage is started. When the bandgap buffer voltage request is set, this bit is cleared by hardware or writing 0.
pub fn refvsel(&mut self) -> REFVSEL_W[src]
Bits 4:5 - Internal reference voltage level select. 00b = 1.5V, 01b = 2.0V, 10b = 2.5V
impl W<u16, Reg<u16, _PMMIFG>>[src]
pub fn pmmborifg(&mut self) -> PMMBORIFG_W[src]
Bit 8 - PMM Software BOR interrupt flag
pub fn pmmrstifg(&mut self) -> PMMRSTIFG_W[src]
Bit 9 - PMM RESET pin interrupt flag
pub fn pmmporifg(&mut self) -> PMMPORIFG_W[src]
Bit 10 - PMM Software POR interrupt flag
pub fn svshifg(&mut self) -> SVSHIFG_W[src]
Bit 13 - SVS low side interrupt flag
pub fn pmmlpm5ifg(&mut self) -> PMMLPM5IFG_W[src]
Bit 15 - LPM5 indication Flag
impl W<u16, Reg<u16, _PM5CTL0>>[src]
pub fn locklpm5(&mut self) -> LOCKLPM5_W[src]
Bit 0 - Lock I/O pin configuration upon entry/exit to/from LPM5
pub fn lpm5sw(&mut self) -> LPM5SW_W[src]
Bit 4 - LPMx.5 switch dis/connected
pub fn lpm5sm(&mut self) -> LPM5SM_W[src]
Bit 5 - Manual mode for LPM3.5 switch
impl W<u16, Reg<u16, _SYSCTL>>[src]
pub fn sysrivect(&mut self) -> SYSRIVECT_W[src]
Bit 0 - SYS - RAM based interrupt vectors
pub fn syspmmpe(&mut self) -> SYSPMMPE_W[src]
Bit 2 - SYS - PMM access protect
pub fn sysbslind(&mut self) -> SYSBSLIND_W[src]
Bit 4 - SYS - TCK/RST indication detected
pub fn sysjtagpin(&mut self) -> SYSJTAGPIN_W[src]
Bit 5 - SYS - Dedicated JTAG pins enabled
impl W<u16, Reg<u16, _SYSBSLC>>[src]
pub fn sysbslr(&mut self) -> SYSBSLR_W[src]
Bit 2 - SYS - RAM assigned to BSL
pub fn sysbsloff(&mut self) -> SYSBSLOFF_W[src]
Bit 14 - SYS - BSL Memory disabled
pub fn sysbslpe(&mut self) -> SYSBSLPE_W[src]
Bit 15 - SYS - BSL Memory protection enabled
impl W<u16, Reg<u16, _SYSJMBC>>[src]
pub fn jmbin0fg(&mut self) -> JMBIN0FG_W[src]
Bit 0 - SYS - Incoming JTAG Mailbox 0 Flag
pub fn jmbin1fg(&mut self) -> JMBIN1FG_W[src]
Bit 1 - SYS - Incoming JTAG Mailbox 1 Flag
pub fn jmbout0fg(&mut self) -> JMBOUT0FG_W[src]
Bit 2 - SYS - Outgoing JTAG Mailbox 0 Flag
pub fn jmbout1fg(&mut self) -> JMBOUT1FG_W[src]
Bit 3 - SYS - Outgoing JTAG Mailbox 1 Flag
pub fn jmbmode(&mut self) -> JMBMODE_W[src]
Bit 4 - SYS - JMB 16/32 Bit Mode
pub fn jmbclr0off(&mut self) -> JMBCLR0OFF_W[src]
Bit 6 - SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe
pub fn jmbclr1off(&mut self) -> JMBCLR1OFF_W[src]
Bit 7 - SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe
impl W<u16, Reg<u16, _SYSCFG0>>[src]
pub fn pfwp(&mut self) -> PFWP_W[src]
Bit 0 - Program FRAM Write Protection
pub fn dfwp(&mut self) -> DFWP_W[src]
Bit 1 - Data FRAM Write Protection
impl W<u16, Reg<u16, _SYSCFG1>>[src]
pub fn iren(&mut self) -> IREN_W[src]
Bit 0 - Infrared enable
pub fn irpsel(&mut self) -> IRPSEL_W[src]
Bit 1 - Infrared polarity select
pub fn irmsel(&mut self) -> IRMSEL_W[src]
Bit 2 - Infrared mode select
pub fn irdssel(&mut self) -> IRDSSEL_W[src]
Bit 3 - Infrared data source select
pub fn irdata(&mut self) -> IRDATA_W[src]
Bit 4 - Infrared enable
impl W<u16, Reg<u16, _SYSCFG2>>[src]
pub fn adcpctl0(&mut self) -> ADCPCTL0_W[src]
Bit 0 - ADC input A0 pin select
pub fn adcpctl1(&mut self) -> ADCPCTL1_W[src]
Bit 1 - ADC input A1 pin select
pub fn adcpctl2(&mut self) -> ADCPCTL2_W[src]
Bit 2 - ADC input A2 pin select
pub fn adcpctl3(&mut self) -> ADCPCTL3_W[src]
Bit 3 - ADC input A3 pin select
pub fn adcpctl4(&mut self) -> ADCPCTL4_W[src]
Bit 4 - ADC input A4 pin select
pub fn adcpctl5(&mut self) -> ADCPCTL5_W[src]
Bit 5 - ADC input A5 pin select
pub fn adcpctl6(&mut self) -> ADCPCTL6_W[src]
Bit 6 - ADC input A6 pin select
pub fn adcpctl7(&mut self) -> ADCPCTL7_W[src]
Bit 7 - ADC input A7 pin select
pub fn adcpctl8(&mut self) -> ADCPCTL8_W[src]
Bit 8 - ADC input A8 pin select
pub fn adcpctl9(&mut self) -> ADCPCTL9_W[src]
Bit 9 - ADC input A9 pin select
pub fn lcdpctl(&mut self) -> LCDPCTL_W[src]
Bit 12 - LCD Power Pin
impl W<u16, Reg<u16, _CSCTL0>>[src]
pub fn dco0(&mut self) -> DCO0_W[src]
Bit 0 - DCO TAP Bit : 0
pub fn dco1(&mut self) -> DCO1_W[src]
Bit 1 - DCO TAP Bit : 1
pub fn dco2(&mut self) -> DCO2_W[src]
Bit 2 - DCO TAP Bit : 2
pub fn dco3(&mut self) -> DCO3_W[src]
Bit 3 - DCO TAP Bit : 3
pub fn dco4(&mut self) -> DCO4_W[src]
Bit 4 - DCO TAP Bit : 4
pub fn dco5(&mut self) -> DCO5_W[src]
Bit 5 - DCO TAP Bit : 5
pub fn dco6(&mut self) -> DCO6_W[src]
Bit 6 - DCO TAP Bit : 6
pub fn dco7(&mut self) -> DCO7_W[src]
Bit 7 - DCO TAP Bit : 7
pub fn dco8(&mut self) -> DCO8_W[src]
Bit 8 - DCO TAP Bit : 8
pub fn mod0(&mut self) -> MOD0_W[src]
Bit 9 - Modulation Bit Counter Bit : 0
pub fn mod1(&mut self) -> MOD1_W[src]
Bit 10 - Modulation Bit Counter Bit : 1
pub fn mod2(&mut self) -> MOD2_W[src]
Bit 11 - Modulation Bit Counter Bit : 2
pub fn mod3(&mut self) -> MOD3_W[src]
Bit 12 - Modulation Bit Counter Bit : 3
pub fn mod4(&mut self) -> MOD4_W[src]
Bit 13 - Modulation Bit Counter Bit : 4
impl W<u16, Reg<u16, _CSCTL1>>[src]
pub fn dismod(&mut self) -> DISMOD_W[src]
Bit 0 - Disable Modulation
pub fn dcorsel(&mut self) -> DCORSEL_W[src]
Bits 1:3 - DCO frequency range select Bit: 0
pub fn dcoftrim(&mut self) -> DCOFTRIM_W[src]
Bits 4:6 - DCO frequency trim. Bit: 0
pub fn dcoftrimen(&mut self) -> DCOFTRIMEN_W[src]
Bit 7 - DCO frequency trim enable
impl W<u16, Reg<u16, _CSCTL2>>[src]
pub fn flln0(&mut self) -> FLLN0_W[src]
Bit 0 - FLL Multipier Bit : 0
pub fn flln1(&mut self) -> FLLN1_W[src]
Bit 1 - FLL Multipier Bit : 1
pub fn flln2(&mut self) -> FLLN2_W[src]
Bit 2 - FLL Multipier Bit : 2
pub fn flln3(&mut self) -> FLLN3_W[src]
Bit 3 - FLL Multipier Bit : 3
pub fn flln4(&mut self) -> FLLN4_W[src]
Bit 4 - FLL Multipier Bit : 4
pub fn flln5(&mut self) -> FLLN5_W[src]
Bit 5 - FLL Multipier Bit : 5
pub fn flln6(&mut self) -> FLLN6_W[src]
Bit 6 - FLL Multipier Bit : 6
pub fn flln7(&mut self) -> FLLN7_W[src]
Bit 7 - FLL Multipier Bit : 7
pub fn flln8(&mut self) -> FLLN8_W[src]
Bit 8 - FLL Multipier Bit : 8
pub fn flln9(&mut self) -> FLLN9_W[src]
Bit 9 - FLL Multipier Bit : 9
pub fn flld(&mut self) -> FLLD_W[src]
Bits 12:14 - Loop Divider Bit : 0
impl W<u16, Reg<u16, _CSCTL3>>[src]
pub fn fllrefdiv(&mut self) -> FLLREFDIV_W[src]
Bits 0:2 - Reference Divider Bit : 0
pub fn selref(&mut self) -> SELREF_W[src]
Bits 4:5 - FLL Reference Clock Select Bit : 0
impl W<u16, Reg<u16, _CSCTL4>>[src]
pub fn selms(&mut self) -> SELMS_W[src]
Bits 0:2 - MCLK and SMCLK Source Select Bit: 0
pub fn sela(&mut self) -> SELA_W[src]
Bit 8 - ACLK Source Select Bit: 0
impl W<u16, Reg<u16, _CSCTL5>>[src]
pub fn divm(&mut self) -> DIVM_W[src]
Bits 0:2 - MCLK Divider Bit: 0
pub fn divs(&mut self) -> DIVS_W[src]
Bits 4:5 - SMCLK Divider Bit: 0
pub fn smclkoff(&mut self) -> SMCLKOFF_W[src]
Bit 8 - SMCLK off
pub fn vloautooff(&mut self) -> VLOAUTOOFF_W[src]
Bit 12 - VLO automatic off enable
impl W<u16, Reg<u16, _CSCTL6>>[src]
pub fn xt1autooff(&mut self) -> XT1AUTOOFF_W[src]
Bit 0 - XT1 automatic off enable
pub fn xt1agcoff(&mut self) -> XT1AGCOFF_W[src]
Bit 1 - XT1 Automatic Gain Control (AGC) disable
pub fn xt1bypass(&mut self) -> XT1BYPASS_W[src]
Bit 4 - XT1 bypass mode : 0: internal 1:sourced from external pin
pub fn xts(&mut self) -> XTS_W[src]
Bit 5 - 1: Selects high-freq. oscillator
pub fn xt1drive(&mut self) -> XT1DRIVE_W[src]
Bits 6:7 - XT1 Drive Level mode Bit 0
impl W<u16, Reg<u16, _CSCTL7>>[src]
pub fn dcoffg(&mut self) -> DCOFFG_W[src]
Bit 0 - DCO fault flag
pub fn xt1offg(&mut self) -> XT1OFFG_W[src]
Bit 1 - XT1 Low Frequency Oscillator Fault Flag
pub fn fllulifg(&mut self) -> FLLULIFG_W[src]
Bit 4 - FLL unlock interrupt flag
pub fn enstfcnt1(&mut self) -> ENSTFCNT1_W[src]
Bit 6 - Enable start counter for XT1
pub fn fllunlock(&mut self) -> FLLUNLOCK_W[src]
Bits 8:9 - FLL unlock condition Bit: 0
pub fn fllunlockhis(&mut self) -> FLLUNLOCKHIS_W[src]
Bits 10:11 - Unlock history Bit: 0
pub fn fllulpuc(&mut self) -> FLLULPUC_W[src]
Bit 12 - FLL unlock PUC enable
pub fn fllwarnen(&mut self) -> FLLWARNEN_W[src]
Bit 13 - Warning enable
impl W<u16, Reg<u16, _CSCTL8>>[src]
pub fn aclkreqen(&mut self) -> ACLKREQEN_W[src]
Bit 0 - ACLK Clock Request Enable
pub fn mclkreqen(&mut self) -> MCLKREQEN_W[src]
Bit 1 - MCLK Clock Request Enable
pub fn smclkreqen(&mut self) -> SMCLKREQEN_W[src]
Bit 2 - SMCLK Clock Request Enable
pub fn modoscreqen(&mut self) -> MODOSCREQEN_W[src]
Bit 3 - MODOSC Clock Request Enable
impl W<u16, Reg<u16, _FRCTL0>>[src]
pub fn nwaits(&mut self) -> NWAITS_W[src]
Bits 4:6 - FRAM Wait state control Bit: 0
pub fn frctlpw(&mut self) -> FRCTLPW_W[src]
Bits 8:15 - FRCTLPW Password
impl W<u16, Reg<u16, _GCCTL0>>[src]
pub fn frlpmpwr(&mut self) -> FRLPMPWR_W[src]
Bit 1 - FRAM Enable FRAM auto power up after LPM
pub fn frpwr(&mut self) -> FRPWR_W[src]
Bit 2 - FRAM Power Control
pub fn accteie(&mut self) -> ACCTEIE_W[src]
Bit 3 - RESERVED
pub fn cbdie(&mut self) -> CBDIE_W[src]
Bit 5 - Enable NMI event if correctable bit error detected
pub fn ubdie(&mut self) -> UBDIE_W[src]
Bit 6 - Enable NMI event if uncorrectable bit error detected
pub fn ubdrsten(&mut self) -> UBDRSTEN_W[src]
Bit 7 - Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected
impl W<u16, Reg<u16, _GCCTL1>>[src]
pub fn cbdifg(&mut self) -> CBDIFG_W[src]
Bit 1 - FRAM correctable bit error flag
pub fn ubdifg(&mut self) -> UBDIFG_W[src]
Bit 2 - FRAM uncorrectable bit error flag
pub fn accteifg(&mut self) -> ACCTEIFG_W[src]
Bit 3 - Access time error flag
impl W<u16, Reg<u16, _WDTCTL>>[src]
pub fn wdtis(&mut self) -> WDTIS_W[src]
Bits 0:2 - WDT - Timer Interval Select 0
pub fn wdtcntcl(&mut self) -> WDTCNTCL_W[src]
Bit 3 - WDT - Timer Clear
pub fn wdttmsel(&mut self) -> WDTTMSEL_W[src]
Bit 4 - WDT - Timer Mode Select
pub fn wdtssel(&mut self) -> WDTSSEL_W[src]
Bits 5:6 - WDT - Timer Clock Source Select 0
pub fn wdthold(&mut self) -> WDTHOLD_W[src]
Bit 7 - WDT - Timer hold
pub fn wdtpw(&mut self) -> WDTPW_W[src]
Bits 8:15 - Watchdog Timer Password
impl W<u16, Reg<u16, _CAPTIO0CTL>>[src]
pub fn captiopisel0(&mut self) -> CAPTIOPISEL0_W[src]
Bit 1 - CapTouchIO Pin Select Bit: 0
pub fn captiopisel1(&mut self) -> CAPTIOPISEL1_W[src]
Bit 2 - CapTouchIO Pin Select Bit: 1
pub fn captiopisel2(&mut self) -> CAPTIOPISEL2_W[src]
Bit 3 - CapTouchIO Pin Select Bit: 2
pub fn captioposel0(&mut self) -> CAPTIOPOSEL0_W[src]
Bit 4 - CapTouchIO Port Select Bit: 0
pub fn captioposel1(&mut self) -> CAPTIOPOSEL1_W[src]
Bit 5 - CapTouchIO Port Select Bit: 1
pub fn captioposel2(&mut self) -> CAPTIOPOSEL2_W[src]
Bit 6 - CapTouchIO Port Select Bit: 2
pub fn captioposel3(&mut self) -> CAPTIOPOSEL3_W[src]
Bit 7 - CapTouchIO Port Select Bit: 3
pub fn captioen(&mut self) -> CAPTIOEN_W[src]
Bit 8 - CapTouchIO Enable
pub fn captio(&mut self) -> CAPTIO_W[src]
Bit 9 - CapTouchIO state
impl W<u16, Reg<u16, _TA0CTL>>[src]
pub fn taifg(&mut self) -> TAIFG_W[src]
Bit 0 - Timer A counter interrupt flag
pub fn taie(&mut self) -> TAIE_W[src]
Bit 1 - Timer A counter interrupt enable
pub fn taclr(&mut self) -> TACLR_W[src]
Bit 2 - Timer A counter clear
pub fn mc(&mut self) -> MC_W[src]
Bits 4:5 - Timer A mode control 1
pub fn id(&mut self) -> ID_W[src]
Bits 6:7 - Timer A clock input divider 1
pub fn tassel(&mut self) -> TASSEL_W[src]
Bits 8:9 - Timer A clock source select 1
impl W<u16, Reg<u16, _TA0CCTL0>>[src]
pub fn ccifg(&mut self) -> CCIFG_W[src]
Bit 0 - Capture/compare interrupt flag
pub fn cov(&mut self) -> COV_W[src]
Bit 1 - Capture/compare overflow flag
pub fn out(&mut self) -> OUT_W[src]
Bit 2 - PWM Output signal if output mode 0
pub fn cci(&mut self) -> CCI_W[src]
Bit 3 - Capture input signal (read)
pub fn ccie(&mut self) -> CCIE_W[src]
Bit 4 - Capture/compare interrupt enable
pub fn outmod(&mut self) -> OUTMOD_W[src]
Bits 5:7 - Output mode 2
pub fn cap(&mut self) -> CAP_W[src]
Bit 8 - Capture mode: 1 /Compare mode : 0
pub fn scci(&mut self) -> SCCI_W[src]
Bit 10 - Latched capture signal (read)
pub fn scs(&mut self) -> SCS_W[src]
Bit 11 - Capture sychronize
pub fn ccis(&mut self) -> CCIS_W[src]
Bits 12:13 - Capture input select 1
pub fn cm(&mut self) -> CM_W[src]
Bits 14:15 - Capture mode 1
impl W<u16, Reg<u16, _TA0CCTL1>>[src]
pub fn ccifg(&mut self) -> CCIFG_W[src]
Bit 0 - Capture/compare interrupt flag
pub fn cov(&mut self) -> COV_W[src]
Bit 1 - Capture/compare overflow flag
pub fn out(&mut self) -> OUT_W[src]
Bit 2 - PWM Output signal if output mode 0
pub fn cci(&mut self) -> CCI_W[src]
Bit 3 - Capture input signal (read)
pub fn ccie(&mut self) -> CCIE_W[src]
Bit 4 - Capture/compare interrupt enable
pub fn outmod(&mut self) -> OUTMOD_W[src]
Bits 5:7 - Output mode 2
pub fn cap(&mut self) -> CAP_W[src]
Bit 8 - Capture mode: 1 /Compare mode : 0
pub fn scci(&mut self) -> SCCI_W[src]
Bit 10 - Latched capture signal (read)
pub fn scs(&mut self) -> SCS_W[src]
Bit 11 - Capture sychronize
pub fn ccis(&mut self) -> CCIS_W[src]
Bits 12:13 - Capture input select 1
pub fn cm(&mut self) -> CM_W[src]
Bits 14:15 - Capture mode 1
impl W<u16, Reg<u16, _TA0CCTL2>>[src]
pub fn ccifg(&mut self) -> CCIFG_W[src]
Bit 0 - Capture/compare interrupt flag
pub fn cov(&mut self) -> COV_W[src]
Bit 1 - Capture/compare overflow flag
pub fn out(&mut self) -> OUT_W[src]
Bit 2 - PWM Output signal if output mode 0
pub fn cci(&mut self) -> CCI_W[src]
Bit 3 - Capture input signal (read)
pub fn ccie(&mut self) -> CCIE_W[src]
Bit 4 - Capture/compare interrupt enable
pub fn outmod(&mut self) -> OUTMOD_W[src]
Bits 5:7 - Output mode 2
pub fn cap(&mut self) -> CAP_W[src]
Bit 8 - Capture mode: 1 /Compare mode : 0
pub fn scci(&mut self) -> SCCI_W[src]
Bit 10 - Latched capture signal (read)
pub fn scs(&mut self) -> SCS_W[src]
Bit 11 - Capture sychronize
pub fn ccis(&mut self) -> CCIS_W[src]
Bits 12:13 - Capture input select 1
pub fn cm(&mut self) -> CM_W[src]
Bits 14:15 - Capture mode 1
impl W<u16, Reg<u16, _TA0EX0>>[src]
impl W<u16, Reg<u16, _TA1CTL>>[src]
pub fn taifg(&mut self) -> TAIFG_W[src]
Bit 0 - Timer A counter interrupt flag
pub fn taie(&mut self) -> TAIE_W[src]
Bit 1 - Timer A counter interrupt enable
pub fn taclr(&mut self) -> TACLR_W[src]
Bit 2 - Timer A counter clear
pub fn mc(&mut self) -> MC_W[src]
Bits 4:5 - Timer A mode control 1
pub fn id(&mut self) -> ID_W[src]
Bits 6:7 - Timer A clock input divider 1
pub fn tassel(&mut self) -> TASSEL_W[src]
Bits 8:9 - Timer A clock source select 1
impl W<u16, Reg<u16, _TA1CCTL0>>[src]
pub fn ccifg(&mut self) -> CCIFG_W[src]
Bit 0 - Capture/compare interrupt flag
pub fn cov(&mut self) -> COV_W[src]
Bit 1 - Capture/compare overflow flag
pub fn out(&mut self) -> OUT_W[src]
Bit 2 - PWM Output signal if output mode 0
pub fn cci(&mut self) -> CCI_W[src]
Bit 3 - Capture input signal (read)
pub fn ccie(&mut self) -> CCIE_W[src]
Bit 4 - Capture/compare interrupt enable
pub fn outmod(&mut self) -> OUTMOD_W[src]
Bits 5:7 - Output mode 2
pub fn cap(&mut self) -> CAP_W[src]
Bit 8 - Capture mode: 1 /Compare mode : 0
pub fn scci(&mut self) -> SCCI_W[src]
Bit 10 - Latched capture signal (read)
pub fn scs(&mut self) -> SCS_W[src]
Bit 11 - Capture sychronize
pub fn ccis(&mut self) -> CCIS_W[src]
Bits 12:13 - Capture input select 1
pub fn cm(&mut self) -> CM_W[src]
Bits 14:15 - Capture mode 1
impl W<u16, Reg<u16, _TA1CCTL1>>[src]
pub fn ccifg(&mut self) -> CCIFG_W[src]
Bit 0 - Capture/compare interrupt flag
pub fn cov(&mut self) -> COV_W[src]
Bit 1 - Capture/compare overflow flag
pub fn out(&mut self) -> OUT_W[src]
Bit 2 - PWM Output signal if output mode 0
pub fn cci(&mut self) -> CCI_W[src]
Bit 3 - Capture input signal (read)
pub fn ccie(&mut self) -> CCIE_W[src]
Bit 4 - Capture/compare interrupt enable
pub fn outmod(&mut self) -> OUTMOD_W[src]
Bits 5:7 - Output mode 2
pub fn cap(&mut self) -> CAP_W[src]
Bit 8 - Capture mode: 1 /Compare mode : 0
pub fn scci(&mut self) -> SCCI_W[src]
Bit 10 - Latched capture signal (read)
pub fn scs(&mut self) -> SCS_W[src]
Bit 11 - Capture sychronize
pub fn ccis(&mut self) -> CCIS_W[src]
Bits 12:13 - Capture input select 1
pub fn cm(&mut self) -> CM_W[src]
Bits 14:15 - Capture mode 1
impl W<u16, Reg<u16, _TA1CCTL2>>[src]
pub fn ccifg(&mut self) -> CCIFG_W[src]
Bit 0 - Capture/compare interrupt flag
pub fn cov(&mut self) -> COV_W[src]
Bit 1 - Capture/compare overflow flag
pub fn out(&mut self) -> OUT_W[src]
Bit 2 - PWM Output signal if output mode 0
pub fn cci(&mut self) -> CCI_W[src]
Bit 3 - Capture input signal (read)
pub fn ccie(&mut self) -> CCIE_W[src]
Bit 4 - Capture/compare interrupt enable
pub fn outmod(&mut self) -> OUTMOD_W[src]
Bits 5:7 - Output mode 2
pub fn cap(&mut self) -> CAP_W[src]
Bit 8 - Capture mode: 1 /Compare mode : 0
pub fn scci(&mut self) -> SCCI_W[src]
Bit 10 - Latched capture signal (read)
pub fn scs(&mut self) -> SCS_W[src]
Bit 11 - Capture sychronize
pub fn ccis(&mut self) -> CCIS_W[src]
Bits 12:13 - Capture input select 1
pub fn cm(&mut self) -> CM_W[src]
Bits 14:15 - Capture mode 1
impl W<u16, Reg<u16, _TA1EX0>>[src]
impl W<u16, Reg<u16, _RTCCTL>>[src]
pub fn rtcif(&mut self) -> RTCIF_W[src]
Bit 0 - Low-Power-Counter Interrupt Flag
pub fn rtcie(&mut self) -> RTCIE_W[src]
Bit 1 - Low-Power-Counter Interrupt Enable
pub fn rtcsr(&mut self) -> RTCSR_W[src]
Bit 6 - Low-Power-Counter Software Reset
pub fn rtcps(&mut self) -> RTCPS_W[src]
Bits 8:10 - Low-Power-Counter Clock Pre-divider Select Bit: 0
pub fn rtcss(&mut self) -> RTCSS_W[src]
Bits 12:13 - Low-Power-Counter Clock Source Select Bit: 0
impl W<u16, Reg<u16, _LCDCTL0>>[src]
pub fn lcdon(&mut self) -> LCDON_W[src]
Bit 0 - LCD_E LCD On
pub fn lcdlp(&mut self) -> LCDLP_W[src]
Bit 1 - LCD_E Low Power Waveform
pub fn lcdson(&mut self) -> LCDSON_W[src]
Bit 2 - LCD_E LCD Segments On
pub fn lcdmx0(&mut self) -> LCDMX0_W[src]
Bit 3 - LCD_E Mux Rate Bit: 0
pub fn lcdmx1(&mut self) -> LCDMX1_W[src]
Bit 4 - LCD_E Mux Rate Bit: 1
pub fn lcdmx2(&mut self) -> LCDMX2_W[src]
Bit 5 - LCD_E Mux Rate Bit: 2
pub fn lcdssel(&mut self) -> LCDSSEL_W[src]
Bits 6:7 - LCD_E Clock Select Bit: 0
pub fn lcddiv(&mut self) -> LCDDIV_W[src]
Bits 11:15 - LCD_E LCD frequency divider Bit: 0
impl W<u16, Reg<u16, _LCDCTL1>>[src]
pub fn lcdfrmifg(&mut self) -> LCDFRMIFG_W[src]
Bit 0 - LCD_E LCD frame interrupt flag
pub fn lcdblkoffifg(&mut self) -> LCDBLKOFFIFG_W[src]
Bit 1 - LCD_E LCD blinking off interrupt flag
pub fn lcdblkonifg(&mut self) -> LCDBLKONIFG_W[src]
Bit 2 - LCD_E LCD blinking on interrupt flag
pub fn lcdfrmie(&mut self) -> LCDFRMIE_W[src]
Bit 8 - LCD_E LCD frame interrupt enable
pub fn lcdblkoffie(&mut self) -> LCDBLKOFFIE_W[src]
Bit 9 - LCD_E LCD blinking off interrupt flag
pub fn lcdblkonie(&mut self) -> LCDBLKONIE_W[src]
Bit 10 - LCD_E LCD blinking on interrupt flag
impl W<u16, Reg<u16, _LCDBLKCTL>>[src]
pub fn lcdblkmod(&mut self) -> LCDBLKMOD_W[src]
Bits 0:1 - LCD_E Blinking mode Bit: 0
pub fn lcdblkpre(&mut self) -> LCDBLKPRE_W[src]
Bits 2:4 - LCD_E Clock pre-scaler for blinking frequency Bit: 0
impl W<u16, Reg<u16, _LCDMEMCTL>>[src]
pub fn lcddisp(&mut self) -> LCDDISP_W[src]
Bit 0 - LCD_E LCD memory registers for display
pub fn lcdclrm(&mut self) -> LCDCLRM_W[src]
Bit 1 - LCD_E Clear LCD memory
pub fn lcdclrbm(&mut self) -> LCDCLRBM_W[src]
Bit 2 - LCD_E Clear LCD blinking memory
impl W<u16, Reg<u16, _LCDVCTL>>[src]
pub fn lcdrefmode(&mut self) -> LCDREFMODE_W[src]
Bit 0 - Selects wether R13 voltage is switched or in static mode
pub fn lcdselvdd(&mut self) -> LCDSELVDD_W[src]
Bit 5 - selects if R33 is supplied either from Vcc internally or from charge pump
pub fn lcdrefen(&mut self) -> LCDREFEN_W[src]
Bit 6 - Internal reference voltage enable on R13
pub fn lcdcpen(&mut self) -> LCDCPEN_W[src]
Bit 7 - Charge pump enable
pub fn vlcd(&mut self) -> VLCD_W[src]
Bits 8:11 - VLCD select: 0
pub fn lcdcpfsel0(&mut self) -> LCDCPFSEL0_W[src]
Bit 12 - Charge pump frequency selection Bit: 0
pub fn lcdcpfsel1(&mut self) -> LCDCPFSEL1_W[src]
Bit 13 - Charge pump frequency selection Bit: 1
pub fn lcdcpfsel2(&mut self) -> LCDCPFSEL2_W[src]
Bit 14 - Charge pump frequency selection Bit: 2
pub fn lcdcpfsel3(&mut self) -> LCDCPFSEL3_W[src]
Bit 15 - Charge pump frequency selection Bit: 3
impl W<u16, Reg<u16, _LCDPCTL0>>[src]
pub fn lcds0(&mut self) -> LCDS0_W[src]
Bit 0 - LCD Segment 0 enable.
pub fn lcds1(&mut self) -> LCDS1_W[src]
Bit 1 - LCD Segment 1 enable.
pub fn lcds2(&mut self) -> LCDS2_W[src]
Bit 2 - LCD Segment 2 enable.
pub fn lcds3(&mut self) -> LCDS3_W[src]
Bit 3 - LCD Segment 3 enable.
pub fn lcds4(&mut self) -> LCDS4_W[src]
Bit 4 - LCD Segment 4 enable.
pub fn lcds5(&mut self) -> LCDS5_W[src]
Bit 5 - LCD Segment 5 enable.
pub fn lcds6(&mut self) -> LCDS6_W[src]
Bit 6 - LCD Segment 6 enable.
pub fn lcds7(&mut self) -> LCDS7_W[src]
Bit 7 - LCD Segment 7 enable.
pub fn lcds8(&mut self) -> LCDS8_W[src]
Bit 8 - LCD Segment 8 enable.
pub fn lcds9(&mut self) -> LCDS9_W[src]
Bit 9 - LCD Segment 9 enable.
pub fn lcds10(&mut self) -> LCDS10_W[src]
Bit 10 - LCD Segment 10 enable.
pub fn lcds11(&mut self) -> LCDS11_W[src]
Bit 11 - LCD Segment 11 enable.
pub fn lcds12(&mut self) -> LCDS12_W[src]
Bit 12 - LCD Segment 12 enable.
pub fn lcds13(&mut self) -> LCDS13_W[src]
Bit 13 - LCD Segment 13 enable.
pub fn lcds14(&mut self) -> LCDS14_W[src]
Bit 14 - LCD Segment 14 enable.
pub fn lcds15(&mut self) -> LCDS15_W[src]
Bit 15 - LCD Segment 15 enable.
impl W<u16, Reg<u16, _LCDPCTL1>>[src]
pub fn lcds16(&mut self) -> LCDS16_W[src]
Bit 0 - LCD Segment 16 enable.
pub fn lcds17(&mut self) -> LCDS17_W[src]
Bit 1 - LCD Segment 17 enable.
pub fn lcds18(&mut self) -> LCDS18_W[src]
Bit 2 - LCD Segment 18 enable.
pub fn lcds19(&mut self) -> LCDS19_W[src]
Bit 3 - LCD Segment 19 enable.
pub fn lcds20(&mut self) -> LCDS20_W[src]
Bit 4 - LCD Segment 20 enable.
pub fn lcds21(&mut self) -> LCDS21_W[src]
Bit 5 - LCD Segment 21 enable.
pub fn lcds22(&mut self) -> LCDS22_W[src]
Bit 6 - LCD Segment 22 enable.
pub fn lcds23(&mut self) -> LCDS23_W[src]
Bit 7 - LCD Segment 23 enable.
pub fn lcds24(&mut self) -> LCDS24_W[src]
Bit 8 - LCD Segment 24 enable.
pub fn lcds25(&mut self) -> LCDS25_W[src]
Bit 9 - LCD Segment 25 enable.
pub fn lcds26(&mut self) -> LCDS26_W[src]
Bit 10 - LCD Segment 26 enable.
pub fn lcds27(&mut self) -> LCDS27_W[src]
Bit 11 - LCD Segment 27 enable.
pub fn lcds28(&mut self) -> LCDS28_W[src]
Bit 12 - LCD Segment 28 enable.
pub fn lcds29(&mut self) -> LCDS29_W[src]
Bit 13 - LCD Segment 29 enable.
pub fn lcds30(&mut self) -> LCDS30_W[src]
Bit 14 - LCD Segment 30 enable.
pub fn lcds31(&mut self) -> LCDS31_W[src]
Bit 15 - LCD Segment 31 enable.
impl W<u16, Reg<u16, _LCDPCTL2>>[src]
pub fn lcds32(&mut self) -> LCDS32_W[src]
Bit 0 - LCD Segment 32 enable.
pub fn lcds33(&mut self) -> LCDS33_W[src]
Bit 1 - LCD Segment 33 enable.
pub fn lcds34(&mut self) -> LCDS34_W[src]
Bit 2 - LCD Segment 34 enable.
pub fn lcds35(&mut self) -> LCDS35_W[src]
Bit 3 - LCD Segment 35 enable.
pub fn lcds36(&mut self) -> LCDS36_W[src]
Bit 4 - LCD Segment 36 enable.
pub fn lcds37(&mut self) -> LCDS37_W[src]
Bit 5 - LCD Segment 37 enable.
pub fn lcds38(&mut self) -> LCDS38_W[src]
Bit 6 - LCD Segment 38 enable.
pub fn lcds39(&mut self) -> LCDS39_W[src]
Bit 7 - LCD Segment 39 enable.
pub fn lcds40(&mut self) -> LCDS40_W[src]
Bit 8 - LCD Segment 40 enable.
pub fn lcds41(&mut self) -> LCDS41_W[src]
Bit 9 - LCD Segment 41 enable.
pub fn lcds42(&mut self) -> LCDS42_W[src]
Bit 10 - LCD Segment 42 enable.
pub fn lcds43(&mut self) -> LCDS43_W[src]
Bit 11 - LCD Segment 43 enable.
pub fn lcds44(&mut self) -> LCDS44_W[src]
Bit 12 - LCD Segment 44 enable.
pub fn lcds45(&mut self) -> LCDS45_W[src]
Bit 13 - LCD Segment 45 enable.
pub fn lcds46(&mut self) -> LCDS46_W[src]
Bit 14 - LCD Segment 46 enable.
pub fn lcds47(&mut self) -> LCDS47_W[src]
Bit 15 - LCD Segment 47 enable.
impl W<u16, Reg<u16, _LCDCSSEL0>>[src]
pub fn lcdcss0(&mut self) -> LCDCSS0_W[src]
Bit 0 - Selects pin L0 as either common or segment line
pub fn lcdcss1(&mut self) -> LCDCSS1_W[src]
Bit 1 - Selects pin L1 as either common or segment line
pub fn lcdcss2(&mut self) -> LCDCSS2_W[src]
Bit 2 - Selects pin L2 as either common or segment line
pub fn lcdcss3(&mut self) -> LCDCSS3_W[src]
Bit 3 - Selects pin L3 as either common or segment line
pub fn lcdcss4(&mut self) -> LCDCSS4_W[src]
Bit 4 - Selects pin L4 as either common or segment line
pub fn lcdcss5(&mut self) -> LCDCSS5_W[src]
Bit 5 - Selects pin L5 as either common or segment line
pub fn lcdcss6(&mut self) -> LCDCSS6_W[src]
Bit 6 - Selects pin L6 as either common or segment line
pub fn lcdcss7(&mut self) -> LCDCSS7_W[src]
Bit 7 - Selects pin L7 as either common or segment line
pub fn lcdcss8(&mut self) -> LCDCSS8_W[src]
Bit 8 - Selects pin L8 as either common or segment line
pub fn lcdcss9(&mut self) -> LCDCSS9_W[src]
Bit 9 - Selects pin L9 as either common or segment line
pub fn lcdcss10(&mut self) -> LCDCSS10_W[src]
Bit 10 - Selects pin L10 as either common or segment line
pub fn lcdcss11(&mut self) -> LCDCSS11_W[src]
Bit 11 - Selects pin L11 as either common or segment line
pub fn lcdcss12(&mut self) -> LCDCSS12_W[src]
Bit 12 - Selects pin L12 as either common or segment line
pub fn lcdcss13(&mut self) -> LCDCSS13_W[src]
Bit 13 - Selects pin L13 as either common or segment line
pub fn lcdcss14(&mut self) -> LCDCSS14_W[src]
Bit 14 - Selects pin L14 as either common or segment line
pub fn lcdcss15(&mut self) -> LCDCSS15_W[src]
Bit 15 - Selects pin L15 as either common or segment line
impl W<u16, Reg<u16, _LCDCSSEL1>>[src]
pub fn lcdcss16(&mut self) -> LCDCSS16_W[src]
Bit 0 - Selects pin L16 as either common or segment line
pub fn lcdcss17(&mut self) -> LCDCSS17_W[src]
Bit 1 - Selects pin L17 as either common or segment line
pub fn lcdcss18(&mut self) -> LCDCSS18_W[src]
Bit 2 - Selects pin L18 as either common or segment line
pub fn lcdcss19(&mut self) -> LCDCSS19_W[src]
Bit 3 - Selects pin L19 as either common or segment line
pub fn lcdcss20(&mut self) -> LCDCSS20_W[src]
Bit 4 - Selects pin L20 as either common or segment line
pub fn lcdcss21(&mut self) -> LCDCSS21_W[src]
Bit 5 - Selects pin L21 as either common or segment line
pub fn lcdcss22(&mut self) -> LCDCSS22_W[src]
Bit 6 - Selects pin L22 as either common or segment line
pub fn lcdcss23(&mut self) -> LCDCSS23_W[src]
Bit 7 - Selects pin L23 as either common or segment line
pub fn lcdcss24(&mut self) -> LCDCSS24_W[src]
Bit 8 - Selects pin L24 as either common or segment line
pub fn lcdcss25(&mut self) -> LCDCSS25_W[src]
Bit 9 - Selects pin L25 as either common or segment line
pub fn lcdcss26(&mut self) -> LCDCSS26_W[src]
Bit 10 - Selects pin L26 as either common or segment line
pub fn lcdcss27(&mut self) -> LCDCSS27_W[src]
Bit 11 - Selects pin L27 as either common or segment line
pub fn lcdcss28(&mut self) -> LCDCSS28_W[src]
Bit 12 - Selects pin L28 as either common or segment line
pub fn lcdcss29(&mut self) -> LCDCSS29_W[src]
Bit 13 - Selects pin L29 as either common or segment line
pub fn lcdcss30(&mut self) -> LCDCSS30_W[src]
Bit 14 - Selects pin L30 as either common or segment line
pub fn lcdcss31(&mut self) -> LCDCSS31_W[src]
Bit 15 - Selects pin L31 as either common or segment line
impl W<u16, Reg<u16, _LCDCSSEL2>>[src]
pub fn lcdcss32(&mut self) -> LCDCSS32_W[src]
Bit 0 - Selects pin L32 as either common or segment line
pub fn lcdcss33(&mut self) -> LCDCSS33_W[src]
Bit 1 - Selects pin L33 as either common or segment line
pub fn lcdcss34(&mut self) -> LCDCSS34_W[src]
Bit 2 - Selects pin L34 as either common or segment line
pub fn lcdcss35(&mut self) -> LCDCSS35_W[src]
Bit 3 - Selects pin L35 as either common or segment line
pub fn lcdcss36(&mut self) -> LCDCSS36_W[src]
Bit 4 - Selects pin L36 as either common or segment line
pub fn lcdcss37(&mut self) -> LCDCSS37_W[src]
Bit 5 - Selects pin L37 as either common or segment line
pub fn lcdcss38(&mut self) -> LCDCSS38_W[src]
Bit 6 - Selects pin L38 as either common or segment line
pub fn lcdcss39(&mut self) -> LCDCSS39_W[src]
Bit 7 - Selects pin L39 as either common or segment line
pub fn lcdcss40(&mut self) -> LCDCSS40_W[src]
Bit 8 - Selects pin L40 as either common or segment line
pub fn lcdcss41(&mut self) -> LCDCSS41_W[src]
Bit 9 - Selects pin L41 as either common or segment line
pub fn lcdcss42(&mut self) -> LCDCSS42_W[src]
Bit 10 - Selects pin L42 as either common or segment line
pub fn lcdcss43(&mut self) -> LCDCSS43_W[src]
Bit 11 - Selects pin L43 as either common or segment line
pub fn lcdcss44(&mut self) -> LCDCSS44_W[src]
Bit 12 - Selects pin L44 as either common or segment line
pub fn lcdcss45(&mut self) -> LCDCSS45_W[src]
Bit 13 - Selects pin L45 as either common or segment line
pub fn lcdcss46(&mut self) -> LCDCSS46_W[src]
Bit 14 - Selects pin L46 as either common or segment line
pub fn lcdcss47(&mut self) -> LCDCSS47_W[src]
Bit 15 - Selects pin L47 as either common or segment line
impl W<u16, Reg<u16, _ADCCTL0>>[src]
pub fn adcsc(&mut self) -> ADCSC_W[src]
Bit 0 - ADC Start Conversion
pub fn adcenc(&mut self) -> ADCENC_W[src]
Bit 1 - ADC Enable Conversion
pub fn adcon(&mut self) -> ADCON_W[src]
Bit 4 - ADC On/enable
pub fn adcmsc(&mut self) -> ADCMSC_W[src]
Bit 7 - ADC Multiple SampleConversion
pub fn adcsht(&mut self) -> ADCSHT_W[src]
Bits 8:11 - ADC Sample Hold Select Bit: 0
impl W<u16, Reg<u16, _ADCCTL1>>[src]
pub fn adcbusy(&mut self) -> ADCBUSY_W[src]
Bit 0 - ADC Busy
pub fn adcconseq(&mut self) -> ADCCONSEQ_W[src]
Bits 1:2 - ADC Conversion Sequence Select 0
pub fn adcssel(&mut self) -> ADCSSEL_W[src]
Bits 3:4 - ADC Clock Source Select 0
pub fn adcdiv(&mut self) -> ADCDIV_W[src]
Bits 5:7 - ADC Clock Divider Select 0
pub fn adcissh(&mut self) -> ADCISSH_W[src]
Bit 8 - ADC Invert Sample Hold Signal
pub fn adcshp(&mut self) -> ADCSHP_W[src]
Bit 9 - ADC Sample/Hold Pulse Mode
pub fn adcshs(&mut self) -> ADCSHS_W[src]
Bits 10:11 - ADC Sample/Hold Source 0
impl W<u16, Reg<u16, _ADCCTL2>>[src]
pub fn adcsr(&mut self) -> ADCSR_W[src]
Bit 2 - ADC Sampling Rate
pub fn adcdf(&mut self) -> ADCDF_W[src]
Bit 3 - ADC Data Format
pub fn adcres(&mut self) -> ADCRES_W[src]
Bits 4:5 - ADC Resolution
pub fn adcpdiv(&mut self) -> ADCPDIV_W[src]
Bits 8:9 - ADC predivider Bit: 0
impl W<u16, Reg<u16, _ADCMCTL0>>[src]
pub fn adcinch(&mut self) -> ADCINCH_W[src]
Bits 0:3 - ADC Input Channel Select Bit 0
pub fn adcsref(&mut self) -> ADCSREF_W[src]
Bits 4:6 - ADC Select Reference Bit 0
impl W<u16, Reg<u16, _ADCIE>>[src]
pub fn adcie0(&mut self) -> ADCIE0_W[src]
Bit 0 - ADC Interrupt enable
pub fn adcinie(&mut self) -> ADCINIE_W[src]
Bit 1 - ADC Interrupt enable for the inside of window of the Window comparator
pub fn adcloie(&mut self) -> ADCLOIE_W[src]
Bit 2 - ADC Interrupt enable for lower threshold of the Window comparator
pub fn adchiie(&mut self) -> ADCHIIE_W[src]
Bit 3 - ADC Interrupt enable for upper threshold of the Window comparator
pub fn adcovie(&mut self) -> ADCOVIE_W[src]
Bit 4 - ADC ADCMEM overflow Interrupt enable
pub fn adctovie(&mut self) -> ADCTOVIE_W[src]
Bit 5 - ADC conversion-time-overflow Interrupt enable
impl W<u16, Reg<u16, _ADCIFG>>[src]
pub fn adcifg0(&mut self) -> ADCIFG0_W[src]
Bit 0 - ADC Interrupt Flag
pub fn adcinifg(&mut self) -> ADCINIFG_W[src]
Bit 1 - ADC Interrupt Flag for the inside of window of the Window comparator
pub fn adcloifg(&mut self) -> ADCLOIFG_W[src]
Bit 2 - ADC Interrupt Flag for lower threshold of the Window comparator
pub fn adchiifg(&mut self) -> ADCHIIFG_W[src]
Bit 3 - ADC Interrupt Flag for upper threshold of the Window comparator
pub fn adcovifg(&mut self) -> ADCOVIFG_W[src]
Bit 4 - ADC ADCMEM overflow Interrupt Flag
pub fn adctovifg(&mut self) -> ADCTOVIFG_W[src]
Bit 5 - ADC conversion-time-overflow Interrupt Flag
Auto Trait Implementations
impl<U, REG> Send for W<U, REG> where
REG: Send,
U: Send,
REG: Send,
U: Send,
impl<U, REG> Sync for W<U, REG> where
REG: Sync,
U: Sync,
REG: Sync,
U: Sync,
impl<U, REG> Unpin for W<U, REG> where
REG: Unpin,
U: Unpin,
REG: Unpin,
U: Unpin,
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized, [src]
T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized, [src]
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized, [src]
T: ?Sized,
fn borrow_mut(&mut self) -> &mut T[src]
impl<T> From<T> for T[src]
impl<T, U> Into<U> for T where
U: From<T>, [src]
U: From<T>,
impl<T, U> TryFrom<U> for T where
U: Into<T>, [src]
U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>[src]
impl<T, U> TryInto<U> for T where
U: TryFrom<T>, [src]
U: TryFrom<T>,