msp430fr2355/sys/
sysrstiv.rs1#[doc = "Register `SYSRSTIV` reader"]
2pub type R = crate::R<SysrstivSpec>;
3#[doc = "Register `SYSRSTIV` writer"]
4pub type W = crate::W<SysrstivSpec>;
5#[doc = "Reset interrupt vector\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u16)]
8pub enum Sysrstiv {
9 #[doc = "0: No interrupt pending"]
10 None = 0,
11 #[doc = "2: Brownout"]
12 Bor = 2,
13 #[doc = "4: RSTIFG RST/NMI"]
14 Rstnmi = 4,
15 #[doc = "6: PMMSWBOR software BOR"]
16 Pmmswbor = 6,
17 #[doc = "8: LPMx.5 wakeup"]
18 Lpm5wu = 8,
19 #[doc = "10: Security violation"]
20 Secyv = 10,
21 #[doc = "12: Reserved"]
22 Sysrstiv12 = 12,
23 #[doc = "14: SVSHIFG SVSH event"]
24 Svshifg = 14,
25 #[doc = "16: Reserved"]
26 Sysrstiv16 = 16,
27 #[doc = "18: Reserved"]
28 Sysrstiv18 = 18,
29 #[doc = "20: PMMSWPOR software POR"]
30 Pmmswpor = 20,
31 #[doc = "22: WDTIFG watchdog timeout"]
32 Wdtifg = 22,
33 #[doc = "24: WDTPW watchdog password violation"]
34 Wdtpw = 24,
35 #[doc = "26: FRCTLPW password violation"]
36 Frctlpw = 26,
37 #[doc = "28: Uncorrectable FRAM bit error detection"]
38 Ubdifg = 28,
39 #[doc = "30: Peripheral area fetch"]
40 Perf = 30,
41 #[doc = "32: PMM password violation"]
42 Pmmpw = 32,
43 #[doc = "34: Reserved"]
44 Sysrstiv34 = 34,
45 #[doc = "36: FLL unlock (PUC)"]
46 Fllul = 36,
47}
48impl From<Sysrstiv> for u16 {
49 #[inline(always)]
50 fn from(variant: Sysrstiv) -> Self {
51 variant as _
52 }
53}
54impl crate::FieldSpec for Sysrstiv {
55 type Ux = u16;
56}
57impl crate::IsEnum for Sysrstiv {}
58#[doc = "Field `SYSRSTIV` reader - Reset interrupt vector"]
59pub type SysrstivR = crate::FieldReader<Sysrstiv>;
60impl SysrstivR {
61 #[doc = "Get enumerated values variant"]
62 #[inline(always)]
63 pub const fn variant(&self) -> Option<Sysrstiv> {
64 match self.bits {
65 0 => Some(Sysrstiv::None),
66 2 => Some(Sysrstiv::Bor),
67 4 => Some(Sysrstiv::Rstnmi),
68 6 => Some(Sysrstiv::Pmmswbor),
69 8 => Some(Sysrstiv::Lpm5wu),
70 10 => Some(Sysrstiv::Secyv),
71 12 => Some(Sysrstiv::Sysrstiv12),
72 14 => Some(Sysrstiv::Svshifg),
73 16 => Some(Sysrstiv::Sysrstiv16),
74 18 => Some(Sysrstiv::Sysrstiv18),
75 20 => Some(Sysrstiv::Pmmswpor),
76 22 => Some(Sysrstiv::Wdtifg),
77 24 => Some(Sysrstiv::Wdtpw),
78 26 => Some(Sysrstiv::Frctlpw),
79 28 => Some(Sysrstiv::Ubdifg),
80 30 => Some(Sysrstiv::Perf),
81 32 => Some(Sysrstiv::Pmmpw),
82 34 => Some(Sysrstiv::Sysrstiv34),
83 36 => Some(Sysrstiv::Fllul),
84 _ => None,
85 }
86 }
87 #[doc = "No interrupt pending"]
88 #[inline(always)]
89 pub fn is_none(&self) -> bool {
90 *self == Sysrstiv::None
91 }
92 #[doc = "Brownout"]
93 #[inline(always)]
94 pub fn is_bor(&self) -> bool {
95 *self == Sysrstiv::Bor
96 }
97 #[doc = "RSTIFG RST/NMI"]
98 #[inline(always)]
99 pub fn is_rstnmi(&self) -> bool {
100 *self == Sysrstiv::Rstnmi
101 }
102 #[doc = "PMMSWBOR software BOR"]
103 #[inline(always)]
104 pub fn is_pmmswbor(&self) -> bool {
105 *self == Sysrstiv::Pmmswbor
106 }
107 #[doc = "LPMx.5 wakeup"]
108 #[inline(always)]
109 pub fn is_lpm5wu(&self) -> bool {
110 *self == Sysrstiv::Lpm5wu
111 }
112 #[doc = "Security violation"]
113 #[inline(always)]
114 pub fn is_secyv(&self) -> bool {
115 *self == Sysrstiv::Secyv
116 }
117 #[doc = "Reserved"]
118 #[inline(always)]
119 pub fn is_sysrstiv_12(&self) -> bool {
120 *self == Sysrstiv::Sysrstiv12
121 }
122 #[doc = "SVSHIFG SVSH event"]
123 #[inline(always)]
124 pub fn is_svshifg(&self) -> bool {
125 *self == Sysrstiv::Svshifg
126 }
127 #[doc = "Reserved"]
128 #[inline(always)]
129 pub fn is_sysrstiv_16(&self) -> bool {
130 *self == Sysrstiv::Sysrstiv16
131 }
132 #[doc = "Reserved"]
133 #[inline(always)]
134 pub fn is_sysrstiv_18(&self) -> bool {
135 *self == Sysrstiv::Sysrstiv18
136 }
137 #[doc = "PMMSWPOR software POR"]
138 #[inline(always)]
139 pub fn is_pmmswpor(&self) -> bool {
140 *self == Sysrstiv::Pmmswpor
141 }
142 #[doc = "WDTIFG watchdog timeout"]
143 #[inline(always)]
144 pub fn is_wdtifg(&self) -> bool {
145 *self == Sysrstiv::Wdtifg
146 }
147 #[doc = "WDTPW watchdog password violation"]
148 #[inline(always)]
149 pub fn is_wdtpw(&self) -> bool {
150 *self == Sysrstiv::Wdtpw
151 }
152 #[doc = "FRCTLPW password violation"]
153 #[inline(always)]
154 pub fn is_frctlpw(&self) -> bool {
155 *self == Sysrstiv::Frctlpw
156 }
157 #[doc = "Uncorrectable FRAM bit error detection"]
158 #[inline(always)]
159 pub fn is_ubdifg(&self) -> bool {
160 *self == Sysrstiv::Ubdifg
161 }
162 #[doc = "Peripheral area fetch"]
163 #[inline(always)]
164 pub fn is_perf(&self) -> bool {
165 *self == Sysrstiv::Perf
166 }
167 #[doc = "PMM password violation"]
168 #[inline(always)]
169 pub fn is_pmmpw(&self) -> bool {
170 *self == Sysrstiv::Pmmpw
171 }
172 #[doc = "Reserved"]
173 #[inline(always)]
174 pub fn is_sysrstiv_34(&self) -> bool {
175 *self == Sysrstiv::Sysrstiv34
176 }
177 #[doc = "FLL unlock (PUC)"]
178 #[inline(always)]
179 pub fn is_fllul(&self) -> bool {
180 *self == Sysrstiv::Fllul
181 }
182}
183impl R {
184 #[doc = "Bits 0:15 - Reset interrupt vector"]
185 #[inline(always)]
186 pub fn sysrstiv(&self) -> SysrstivR {
187 SysrstivR::new(self.bits)
188 }
189}
190impl W {}
191#[doc = "Reset Vector Generator\n\nYou can [`read`](crate::Reg::read) this register and get [`sysrstiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysrstiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
192pub struct SysrstivSpec;
193impl crate::RegisterSpec for SysrstivSpec {
194 type Ux = u16;
195}
196#[doc = "`read()` method returns [`sysrstiv::R`](R) reader structure"]
197impl crate::Readable for SysrstivSpec {}
198#[doc = "`write(|w| ..)` method takes [`sysrstiv::W`](W) writer structure"]
199impl crate::Writable for SysrstivSpec {
200 type Safety = crate::Unsafe;
201}
202#[doc = "`reset()` method sets SYSRSTIV to value 0"]
203impl crate::Resettable for SysrstivSpec {}