msp430fr2355/cs/
csctl2.rs1#[doc = "Register `CSCTL2` reader"]
2pub struct R(crate::R<CSCTL2_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CSCTL2_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CSCTL2_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CSCTL2_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CSCTL2` writer"]
17pub struct W(crate::W<CSCTL2_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CSCTL2_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CSCTL2_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CSCTL2_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `FLLN` reader - Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to FLLN causes N to be set to 1."]
38pub type FLLN_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `FLLN` writer - Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to FLLN causes N to be set to 1."]
40pub type FLLN_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CSCTL2_SPEC, u16, u16, 10, O>;
41#[doc = "Field `FLLD` reader - FLL loop divider. These bits divide f(DCOCLK) in the FLL feedback loop. This results in an additional multiplier for the multiplier bits. See also multiplier bits."]
42pub type FLLD_R = crate::FieldReader<u8, FLLD_A>;
43#[doc = "FLL loop divider. These bits divide f(DCOCLK) in the FLL feedback loop. This results in an additional multiplier for the multiplier bits. See also multiplier bits.\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum FLLD_A {
47 #[doc = "0: fDCOCLK / 1"]
48 _1 = 0,
49 #[doc = "1: fDCOCLK / 2"]
50 _2 = 1,
51 #[doc = "2: fDCOCLK / 4"]
52 _4 = 2,
53 #[doc = "3: fDCOCLK / 8"]
54 _8 = 3,
55 #[doc = "4: fDCOCLK / 16"]
56 _16 = 4,
57 #[doc = "5: fDCOCLK / 32"]
58 _32 = 5,
59 #[doc = "6: fDCOCLK / 40(Only avaliable in 24MHz clock system)"]
60 FLLD_6 = 6,
61 #[doc = "7: fDCOCLK / 48(Only avaliable in 24MHz clock system)"]
62 FLLD_7 = 7,
63}
64impl From<FLLD_A> for u8 {
65 #[inline(always)]
66 fn from(variant: FLLD_A) -> Self {
67 variant as _
68 }
69}
70impl FLLD_R {
71 #[doc = "Get enumerated values variant"]
72 #[inline(always)]
73 pub fn variant(&self) -> FLLD_A {
74 match self.bits {
75 0 => FLLD_A::_1,
76 1 => FLLD_A::_2,
77 2 => FLLD_A::_4,
78 3 => FLLD_A::_8,
79 4 => FLLD_A::_16,
80 5 => FLLD_A::_32,
81 6 => FLLD_A::FLLD_6,
82 7 => FLLD_A::FLLD_7,
83 _ => unreachable!(),
84 }
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline(always)]
88 pub fn is_1(&self) -> bool {
89 *self == FLLD_A::_1
90 }
91 #[doc = "Checks if the value of the field is `_2`"]
92 #[inline(always)]
93 pub fn is_2(&self) -> bool {
94 *self == FLLD_A::_2
95 }
96 #[doc = "Checks if the value of the field is `_4`"]
97 #[inline(always)]
98 pub fn is_4(&self) -> bool {
99 *self == FLLD_A::_4
100 }
101 #[doc = "Checks if the value of the field is `_8`"]
102 #[inline(always)]
103 pub fn is_8(&self) -> bool {
104 *self == FLLD_A::_8
105 }
106 #[doc = "Checks if the value of the field is `_16`"]
107 #[inline(always)]
108 pub fn is_16(&self) -> bool {
109 *self == FLLD_A::_16
110 }
111 #[doc = "Checks if the value of the field is `_32`"]
112 #[inline(always)]
113 pub fn is_32(&self) -> bool {
114 *self == FLLD_A::_32
115 }
116 #[doc = "Checks if the value of the field is `FLLD_6`"]
117 #[inline(always)]
118 pub fn is_flld_6(&self) -> bool {
119 *self == FLLD_A::FLLD_6
120 }
121 #[doc = "Checks if the value of the field is `FLLD_7`"]
122 #[inline(always)]
123 pub fn is_flld_7(&self) -> bool {
124 *self == FLLD_A::FLLD_7
125 }
126}
127#[doc = "Field `FLLD` writer - FLL loop divider. These bits divide f(DCOCLK) in the FLL feedback loop. This results in an additional multiplier for the multiplier bits. See also multiplier bits."]
128pub type FLLD_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u16, CSCTL2_SPEC, u8, FLLD_A, 3, O>;
129impl<'a, const O: u8> FLLD_W<'a, O> {
130 #[doc = "fDCOCLK / 1"]
131 #[inline(always)]
132 pub fn _1(self) -> &'a mut W {
133 self.variant(FLLD_A::_1)
134 }
135 #[doc = "fDCOCLK / 2"]
136 #[inline(always)]
137 pub fn _2(self) -> &'a mut W {
138 self.variant(FLLD_A::_2)
139 }
140 #[doc = "fDCOCLK / 4"]
141 #[inline(always)]
142 pub fn _4(self) -> &'a mut W {
143 self.variant(FLLD_A::_4)
144 }
145 #[doc = "fDCOCLK / 8"]
146 #[inline(always)]
147 pub fn _8(self) -> &'a mut W {
148 self.variant(FLLD_A::_8)
149 }
150 #[doc = "fDCOCLK / 16"]
151 #[inline(always)]
152 pub fn _16(self) -> &'a mut W {
153 self.variant(FLLD_A::_16)
154 }
155 #[doc = "fDCOCLK / 32"]
156 #[inline(always)]
157 pub fn _32(self) -> &'a mut W {
158 self.variant(FLLD_A::_32)
159 }
160 #[doc = "fDCOCLK / 40(Only avaliable in 24MHz clock system)"]
161 #[inline(always)]
162 pub fn flld_6(self) -> &'a mut W {
163 self.variant(FLLD_A::FLLD_6)
164 }
165 #[doc = "fDCOCLK / 48(Only avaliable in 24MHz clock system)"]
166 #[inline(always)]
167 pub fn flld_7(self) -> &'a mut W {
168 self.variant(FLLD_A::FLLD_7)
169 }
170}
171impl R {
172 #[doc = "Bits 0:9 - Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to FLLN causes N to be set to 1."]
173 #[inline(always)]
174 pub fn flln(&self) -> FLLN_R {
175 FLLN_R::new((self.bits & 0x03ff) as u16)
176 }
177 #[doc = "Bits 12:14 - FLL loop divider. These bits divide f(DCOCLK) in the FLL feedback loop. This results in an additional multiplier for the multiplier bits. See also multiplier bits."]
178 #[inline(always)]
179 pub fn flld(&self) -> FLLD_R {
180 FLLD_R::new(((self.bits >> 12) & 7) as u8)
181 }
182}
183impl W {
184 #[doc = "Bits 0:9 - Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to FLLN causes N to be set to 1."]
185 #[inline(always)]
186 pub fn flln(&mut self) -> FLLN_W<0> {
187 FLLN_W::new(self)
188 }
189 #[doc = "Bits 12:14 - FLL loop divider. These bits divide f(DCOCLK) in the FLL feedback loop. This results in an additional multiplier for the multiplier bits. See also multiplier bits."]
190 #[inline(always)]
191 pub fn flld(&mut self) -> FLLD_W<12> {
192 FLLD_W::new(self)
193 }
194 #[doc = "Writes raw bits to the register."]
195 #[inline(always)]
196 pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
197 self.0.bits(bits);
198 self
199 }
200}
201#[doc = "Clock System Control 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csctl2](index.html) module"]
202pub struct CSCTL2_SPEC;
203impl crate::RegisterSpec for CSCTL2_SPEC {
204 type Ux = u16;
205}
206#[doc = "`read()` method returns [csctl2::R](R) reader structure"]
207impl crate::Readable for CSCTL2_SPEC {
208 type Reader = R;
209}
210#[doc = "`write(|w| ..)` method takes [csctl2::W](W) writer structure"]
211impl crate::Writable for CSCTL2_SPEC {
212 type Writer = W;
213}
214#[doc = "`reset()` method sets CSCTL2 to value 0"]
215impl crate::Resettable for CSCTL2_SPEC {
216 #[inline(always)]
217 fn reset_value() -> Self::Ux {
218 0
219 }
220}