msp430fr2355/cs/
csctl8.rs

1#[doc = "Register `CSCTL8` reader"]
2pub struct R(crate::R<CSCTL8_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CSCTL8_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CSCTL8_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CSCTL8_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CSCTL8` writer"]
17pub struct W(crate::W<CSCTL8_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CSCTL8_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CSCTL8_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CSCTL8_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ACLKREQEN` reader - ACLK clock request enable. Setting this enables conditional module requests for ACLK"]
38pub type ACLKREQEN_R = crate::BitReader<ACLKREQEN_A>;
39#[doc = "ACLK clock request enable. Setting this enables conditional module requests for ACLK\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum ACLKREQEN_A {
42    #[doc = "0: ACLK conditional requests are disabled."]
43    ACLKREQEN_0 = 0,
44    #[doc = "1: ACLK conditional requests are enabled."]
45    ACLKREQEN_1 = 1,
46}
47impl From<ACLKREQEN_A> for bool {
48    #[inline(always)]
49    fn from(variant: ACLKREQEN_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl ACLKREQEN_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> ACLKREQEN_A {
57        match self.bits {
58            false => ACLKREQEN_A::ACLKREQEN_0,
59            true => ACLKREQEN_A::ACLKREQEN_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `ACLKREQEN_0`"]
63    #[inline(always)]
64    pub fn is_aclkreqen_0(&self) -> bool {
65        *self == ACLKREQEN_A::ACLKREQEN_0
66    }
67    #[doc = "Checks if the value of the field is `ACLKREQEN_1`"]
68    #[inline(always)]
69    pub fn is_aclkreqen_1(&self) -> bool {
70        *self == ACLKREQEN_A::ACLKREQEN_1
71    }
72}
73#[doc = "Field `ACLKREQEN` writer - ACLK clock request enable. Setting this enables conditional module requests for ACLK"]
74pub type ACLKREQEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CSCTL8_SPEC, ACLKREQEN_A, O>;
75impl<'a, const O: u8> ACLKREQEN_W<'a, O> {
76    #[doc = "ACLK conditional requests are disabled."]
77    #[inline(always)]
78    pub fn aclkreqen_0(self) -> &'a mut W {
79        self.variant(ACLKREQEN_A::ACLKREQEN_0)
80    }
81    #[doc = "ACLK conditional requests are enabled."]
82    #[inline(always)]
83    pub fn aclkreqen_1(self) -> &'a mut W {
84        self.variant(ACLKREQEN_A::ACLKREQEN_1)
85    }
86}
87#[doc = "Field `MCLKREQEN` reader - MCLK clock request enable. Setting this enables conditional module requests for MCLK"]
88pub type MCLKREQEN_R = crate::BitReader<MCLKREQEN_A>;
89#[doc = "MCLK clock request enable. Setting this enables conditional module requests for MCLK\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum MCLKREQEN_A {
92    #[doc = "0: MCLK conditional requests are disabled."]
93    MCLKREQEN_0 = 0,
94    #[doc = "1: MCLK conditional requests are enabled."]
95    MCLKREQEN_1 = 1,
96}
97impl From<MCLKREQEN_A> for bool {
98    #[inline(always)]
99    fn from(variant: MCLKREQEN_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl MCLKREQEN_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> MCLKREQEN_A {
107        match self.bits {
108            false => MCLKREQEN_A::MCLKREQEN_0,
109            true => MCLKREQEN_A::MCLKREQEN_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `MCLKREQEN_0`"]
113    #[inline(always)]
114    pub fn is_mclkreqen_0(&self) -> bool {
115        *self == MCLKREQEN_A::MCLKREQEN_0
116    }
117    #[doc = "Checks if the value of the field is `MCLKREQEN_1`"]
118    #[inline(always)]
119    pub fn is_mclkreqen_1(&self) -> bool {
120        *self == MCLKREQEN_A::MCLKREQEN_1
121    }
122}
123#[doc = "Field `MCLKREQEN` writer - MCLK clock request enable. Setting this enables conditional module requests for MCLK"]
124pub type MCLKREQEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CSCTL8_SPEC, MCLKREQEN_A, O>;
125impl<'a, const O: u8> MCLKREQEN_W<'a, O> {
126    #[doc = "MCLK conditional requests are disabled."]
127    #[inline(always)]
128    pub fn mclkreqen_0(self) -> &'a mut W {
129        self.variant(MCLKREQEN_A::MCLKREQEN_0)
130    }
131    #[doc = "MCLK conditional requests are enabled."]
132    #[inline(always)]
133    pub fn mclkreqen_1(self) -> &'a mut W {
134        self.variant(MCLKREQEN_A::MCLKREQEN_1)
135    }
136}
137#[doc = "Field `SMCLKREQEN` reader - SMCLK clock request enable. Setting this enables conditional module requests for SMCLK"]
138pub type SMCLKREQEN_R = crate::BitReader<SMCLKREQEN_A>;
139#[doc = "SMCLK clock request enable. Setting this enables conditional module requests for SMCLK\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum SMCLKREQEN_A {
142    #[doc = "0: SMCLK conditional requests are disabled."]
143    SMCLKREQEN_0 = 0,
144    #[doc = "1: SMCLK conditional requests are enabled."]
145    SMCLKREQEN_1 = 1,
146}
147impl From<SMCLKREQEN_A> for bool {
148    #[inline(always)]
149    fn from(variant: SMCLKREQEN_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl SMCLKREQEN_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> SMCLKREQEN_A {
157        match self.bits {
158            false => SMCLKREQEN_A::SMCLKREQEN_0,
159            true => SMCLKREQEN_A::SMCLKREQEN_1,
160        }
161    }
162    #[doc = "Checks if the value of the field is `SMCLKREQEN_0`"]
163    #[inline(always)]
164    pub fn is_smclkreqen_0(&self) -> bool {
165        *self == SMCLKREQEN_A::SMCLKREQEN_0
166    }
167    #[doc = "Checks if the value of the field is `SMCLKREQEN_1`"]
168    #[inline(always)]
169    pub fn is_smclkreqen_1(&self) -> bool {
170        *self == SMCLKREQEN_A::SMCLKREQEN_1
171    }
172}
173#[doc = "Field `SMCLKREQEN` writer - SMCLK clock request enable. Setting this enables conditional module requests for SMCLK"]
174pub type SMCLKREQEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CSCTL8_SPEC, SMCLKREQEN_A, O>;
175impl<'a, const O: u8> SMCLKREQEN_W<'a, O> {
176    #[doc = "SMCLK conditional requests are disabled."]
177    #[inline(always)]
178    pub fn smclkreqen_0(self) -> &'a mut W {
179        self.variant(SMCLKREQEN_A::SMCLKREQEN_0)
180    }
181    #[doc = "SMCLK conditional requests are enabled."]
182    #[inline(always)]
183    pub fn smclkreqen_1(self) -> &'a mut W {
184        self.variant(SMCLKREQEN_A::SMCLKREQEN_1)
185    }
186}
187#[doc = "Field `MODOSCREQEN` reader - MODOSC clock request enable. Setting this enables conditional module requests for MODOSC."]
188pub type MODOSCREQEN_R = crate::BitReader<MODOSCREQEN_A>;
189#[doc = "MODOSC clock request enable. Setting this enables conditional module requests for MODOSC.\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum MODOSCREQEN_A {
192    #[doc = "0: MODOSC conditional requests are disabled."]
193    MODOSCREQEN_0 = 0,
194    #[doc = "1: MODOSC conditional requests are enabled."]
195    MODOSCREQEN_1 = 1,
196}
197impl From<MODOSCREQEN_A> for bool {
198    #[inline(always)]
199    fn from(variant: MODOSCREQEN_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl MODOSCREQEN_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub fn variant(&self) -> MODOSCREQEN_A {
207        match self.bits {
208            false => MODOSCREQEN_A::MODOSCREQEN_0,
209            true => MODOSCREQEN_A::MODOSCREQEN_1,
210        }
211    }
212    #[doc = "Checks if the value of the field is `MODOSCREQEN_0`"]
213    #[inline(always)]
214    pub fn is_modoscreqen_0(&self) -> bool {
215        *self == MODOSCREQEN_A::MODOSCREQEN_0
216    }
217    #[doc = "Checks if the value of the field is `MODOSCREQEN_1`"]
218    #[inline(always)]
219    pub fn is_modoscreqen_1(&self) -> bool {
220        *self == MODOSCREQEN_A::MODOSCREQEN_1
221    }
222}
223#[doc = "Field `MODOSCREQEN` writer - MODOSC clock request enable. Setting this enables conditional module requests for MODOSC."]
224pub type MODOSCREQEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CSCTL8_SPEC, MODOSCREQEN_A, O>;
225impl<'a, const O: u8> MODOSCREQEN_W<'a, O> {
226    #[doc = "MODOSC conditional requests are disabled."]
227    #[inline(always)]
228    pub fn modoscreqen_0(self) -> &'a mut W {
229        self.variant(MODOSCREQEN_A::MODOSCREQEN_0)
230    }
231    #[doc = "MODOSC conditional requests are enabled."]
232    #[inline(always)]
233    pub fn modoscreqen_1(self) -> &'a mut W {
234        self.variant(MODOSCREQEN_A::MODOSCREQEN_1)
235    }
236}
237impl R {
238    #[doc = "Bit 0 - ACLK clock request enable. Setting this enables conditional module requests for ACLK"]
239    #[inline(always)]
240    pub fn aclkreqen(&self) -> ACLKREQEN_R {
241        ACLKREQEN_R::new((self.bits & 1) != 0)
242    }
243    #[doc = "Bit 1 - MCLK clock request enable. Setting this enables conditional module requests for MCLK"]
244    #[inline(always)]
245    pub fn mclkreqen(&self) -> MCLKREQEN_R {
246        MCLKREQEN_R::new(((self.bits >> 1) & 1) != 0)
247    }
248    #[doc = "Bit 2 - SMCLK clock request enable. Setting this enables conditional module requests for SMCLK"]
249    #[inline(always)]
250    pub fn smclkreqen(&self) -> SMCLKREQEN_R {
251        SMCLKREQEN_R::new(((self.bits >> 2) & 1) != 0)
252    }
253    #[doc = "Bit 3 - MODOSC clock request enable. Setting this enables conditional module requests for MODOSC."]
254    #[inline(always)]
255    pub fn modoscreqen(&self) -> MODOSCREQEN_R {
256        MODOSCREQEN_R::new(((self.bits >> 3) & 1) != 0)
257    }
258}
259impl W {
260    #[doc = "Bit 0 - ACLK clock request enable. Setting this enables conditional module requests for ACLK"]
261    #[inline(always)]
262    pub fn aclkreqen(&mut self) -> ACLKREQEN_W<0> {
263        ACLKREQEN_W::new(self)
264    }
265    #[doc = "Bit 1 - MCLK clock request enable. Setting this enables conditional module requests for MCLK"]
266    #[inline(always)]
267    pub fn mclkreqen(&mut self) -> MCLKREQEN_W<1> {
268        MCLKREQEN_W::new(self)
269    }
270    #[doc = "Bit 2 - SMCLK clock request enable. Setting this enables conditional module requests for SMCLK"]
271    #[inline(always)]
272    pub fn smclkreqen(&mut self) -> SMCLKREQEN_W<2> {
273        SMCLKREQEN_W::new(self)
274    }
275    #[doc = "Bit 3 - MODOSC clock request enable. Setting this enables conditional module requests for MODOSC."]
276    #[inline(always)]
277    pub fn modoscreqen(&mut self) -> MODOSCREQEN_W<3> {
278        MODOSCREQEN_W::new(self)
279    }
280    #[doc = "Writes raw bits to the register."]
281    #[inline(always)]
282    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
283        self.0.bits(bits);
284        self
285    }
286}
287#[doc = "Clock System Control Register 8\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csctl8](index.html) module"]
288pub struct CSCTL8_SPEC;
289impl crate::RegisterSpec for CSCTL8_SPEC {
290    type Ux = u16;
291}
292#[doc = "`read()` method returns [csctl8::R](R) reader structure"]
293impl crate::Readable for CSCTL8_SPEC {
294    type Reader = R;
295}
296#[doc = "`write(|w| ..)` method takes [csctl8::W](W) writer structure"]
297impl crate::Writable for CSCTL8_SPEC {
298    type Writer = W;
299}
300#[doc = "`reset()` method sets CSCTL8 to value 0"]
301impl crate::Resettable for CSCTL8_SPEC {
302    #[inline(always)]
303    fn reset_value() -> Self::Ux {
304        0
305    }
306}
msp430fr2355/cs/csctl8.rs

msp430fr2355/cs/
csctl8.rs
