[−][src]Module msp430fr2355::cs::csctl5
Clock System Control 5
Structs
| DIVM_W | Write proxy for field |
| DIVS_W | Write proxy for field |
| SMCLKOFF_W | Write proxy for field |
| VLOAUTOOFF_W | Write proxy for field |
Enums
| DIVM_A | MCLK source divider |
| DIVS_A | SMCLK source divider. SMCLK directly derives from MCLK. SMCLK frequency is the combination of DIVM and DIVS out of selected clock source. |
| SMCLKOFF_A | SMCLK off. This bit turns off SMCLK clock |
| VLOAUTOOFF_A | VLO automatic off enable. This bit turns off VLO, if VLO is not used. |
Type Definitions
| DIVM_R | Reader of field |
| DIVS_R | Reader of field |
| R | Reader of register CSCTL5 |
| SMCLKOFF_R | Reader of field |
| VLOAUTOOFF_R | Reader of field |
| W | Writer for register CSCTL5 |