Expand description
Peripheral access API for MSP430F6736 microcontrollers (generated using svd2rust v0.24.0 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.
Modules§
- adc10_a
- ADC10_A
- auxilary_
supply - Auxilary Supply
- backup_
ram - Backup RAM
- crc16
- CRC16
- dma
- DMA
- flash
- Flash
- generic
- Common register and bit access and modify traits
- lcd_c
- LCD_C
- mpy_16
- MPY 16 Multiplier 16 Bit Mode
- mpy_32
- MPY 32 Multiplier 32 Bit Mode
- pmm
- PMM Power Management System
- port_9
- Port 9
- port_
1_ 2 - Port 1/2
- port_
3_ 4 - Port 3/4
- port_
5_ 6 - Port 5/6
- port_
7_ 8 - Port 7/8
- port_j
- Port J
- port_
mapping_ control - Port Mapping Control
- port_
mapping_ port_ 1 - Port Mapping Port 1
- port_
mapping_ port_ 2 - Port Mapping Port 2
- port_
mapping_ port_ 3 - Port Mapping Port 3
- rc
- RC RAM Control Module
- rtc_
c_ real_ time_ clock - RTC_C Real Time Clock
- sd24_b3
- SD24_B3
- sfr
- SFR Special Function Registers
- shared_
reference - Shared Reference
- sys
- SYS System Module
- timer_
0_ a3 - Timer0_A3
- timer_
1_ a2 - Timer1_A2
- timer_
2_ a2 - Timer2_A2
- timer_
3_ a2 - Timer3_A2
- ucs
- UCS Unified System Clock
- usci_
a0_ spi_ mode - USCI_A0 SPI Mode
- usci_
a0_ uart_ mode - USCI_A0 UART Mode
- usci_
a1_ spi_ mode - USCI_A1 SPI Mode
- usci_
a1_ uart_ mode - USCI_A1 UART Mode
- usci_
a2_ spi_ mode - USCI_A2 SPI Mode
- usci_
a2_ uart_ mode - USCI_A2 UART Mode
- usci_
b0_ i2c_ mode - USCI_B0 I2C Mode
- usci_
b0_ spi_ mode - USCI_B0 SPI Mode
- watchdog_
timer - Watchdog Timer
Structs§
- ADC10_A
- ADC10_A
- AUXILARY_
SUPPLY - Auxilary Supply
- BACKUP_
RAM - Backup RAM
- CRC16
- CRC16
- DMA
- DMA
- FLASH
- Flash
- LCD_C
- LCD_C
- MPY_16
- MPY 16 Multiplier 16 Bit Mode
- MPY_32
- MPY 32 Multiplier 32 Bit Mode
- PMM
- PMM Power Management System
- PORT_9
- Port 9
- PORT_
1_ 2 - Port 1/2
- PORT_
3_ 4 - Port 3/4
- PORT_
5_ 6 - Port 5/6
- PORT_
7_ 8 - Port 7/8
- PORT_J
- Port J
- PORT_
MAPPING_ CONTROL - Port Mapping Control
- PORT_
MAPPING_ PORT_ 1 - Port Mapping Port 1
- PORT_
MAPPING_ PORT_ 2 - Port Mapping Port 2
- PORT_
MAPPING_ PORT_ 3 - Port Mapping Port 3
- Peripherals
- All the peripherals
- RC
- RC RAM Control Module
- RTC_
C_ REAL_ TIME_ CLOCK - RTC_C Real Time Clock
- SD24_B3
- SD24_B3
- SFR
- SFR Special Function Registers
- SHARED_
REFERENCE - Shared Reference
- SYS
- SYS System Module
- TIMER_
0_ A3 - Timer0_A3
- TIMER_
1_ A2 - Timer1_A2
- TIMER_
2_ A2 - Timer2_A2
- TIMER_
3_ A2 - Timer3_A2
- UCS
- UCS Unified System Clock
- USCI_
A0_ SPI_ MODE - USCI_A0 SPI Mode
- USCI_
A0_ UART_ MODE - USCI_A0 UART Mode
- USCI_
A1_ SPI_ MODE - USCI_A1 SPI Mode
- USCI_
A1_ UART_ MODE - USCI_A1 UART Mode
- USCI_
A2_ SPI_ MODE - USCI_A2 SPI Mode
- USCI_
A2_ UART_ MODE - USCI_A2 UART Mode
- USCI_
B0_ I2C_ MODE - USCI_B0 I2C Mode
- USCI_
B0_ SPI_ MODE - USCI_B0 SPI Mode
- WATCHDOG_
TIMER - Watchdog Timer
Enums§
- Interrupt
- Enumeration of all the interrupts. This enum is seldom used in application or library crates. It is present primarily for documenting the device’s implemented interrupts.