Enum msp430f5529::dma::dmactl1::DMA2TSEL_A
source · [−]#[repr(u8)]
pub enum DMA2TSEL_A {
Show 32 variants
DMA2TSEL_0,
DMA2TSEL_1,
DMA2TSEL_2,
DMA2TSEL_3,
DMA2TSEL_4,
DMA2TSEL_5,
DMA2TSEL_6,
DMA2TSEL_7,
DMA2TSEL_8,
DMA2TSEL_9,
DMA2TSEL_10,
DMA2TSEL_11,
DMA2TSEL_12,
DMA2TSEL_13,
DMA2TSEL_14,
DMA2TSEL_15,
DMA2TSEL_16,
DMA2TSEL_17,
DMA2TSEL_18,
DMA2TSEL_19,
DMA2TSEL_20,
DMA2TSEL_21,
DMA2TSEL_22,
DMA2TSEL_23,
DMA2TSEL_24,
DMA2TSEL_25,
DMA2TSEL_26,
DMA2TSEL_27,
DMA2TSEL_28,
DMA2TSEL_29,
DMA2TSEL_30,
DMA2TSEL_31,
}
Expand description
DMA channel 2 transfer select bit 0
Value on reset: 0
Variants
DMA2TSEL_0
0: DMA channel 2 transfer select 0: DMA_REQ (sw)
DMA2TSEL_1
1: DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG)
DMA2TSEL_2
2: DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG)
DMA2TSEL_3
3: DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG)
DMA2TSEL_4
4: DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG)
DMA2TSEL_5
5: DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG)
DMA2TSEL_6
6: DMA channel 2 transfer select 6: Timer2_A (TA2CCR2.IFG)
DMA2TSEL_7
7: DMA channel 2 transfer select 7: TimerB (TB0CCR0.IFG)
DMA2TSEL_8
8: DMA channel 2 transfer select 8: TimerB (TB0CCR2.IFG)
DMA2TSEL_9
9: DMA channel 2 transfer select 9: Reserved
DMA2TSEL_10
10: DMA channel 2 transfer select 10: Reserved
DMA2TSEL_11
11: DMA channel 2 transfer select 11: Reserved
DMA2TSEL_12
12: DMA channel 2 transfer select 12: Reserved
DMA2TSEL_13
13: DMA channel 2 transfer select 13: Reserved
DMA2TSEL_14
14: DMA channel 2 transfer select 14: Reserved
DMA2TSEL_15
15: DMA channel 2 transfer select 15: Reserved
DMA2TSEL_16
16: DMA channel 2 transfer select 16: USCIA0 receive
DMA2TSEL_17
17: DMA channel 2 transfer select 17: USCIA0 transmit
DMA2TSEL_18
18: DMA channel 2 transfer select 18: USCIB0 receive
DMA2TSEL_19
19: DMA channel 2 transfer select 19: USCIB0 transmit
DMA2TSEL_20
20: DMA channel 2 transfer select 20: USCIA1 receive
DMA2TSEL_21
21: DMA channel 2 transfer select 21: USCIA1 transmit
DMA2TSEL_22
22: DMA channel 2 transfer select 22: USCIB1 receive
DMA2TSEL_23
23: DMA channel 2 transfer select 23: USCIB1 transmit
DMA2TSEL_24
24: DMA channel 2 transfer select 24: ADC12IFGx
DMA2TSEL_25
25: DMA channel 2 transfer select 25: Reserved
DMA2TSEL_26
26: DMA channel 2 transfer select 26: Reserved
DMA2TSEL_27
27: DMA channel 2 transfer select 27: USB FNRXD
DMA2TSEL_28
28: DMA channel 2 transfer select 28: USB ready
DMA2TSEL_29
29: DMA channel 2 transfer select 29: Multiplier ready
DMA2TSEL_30
30: DMA channel 2 transfer select 30: previous DMA channel DMA1IFG
DMA2TSEL_31
31: DMA channel 2 transfer select 31: ext. Trigger (DMAE0)
Trait Implementations
Performs the conversion.