ms_codeview/arch/arm64/
regs.rs

1register_set! {
2    pub enum Arm64Reg;
3    // General purpose 32-bit integer registers
4
5    W0     =  10,
6    W1     =  11,
7    W2     =  12,
8    W3     =  13,
9    W4     =  14,
10    W5     =  15,
11    W6     =  16,
12    W7     =  17,
13    W8     =  18,
14    W9     =  19,
15    W10    =  20,
16    W11    =  21,
17    W12    =  22,
18    W13    =  23,
19    W14    =  24,
20    W15    =  25,
21    W16    =  26,
22    W17    =  27,
23    W18    =  28,
24    W19    =  29,
25    W20    =  30,
26    W21    =  31,
27    W22    =  32,
28    W23    =  33,
29    W24    =  34,
30    W25    =  35,
31    W26    =  36,
32    W27    =  37,
33    W28    =  38,
34    W29    =  39,
35    W30    =  40,
36    WZR    =  41,
37
38    // General purpose 64-bit integer registers
39
40    X0     =  50,
41    X1     =  51,
42    X2     =  52,
43    X3     =  53,
44    X4     =  54,
45    X5     =  55,
46    X6     =  56,
47    X7     =  57,
48    X8     =  58,
49    X9     =  59,
50    X10    =  60,
51    X11    =  61,
52    X12    =  62,
53    X13    =  63,
54    X14    =  64,
55    X15    =  65,
56    IP0    =  66,
57    IP1    =  67,
58    X18    =  68,
59    X19    =  69,
60    X20    =  70,
61    X21    =  71,
62    X22    =  72,
63    X23    =  73,
64    X24    =  74,
65    X25    =  75,
66    X26    =  76,
67    X27    =  77,
68    X28    =  78,
69    FP     =  79,
70    LR     =  80,
71    SP     =  81,
72    ZR     =  82,
73
74    // statue register
75
76    NZCV   =  90,
77
78    // 32-bit floating point registers
79
80    S0     =  100,
81    S1     =  101,
82    S2     =  102,
83    S3     =  103,
84    S4     =  104,
85    S5     =  105,
86    S6     =  106,
87    S7     =  107,
88    S8     =  108,
89    S9     =  109,
90    S10    =  110,
91    S11    =  111,
92    S12    =  112,
93    S13    =  113,
94    S14    =  114,
95    S15    =  115,
96    S16    =  116,
97    S17    =  117,
98    S18    =  118,
99    S19    =  119,
100    S20    =  120,
101    S21    =  121,
102    S22    =  122,
103    S23    =  123,
104    S24    =  124,
105    S25    =  125,
106    S26    =  126,
107    S27    =  127,
108    S28    =  128,
109    S29    =  129,
110    S30    =  130,
111    S31    =  131,
112
113    // 64-bit floating point registers
114
115    D0     =  140,
116    D1     =  141,
117    D2     =  142,
118    D3     =  143,
119    D4     =  144,
120    D5     =  145,
121    D6     =  146,
122    D7     =  147,
123    D8     =  148,
124    D9     =  149,
125    D10    =  150,
126    D11    =  151,
127    D12    =  152,
128    D13    =  153,
129    D14    =  154,
130    D15    =  155,
131    D16    =  156,
132    D17    =  157,
133    D18    =  158,
134    D19    =  159,
135    D20    =  160,
136    D21    =  161,
137    D22    =  162,
138    D23    =  163,
139    D24    =  164,
140    D25    =  165,
141    D26    =  166,
142    D27    =  167,
143    D28    =  168,
144    D29    =  169,
145    D30    =  170,
146    D31    =  171,
147
148    // 128-bit SIMD registers
149
150    Q0     =  180,
151    Q1     =  181,
152    Q2     =  182,
153    Q3     =  183,
154    Q4     =  184,
155    Q5     =  185,
156    Q6     =  186,
157    Q7     =  187,
158    Q8     =  188,
159    Q9     =  189,
160    Q10    =  190,
161    Q11    =  191,
162    Q12    =  192,
163    Q13    =  193,
164    Q14    =  194,
165    Q15    =  195,
166    Q16    =  196,
167    Q17    =  197,
168    Q18    =  198,
169    Q19    =  199,
170    Q20    =  200,
171    Q21    =  201,
172    Q22    =  202,
173    Q23    =  203,
174    Q24    =  204,
175    Q25    =  205,
176    Q26    =  206,
177    Q27    =  207,
178    Q28    =  208,
179    Q29    =  209,
180    Q30    =  210,
181    Q31    =  211,
182
183    // Floating point status register
184
185    FPSR   =  220,
186}
ms_codeview/arch/arm64/regs.rs

ms_codeview/arch/arm64/
regs.rs
