mpfs_pac/
ethernet.rs

1// Network Control register bit definitions
2pub const GEM_IFG_EATS_QAV_CREDIT: u32 = 1 << 30;
3pub const GEM_TWO_PT_FIVE_GIG: u32 = 1 << 29;
4pub const GEM_SEL_MII_ON_RGMII: u32 = 1 << 28;
5pub const GEM_OSS_CORRECTION_FIELD: u32 = 1 << 27;
6pub const GEM_EXT_RXQ_SEL_EN: u32 = 1 << 26;
7pub const GEM_PFC_CTRL: u32 = 1 << 25;
8pub const GEM_ONE_STEP_SYNC_MODE: u32 = 1 << 24;
9pub const GEM_EXT_TSU_PORT_ENABLE: u32 = 1 << 23;
10pub const GEM_STORE_UDP_OFFSET: u32 = 1 << 22;
11pub const GEM_ALT_SGMII_MODE: u32 = 1 << 21;
12pub const GEM_PTP_UNICAST_ENA: u32 = 1 << 20;
13pub const GEM_TX_LPI_EN: u32 = 1 << 19;
14pub const GEM_FLUSH_RX_PKT_PCLK: u32 = 1 << 18;
15pub const GEM_TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME: u32 = 1 << 17;
16pub const GEM_PFC_ENABLE: u32 = 1 << 16;
17pub const GEM_STORE_RX_TS: u32 = 1 << 15;
18pub const GEM_TX_PAUSE_FRAME_ZERO: u32 = 1 << 12;
19pub const GEM_TX_PAUSE_FRAME_REQ: u32 = 1 << 11;
20pub const GEM_TRANSMIT_HALT: u32 = 1 << 10;
21pub const GEM_TRANSMIT_START: u32 = 1 << 9;
22pub const GEM_BACK_PRESSURE: u32 = 1 << 8;
23pub const GEM_STATS_WRITE_EN: u32 = 1 << 7;
24pub const GEM_INC_ALL_STATS_REGS: u32 = 1 << 6;
25pub const GEM_CLEAR_ALL_STATS_REGS: u32 = 1 << 5;
26pub const GEM_MAN_PORT_EN: u32 = 1 << 4;
27pub const GEM_ENABLE_TRANSMIT: u32 = 1 << 3;
28pub const GEM_ENABLE_RECEIVE: u32 = 1 << 2;
29pub const GEM_LOOPBACK_LOCAL: u32 = 1 << 1;
30pub const GEM_LOOPBACK: u32 = 1 << 0;
31
32/* General MAC Network Configuration register bit definitions */
33/* eMAC Network Configuration register bit definitions */
34
35pub const GEM_UNI_DIRECTION_ENABLE: u32 = 1 << 31;
36pub const GEM_IGNORE_IPG_RX_ER: u32 = 1 << 30;
37pub const GEM_NSP_CHANGE: u32 = 1 << 29;
38pub const GEM_IPG_STRETCH_ENABLE: u32 = 1 << 28;
39pub const GEM_SGMII_MODE_ENABLE: u32 = 1 << 27;
40pub const GEM_IGNORE_RX_FCS: u32 = 1 << 26;
41pub const GEM_EN_HALF_DUPLEX_RX: u32 = 1 << 25;
42pub const GEM_RECEIVE_CHECKSUM_OFFLOAD_ENABLE: u32 = 1 << 24;
43pub const GEM_DISABLE_COPY_OF_PAUSE_FRAMES: u32 = 1 << 23;
44pub const GEM_DATA_BUS_WIDTH: u32 = (1 << 21) | (1 << 22);
45pub const GEM_MDC_CLOCK_DIVISOR: u32 = (1 << 18) | (1 << 19) | (1 << 20);
46pub const GEM_FCS_REMOVE: u32 = 1 << 17;
47pub const GEM_LENGTH_FIELD_ERROR_FRAME_DISCARD: u32 = 1 << 16;
48pub const GEM_RECEIVE_BUFFER_OFFSET: u32 = (1 << 14) | (1 << 15);
49pub const GEM_PAUSE_ENABLE: u32 = 1 << 13;
50pub const GEM_RETRY_TEST: u32 = 1 << 12;
51pub const GEM_PCS_SELECT: u32 = 1 << 11;
52pub const GEM_GIGABIT_MODE_ENABLE: u32 = 1 << 10;
53pub const GEM_EXTERNAL_ADDRESS_MATCH_ENABLE: u32 = 1 << 9;
54pub const GEM_RECEIVE_1536_BYTE_FRAMES: u32 = 1 << 8;
55pub const GEM_UNICAST_HASH_ENABLE: u32 = 1 << 7;
56pub const GEM_MULTICAST_HASH_ENABLE: u32 = 1 << 6;
57pub const GEM_NO_BROADCAST: u32 = 1 << 5;
58pub const GEM_COPY_ALL_FRAMES: u32 = 1 << 4;
59pub const GEM_JUMBO_FRAMES: u32 = 1 << 3;
60pub const GEM_DISCARD_NON_VLAN_FRAMES: u32 = 1 << 2;
61pub const GEM_FULL_DUPLEX: u32 = 1 << 1;
62pub const GEM_SPEED: u32 = 1 << 0;
63
64pub const GEM_DATA_BUS_WIDTH_SHIFT: u32 = 21;
65pub const GEM_MDC_CLOCK_DIVISOR_SHIFT: u32 = 18;
66pub const GEM_MDC_CLOCK_DIVISOR_MASK: u32 = 0b111;
67pub const GEM_RECEIVE_BUFFER_OFFSET_SHIFT: u32 = 14;
68
69/* General MAC Network Status register bit definitions */
70/* eMAC Network Status register bit definitions */
71
72pub const GEM_LPI_INDICATE_PCLK: u32 = 1 << 7;
73pub const GEM_PFC_NEGOTIATE_PCLK: u32 = 1 << 6;
74pub const GEM_MAC_PAUSE_TX_EN: u32 = 1 << 5;
75pub const GEM_MAC_PAUSE_RX_EN: u32 = 1 << 4;
76pub const GEM_MAC_FULL_DUPLEX: u32 = 1 << 3;
77pub const GEM_MAN_DONE: u32 = 1 << 2;
78pub const GEM_MDIO_IN: u32 = 1 << 1;
79pub const GEM_PCS_LINK_STATE: u32 = 1 << 0;
80
81/* General MAC User IO register bit definitions */
82
83pub const GEM_CODEGROUP_BYPASS: u32 = 1 << 5;
84pub const GEM_COMMA_BYPASS: u32 = 1 << 4;
85pub const GEM_TSU_CLK_SOURCE: u32 = 1 << 0;
86
87/* General MAC DMA Config register bit definitions */
88/* eMAC DMA Config register bit definitions */
89
90pub const GEM_DMA_ADDR_BUS_WIDTH_1: u32 = 1 << 30;
91pub const GEM_TX_BD_EXTENDED_MODE_EN: u32 = 1 << 29;
92pub const GEM_RX_BD_EXTENDED_MODE_EN: u32 = 1 << 28;
93pub const GEM_FORCE_MAX_AMBA_BURST_TX: u32 = 1 << 26;
94pub const GEM_FORCE_MAX_AMBA_BURST_RX: u32 = 1 << 25;
95pub const GEM_FORCE_DISCARD_ON_ERR: u32 = 1 << 24;
96pub const GEM_RX_BUF_SIZE: u32 = 0xFF << 16;
97pub const GEM_CRC_ERROR_REPORT: u32 = 1 << 13;
98pub const GEM_INFINITE_LAST_DBUF_SIZE_EN: u32 = 1 << 12;
99pub const GEM_TX_PBUF_TCP_EN: u32 = 1 << 11;
100pub const GEM_TX_PBUF_SIZE: u32 = 1 << 10;
101pub const GEM_RX_PBUF_SIZE: u32 = (1 << 8) | (1 << 9);
102pub const GEM_ENDIAN_SWAP_PACKET: u32 = 1 << 7;
103pub const GEM_ENDIAN_SWAP_MANAGEMENT: u32 = 1 << 6;
104pub const GEM_HDR_DATA_SPLITTING_EN: u32 = 1 << 5;
105pub const GEM_AMBA_BURST_LENGTH: u32 = 0b11111;
106
107pub const GEM_RX_BUF_SIZE_SHIFT: u32 = 16;
108pub const GEM_RX_PBUF_SIZE_SHIFT: u32 = 8;
109
110/* General MAC Transmit Status register bit definitions */
111/* eMAC Transmit Status register bit definitions */
112
113pub const GEM_TX_DMA_LOCKUP_DETECTED: u32 = 1 << 10;
114pub const GEM_TX_MAC_LOCKUP_DETECTED: u32 = 1 << 9;
115pub const GEM_TX_RESP_NOT_OK: u32 = 1 << 8;
116pub const GEM_LATE_COLLISION_OCCURRED: u32 = 1 << 7;
117pub const GEM_STAT_TRANSMIT_UNDER_RUN: u32 = 1 << 6;
118pub const GEM_STAT_TRANSMIT_COMPLETE: u32 = 1 << 5;
119pub const GEM_STAT_AMBA_ERROR: u32 = 1 << 4;
120pub const GEM_TRANSMIT_GO: u32 = 1 << 3;
121pub const GEM_RETRY_LIMIT_EXCEEDED: u32 = 1 << 2;
122pub const GEM_COLLISION_OCCURRED: u32 = 1 << 1;
123pub const GEM_USED_BIT_READ: u32 = 1 << 0;
124
125/* General MAC Receive Queue Pointer register bit definitions */
126/* General MAC Receive Queue 1 Pointer register bit definitions */
127/* General MAC Receive Queue 2 Pointer register bit definitions */
128/* General MAC Receive Queue 3 Pointer register bit definitions */
129/* eMAC Receive Queue Pointer register bit definitions */
130
131pub const GEM_DMA_RX_Q_PTR: u32 = !((1 << 0) | (1 << 1));
132pub const GEM_DMA_RX_DIS_Q: u32 = 1 << 0;
133
134/* General MAC Transmit Queue Pointer register bit definitions */
135/* General MAC Transmit Queue 1 Pointer register bit definitions */
136/* General MAC Transmit Queue 2 Pointer register bit definitions */
137/* General MAC Transmit Queue 3 Pointer register bit definitions */
138/* eMAC Transmit Queue Pointer register bit definitions */
139
140pub const GEM_DMA_TX_Q_PTR: u32 = !((1 << 0) | (1 << 1));
141pub const GEM_DMA_TX_DIS_Q: u32 = 1 << 0;
142
143/* General MAC Receive Status register bit definitions */
144/* eMAC Receive Status register bit definitions */
145
146pub const GEM_RX_DMA_LOCKUP_DETECTED: u32 = 1 << 5;
147pub const GEM_RX_MAC_LOCKUP_DETECTED: u32 = 1 << 4;
148pub const GEM_RX_RESP_NOT_OK: u32 = 1 << 3;
149pub const GEM_RECEIVE_OVERRUN: u32 = 1 << 2;
150pub const GEM_FRAME_RECEIVED: u32 = 1 << 1;
151pub const GEM_BUFFER_NOT_AVAILABLE: u32 = 1 << 0;
152
153/* General MAC Interrupt Status register bit definitions */
154/* General MAC Interrupt Enable register bit definitions */
155/* General MAC Interrupt Disable register bit definitions */
156/* General MAC Interrupt Mask register bit definitions */
157/* General MAC Priority Queue 1 Interrupt Status register bit definitions  - b01 to b11 only */
158/* General MAC Priority Queue 2 Interrupt Status register bit definitions  - b01 to b11 only */
159/* General MAC Priority Queue 3 Interrupt Status register bit definitions  - b01 to b11 only */
160/* General MAC Priority Queue 1 Interrupt Enable register bit definitions  - b01 to b11 only */
161/* General MAC Priority Queue 2 Interrupt Enable register bit definitions  - b01 to b11 only */
162/* General MAC Priority Queue 3 Interrupt Enable register bit definitions  - b01 to b11 only */
163/* General MAC Priority Queue 1 Interrupt Disable register bit definitions  - b01 to b11 only */
164/* General MAC Priority Queue 2 Interrupt Disable register bit definitions  - b01 to b11 only */
165/* General MAC Priority Queue 3 Interrupt Disable register bit definitions  - b01 to b11 only */
166/* General MAC Priority Queue 1 Interrupt Mask register bit definitions  - b01 to b11 only */
167/* General MAC Priority Queue 2 Interrupt Mask register bit definitions  - b01 to b11 only */
168/* General MAC Priority Queue 3 Interrupt Mask register bit definitions  - b01 to b11 only */
169/* eMAC Interrupt Status register bit definitions */
170/* eMAC Interrupt Enable register bit definitions */
171/* eMAC Interrupt Disable register bit definitions */
172/* eMAC Interrupt Mask register bit definitions */
173
174pub const GEM_TX_LOCKUP_DETECTED: u32 = 1 << 31;
175pub const GEM_RX_LOCKUP_DETECTED: u32 = 1 << 30;
176pub const GEM_TSU_TIMER_COMPARISON_INTERRUPT: u32 = 1 << 29;
177pub const GEM_WOL_INTERRUPT: u32 = 1 << 28;
178pub const GEM_RX_LPI_INDICATION_STATUS_BIT_CHANGE: u32 = 1 << 27;
179pub const GEM_TSU_SECONDS_REGISTER_INCREMENT: u32 = 1 << 26;
180pub const GEM_PTP_PDELAY_RESP_FRAME_TRANSMITTED: u32 = 1 << 25;
181pub const GEM_PTP_PDELAY_REQ_FRAME_TRANSMITTED: u32 = 1 << 24;
182pub const GEM_PTP_PDELAY_RESP_FRAME_RECEIVED: u32 = 1 << 23;
183pub const GEM_PTP_PDELAY_REQ_FRAME_RECEIVED: u32 = 1 << 22;
184pub const GEM_PTP_SYNC_FRAME_TRANSMITTED: u32 = 1 << 21;
185pub const GEM_PTP_DELAY_REQ_FRAME_TRANSMITTED: u32 = 1 << 20;
186pub const GEM_PTP_SYNC_FRAME_RECEIVED: u32 = 1 << 19;
187pub const GEM_PTP_DELAY_REQ_FRAME_RECEIVED: u32 = 1 << 18;
188pub const GEM_PCS_LINK_PARTNER_PAGE_RECEIVED: u32 = 1 << 17;
189pub const GEM_PCS_AUTO_NEGOTIATION_COMPLETE: u32 = 1 << 16;
190pub const GEM_EXTERNAL_INTERRUPT: u32 = 1 << 15;
191pub const GEM_PAUSE_FRAME_TRANSMITTED: u32 = 1 << 14;
192pub const GEM_PAUSE_TIME_ELAPSED: u32 = 1 << 13;
193pub const GEM_PAUSE_FRAME_WITH_NON_0_PAUSE_QUANTUM_RX: u32 = 1 << 12;
194pub const GEM_RESP_NOT_OK_INT: u32 = 1 << 11;
195pub const GEM_RECEIVE_OVERRUN_INT: u32 = 1 << 10;
196pub const GEM_LINK_CHANGE: u32 = 1 << 9;
197pub const GEM_TRANSMIT_COMPLETE: u32 = 1 << 7;
198pub const GEM_AMBA_ERROR: u32 = 1 << 6;
199pub const GEM_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION: u32 = 1 << 5;
200pub const GEM_TRANSMIT_UNDER_RUN: u32 = 1 << 4;
201pub const GEM_TX_USED_BIT_READ: u32 = 1 << 3;
202pub const GEM_RX_USED_BIT_READ: u32 = 1 << 2;
203pub const GEM_RECEIVE_COMPLETE: u32 = 1 << 1;
204pub const GEM_MANAGEMENT_FRAME_SENT: u32 = 1 << 0;
205
206/*
207 * General MAC Fatal or Non Fatal Interrupt register bit definitions
208 * Note bits 0 to 15 are as per interrupt mask etc registers above.
209 */
210
211pub const GEM_LOCKUP_DETECTED_INT_TYPE: u32 = 1 << 22;
212pub const GEM_TSU_TIMER_COMPARISON_INTERRUPT_INT_TYPE: u32 = 1 << 21;
213pub const GEM_WOL_INTERRUPT_INT_TYPE: u32 = 1 << 20;
214pub const GEM_RECEIVE_LPI_INT_TYPE: u32 = 1 << 19;
215pub const GEM_TSU_SECONDS_REGISTER_INCREMENT_INT_TYPE: u32 = 1 << 18;
216pub const GEM_PTP_FRAME_RECEIVED_INT_TYPE: u32 = 1 << 17;
217pub const GEM_PCS_INT_TYPE: u32 = 1 << 16;
218
219/* General MAC Phy Management register bit definitions */
220/* eMAC Phy Management register bit definitions */
221
222pub const GEM_WRITE0: u32 = 1 << 31;
223pub const GEM_WRITE1: u32 = 1 << 30;
224pub const GEM_OPERATION: u32 = (1 << 28) | (1 << 29);
225pub const GEM_PHY_ADDRESS: u32 = 0b11111 << 23;
226pub const GEM_REGISTER_ADDRESS: u32 = 0b11111 << 18;
227pub const GEM_WRITE10: u32 = (1 << 16) | (1 << 17);
228pub const GEM_PHY_WRITE_READ_DATA: u32 = 0xFFFF;
229
230pub const GEM_PHY_OP_CL22_WRITE: u32 = 1;
231pub const GEM_PHY_OP_CL22_READ: u32 = 2;
232
233pub const GEM_PHY_OP_CL45_ADDRESS: u32 = 0;
234pub const GEM_PHY_OP_CL45_WRITE: u32 = 1;
235pub const GEM_PHY_OP_CL45_POST_READ_INC: u32 = 2;
236pub const GEM_PHY_OP_CL45_READ: u32 = 3;
237
238pub const GEM_OPERATION_SHIFT: u32 = 28;
239pub const GEM_PHY_ADDRESS_SHIFT: u32 = 23;
240pub const GEM_REGISTER_ADDRESS_SHIFT: u32 = 18;
241pub const GEM_WRITE10_SHIFT: u32 = 16;
242
243/* General MAC Pause Time register bit definitions */
244/* General MAC Transmit Pause Time register bit definitions */
245/* eMAC Pause Time register bit definitions */
246/* eMAC Transmit Pause Time register bit definitions */
247
248pub const GEM_QUANTUM: u32 = 0xFFFF;
249
250/* General MAC PBuff TX Cutthru register bit definitions */
251/* General MAC PBuff RX Cutthru register bit definitions */
252/* eMAC PBuff TX Cutthru register bit definitions */
253/* eMAC PBuff RX Cutthru register bit definitions */
254
255pub const GEM_DMA_CUTTHRU: u32 = 1 << 31;
256pub const GEM_DMA_TX_CUTTHRU_THRESHOLD: u32 = 0b11111111111;
257pub const GEM_DMA_RX_CUTTHRU_THRESHOLD: u32 = 0b1111111111;
258pub const GEM_DMA_EMAC_CUTTHRU_THRESHOLD: u32 = 0b111111111;
259
260/* General MAC AXI Max Pipeline register bit definitions */
261/* eMAC AXI Max Pipeline register bit definitions */
262
263pub const GEM_USE_AW2B_FILL: u32 = 1 << 16;
264pub const GEM_AW2W_MAX_PIPELINE: u32 = 0xFF << 8;
265pub const GEM_AR2R_MAX_PIPELINE: u32 = 0xFF;
266
267/* General MAC Int Moderation register bit definitions */
268/* eMAC Int Moderation register bit definitions */
269
270pub const GEM_TX_INT_MODERATION: u32 = 0xFF << 16;
271pub const GEM_RX_INT_MODERATION: u32 = 0xFF;
272
273/* General MAC Sys Wake Time register bit definitions */
274/* eMAC Sys Wake Time register bit definitions */
275
276pub const GEM_SYS_WAKE_TIME: u32 = 0xFFFF;
277
278/* General MAC Lockup Config register bit definitions */
279/* General RX MAC Lockup Time register bit definitions */
280/* eMAC Lockup Config register bit definitions */
281/* RX eMAC Lockup Time register bit definitions */
282
283pub const GEM_TX_DMA_LOCKUP_MON_EN: u32 = 1 << 31;
284pub const GEM_TX_MAC_LOCKUP_MON_EN: u32 = 1 << 30;
285pub const GEM_RX_DMA_LOCKUP_MON_EN: u32 = 1 << 29;
286pub const GEM_RX_MAC_LOCKUP_MON_EN: u32 = 1 << 28;
287pub const GEM_LOCKUP_RECOVERY_EN: u32 = 1 << 27;
288pub const GEM_LOCKUP_TIME: u32 = 0xFFFF;
289
290/* General MAC Specific Address 1 Top register bit definitions */
291/* General MAC Specific Address 2 Top register bit definitions */
292/* General MAC Specific Address 3 Top register bit definitions */
293/* General MAC Specific Address 4 Top register bit definitions */
294/* eMAC Specific Address 1 Top register bit definitions */
295/* eMAC Specific Address 2 Top register bit definitions */
296/* eMAC Specific Address 3 Top register bit definitions */
297/* eMAC Specific Address 4 Top register bit definitions */
298
299pub const GEM_FILTER_BYTE_MASK: u32 = 0b111111 << 24;
300pub const GEM_FILTER_TYPE: u32 = 1 << 16;
301pub const GEM_SPEC_ADDRESS: u32 = 0xFFFF;
302
303/* General MAC Specific Address Type 1 register bit definitions */
304/* General MAC Specific Address Type 2 register bit definitions */
305/* General MAC Specific Address Type 3 register bit definitions */
306/* General MAC Specific Address Type 4 register bit definitions */
307/* eMAC Specific Address Type 1 register bit definitions */
308/* eMAC Specific Address Type 2 register bit definitions */
309/* eMAC Specific Address Type 3 register bit definitions */
310/* eMAC Specific Address Type 4 register bit definitions */
311
312pub const GEM_ENABLE_COPY: u32 = 1 << 31;
313pub const GEM_SPEC_ADDR_MATCH: u32 = 0xFFFF;
314
315/* General MAC Wake On LAN register bit definitions */
316/* eMAC Wake On LAN register bit definitions */
317
318pub const GEM_WOL_MULTICAST_HASH: u32 = 1 << 19;
319pub const GEM_WOL_SPEC_ADDRESS_1: u32 = 1 << 18;
320pub const GEM_WOL_ARP_REQUEST: u32 = 1 << 17;
321pub const GEM_WOL_MAGIC_PACKET: u32 = 1 << 16;
322pub const GEM_WOL_ADDRESS: u32 = 0xFFFF;
323
324/* General MAC Stretch Ratio register bit definitions */
325/* eMAC Stretch Ratio register bit definitions */
326
327pub const GEM_IPG_STRETCH: u32 = 0xFFFF;
328pub const GEM_IPG_STRETCH_DIV: u32 = 0xFF << 8;
329pub const GEM_IPG_STRETCH_MUL: u32 = 0xFF;
330
331pub const GEM_IPG_STRETCH_DIV_MASK: u32 = 0xFF;
332pub const GEM_IPG_STRETCH_DIV_SHIFT: u32 = 8;
333pub const GEM_IPG_STRETCH_MUL_MASK: u32 = 0xFF;
334
335/* General MAC Stacked VLAN register bit definitions */
336/* eMAC Stacked VLAN register bit definitions */
337
338pub const GEM_ENABLE_PROCESSING: u32 = 1 << 31;
339pub const GEM_VLAN_MATCH: u32 = 0xFFFF;
340pub const GEM_VLAN_C_TAG: u32 = 0x8100;
341pub const GEM_VLAN_S_TAG: u32 = 0x88A8;
342
343/* Valid EtherTypes including VLAN tags must be bigger than this */
344pub const GEM_VLAN_ETHERTYPE_MIN: u32 = 1536;
345pub const GEM_VLAN_NO_STACK: u32 = 0;
346
347/* General MAC Transmit PFC Pause register bit definitions */
348/* eMAC Transmit PFC Pause register bit definitions */
349
350pub const GEM_VECTOR: u32 = 0xFF << 8;
351pub const GEM_VECTOR_ENABLE: u32 = 0xFF;
352
353/* General MAC Specific Address Type 1 Mask register bit definitions */
354/* eMAC Specific Address Type 1 Mask register bit definitions */
355
356pub const GEM_SPEC_ADDR_MASK: u32 = 0xFFFF;
357
358/* General MAC Receive DMA Data Buffer Address Mask register bit definitions */
359/* eMAC Receive DMA Data Buffer Address Mask register bit definitions */
360
361pub const GEM_DMA_DBUF_ADDR_MASK_VALUE: u32 = 0b1111 << 28;
362pub const GEM_DMA_DBUF_ADDR_MASK_ENABLE: u32 = 0b1111;
363
364/* General MAC TSU timer comparison value nanosecond register bit definitions */
365/* eMAC TSU timer comparison value nanosecond register bit definitions */
366
367pub const GEM_NSEC_COMPARISON_VALUE: u32 = 0b1111111111111111111111;
368
369/* General MAC TSU timer comparison value seconds 47:32 register bit definitions */
370/* General MAC PTP Event Frame Transmitted Seconds Register 47:32 register bit definitions */
371/* General MAC PTP Event Frame Received Seconds Register 47:32 register bit definitions */
372/* General MAC PTP Peer Event Frame Transmitted Seconds Register 47:32 register bit definitions */
373/* General MAC PTP Peer Event Frame Received Seconds Register 47:32 register bit definitions */
374/* eMAC TSU timer comparison value seconds 47:32 register bit definitions */
375/* eMAC PTP Event Frame Transmitted Seconds Register 47:32 register bit definitions */
376/* eMAC PTP Event Frame Received Seconds Register 47:32 register bit definitions */
377/* eMAC PTP Peer Event Frame Transmitted Seconds Register 47:32 register bit definitions */
378/* eMAC PTP Peer Event Frame Received Seconds Register 47:32 register bit definitions */
379
380pub const GEM_SEC_VALUE_UPPER: u32 = 0xFFFF;
381
382/* General MAC DP RAM Fill Debug register bit definitions */
383/* eMAC DP RAM Fill Debug register bit definitions */
384
385pub const GEM_DMA_TX_RX_FILL_LEVEL: u32 = 0xFFFF << 16;
386pub const GEM_DMA_TX_Q_FILL_LEVEL_SELECT: u32 = 0b1111 << 4;
387pub const GEM_DMA_TX_RX_FILL_LEVEL_SELECT: u32 = 1 << 0;
388
389/* General MAC Revision register bit definitions */
390/* eMAC Revision register bit definitions */
391
392pub const GEM_FIX_NUMBER: u32 = 0b1111 << 24;
393pub const GEM_MODULE_IDENTIFICATION_NUMBER: u32 = 0xFFF << 16;
394pub const GEM_MODULE_REVISION: u32 = 0xFFFF;
395
396/* General MAC Octets Transmitted Top register bit definitions */
397/* General MAC Octets Received Top register bit definitions */
398/* eMAC Octets Transmitted Top register bit definitions */
399/* eMAC Octets Received Top register bit definitions */
400
401pub const GEM_UPPER_BITS_OF_48: u32 = 0xFFFF;
402
403/* General MAC Pause Frames Transmitted register bit definitions */
404/* General MAC Pause Frames Received register bit definitions */
405/* eMAC Pause Frames Transmitted register bit definitions */
406/* eMAC Pause Frames Received register bit definitions */
407
408pub const GEM_FRAME_COUNT: u32 = 0xFFFF;
409
410/* General MAC Transmit Underruns register bit definitions */
411/* eMAC Transmit Underruns register bit definitions */
412
413pub const GEM_UNDERRUN_COUNT: u32 = 0b1111111111;
414
415/* General MAC Single Collision register bit definitions */
416/* General MAC Multiple Collisions register bit definitions */
417/* eMAC Single Collision register bit definitions */
418/* eMAC Multiple Collisions register bit definitions */
419
420pub const GEM_SM_COLLISION_COUNT: u32 = 0b111111111111111111;
421
422/* General MAC Late Collisions register bit definitions */
423/* eMAC Late Collisions register bit definitions */
424
425pub const GEM_LATE_COLLISION_COUNT: u32 = 0b1111111111;
426
427/* General MAC Deferred Frames register bit definitions */
428/* eMAC Deferred Frames register bit definitions */
429
430pub const GEM_DEFERRED_FRAMES_COUNT: u32 = 0b111111111111111111;
431
432/* General MAC CRS Errors register bit definitions */
433/* eMAC CRS Errors register bit definitions */
434
435pub const GEM_CRS_ERROR_COUNT: u32 = 0b1111111111;
436
437/* General MAC Undersize Frames Received register bit definitions */
438/* eMAC Undersize Frames Received register bit definitions */
439
440pub const GEM_RUNT_FRAME_COUNT: u32 = 0b1111111111;
441
442/* General MAC Oversize Frames Received register bit definitions */
443/* eMAC Oversize Frames Received register bit definitions */
444
445pub const GEM_OVERSIZE_FRAME_COUNT: u32 = 0b1111111111;
446
447/* General MAC Jabbers Received register bit definitions */
448/* eMAC Jabbers Received register bit definitions */
449
450pub const GEM_JABBER_COUNT: u32 = 0b1111111111;
451
452/* General MAC FCS Error register bit definitions */
453/* eMAC FCS Error register bit definitions */
454
455pub const GEM_FCS_ERROR_COUNT: u32 = 0b1111111111;
456
457/* General MAC Length Field Frame Errors register bit definitions */
458/* eMAC Length Field Frame Errors register bit definitions */
459
460pub const GEM_LENGTH_ERROR_COUNT: u32 = 0b1111111111;
461
462/* General MAC Receive Symbol Errors register bit definitions */
463/* eMAC Receive Symbol Errors register bit definitions */
464
465pub const GEM_SYMBOL_ERROR_COUNT: u32 = 0b1111111111;
466
467/* General MAC Receive Alignment Errors register bit definitions */
468/* eMAC Receive Alignment Errors register bit definitions */
469
470pub const GEM_ALIGNMENT_ERROR_COUNT: u32 = 0b1111111111;
471
472/* General MAC Receive Resource Error register bit definitions */
473/* eMAC Receive Resource Error register bit definitions */
474
475pub const GEM_RESOURCE_ERROR_COUNT: u32 = 0b1111111111;
476
477/* General MAC Receive Overrun register bit definitions */
478/* eMAC Receive Overrun register bit definitions */
479
480pub const GEM_OVERRUN_COUNT: u32 = 0b1111111111;
481
482/* General MAC IP Checksum Error register bit definitions */
483/* General MAC TCP Checksum Error register bit definitions */
484/* General MAC UDP Checksum Error register bit definitions */
485/* eMAC IP Checksum Error register bit definitions */
486/* eMAC TCP Checksum Error register bit definitions */
487/* eMAC UDP Checksum Error register bit definitions */
488
489pub const GEM_IP_CHECKSUM_ERROR_COUNT: u32 = 0xFF;
490
491/* General MAC Auto Flushed Packets register bit definitions */
492/* eMAC Auto Flushed Packets register bit definitions */
493
494pub const GEM_AUTO_FLUSHED_COUNT: u32 = 0xFFFF;
495
496/* General MAC TSU Timer Increment Sub Nanoseconds register bit definitions */
497/* eMAC TSU Timer Increment Sub Nanoseconds register bit definitions */
498
499pub const GEM_SUB_NS_INCR_LSB: u32 = 0xFF << 24;
500pub const GEM_SUB_NS_INCR: u32 = 0xFFFF;
501
502/* General MAC TSU Timer Seconds MSB register bit definitions */
503/* General MAC TSU Strobe Seconds MSB register bit definitions */
504
505pub const GEM_TSU_SECONDS_MSB: u32 = 0xFFFF;
506
507/* General MAC TSU Timer Sync Strobe Nanoseconds register bit definitions */
508/* General MAC TSU Timer Nanoseconds register bit definitions */
509/* General MAC TSU Timer Adjust register bit definitions */
510/* General MAC PTP Event Frame Transmitted Nanoseconds register bit definitions */
511/* General MAC PTP Event Frame Received Nanoseconds register bit definitions */
512/* General MAC PTP Peer Event Frame Transmitted Nanoseconds register bit definitions */
513/* General MAC PTP Peer Event Frame Received Nanoseconds register bit definitions */
514/* eMAC TSU Timer Sync Strobe Nanoseconds register bit definitions */
515/* eMAC TSU Timer Nanoseconds register bit definitions */
516/* eMAC TSU Timer Adjust register bit definitions */
517/* eMAC PTP Event Frame Transmitted Nanoseconds register bit definitions */
518/* eMAC PTP Event Frame Received Nanoseconds register bit definitions */
519/* eMAC PTP Peer Event Frame Transmitted Nanoseconds register bit definitions */
520/* eMAC PTP Peer Event Frame Received Nanoseconds register bit definitions */
521
522pub const GEM_ADD_SUBTRACT: u32 = 1 << 31; /* Adjust register only... */
523pub const GEM_TSU_NANOSECONDS: u32 = 0b111111111111111111111111111111;
524
525/* General MAC TSU Timer Adjust register bit definitions */
526/* eMAC TSU Timer Adjust register bit definitions */
527
528pub const GEM_NUM_INCS: u32 = 0xFF << 16;
529pub const GEM_ALT_NS_INC: u32 = 0xFF << 8;
530pub const GEM_NS_INCREMENT: u32 = 0xFF;
531
532/* General MAC PCS Control register bit definitions */
533
534pub const GEM_PCS_SOFTWARE_RESET: u32 = 1 << 15;
535pub const GEM_LOOPBACK_MODE: u32 = 1 << 14;
536pub const GEM_SPEED_SELECT_BIT_1: u32 = 1 << 13;
537pub const GEM_ENABLE_AUTO_NEG: u32 = 1 << 12;
538pub const GEM_RESTART_AUTO_NEG: u32 = 1 << 9;
539pub const GEM_MAC_DUPLEX_STATE: u32 = 1 << 8;
540pub const GEM_COLLISION_TEST: u32 = 1 << 7;
541pub const GEM_SPEED_SELECT_BIT_0: u32 = 1 << 6;
542
543/* General MAC PCS Status register bit definitions */
544
545pub const GEM_BASE_100_T4: u32 = 1 << 15;
546pub const GEM_BASE_100_X_FULL_DUPLEX: u32 = 1 << 14;
547pub const GEM_BASE_100_X_HALF_DUPLEX: u32 = 1 << 13;
548pub const GEM_MBPS_10_FULL_DUPLEX: u32 = 1 << 12;
549pub const GEM_MBPS_10_HALF_DUPLEX: u32 = 1 << 11;
550pub const GEM_BASE_100_T2_FULL_DUPLEX: u32 = 1 << 10;
551pub const GEM_BASE_100_T2_HALF_DUPLEX: u32 = 1 << 9;
552pub const GEM_EXTENDED_STATUS: u32 = 1 << 8;
553pub const GEM_AUTO_NEG_COMPLETE: u32 = 1 << 5;
554pub const GEM_REMOTE_FAULT: u32 = 1 << 4;
555pub const GEM_AUTO_NEG_ABILITY: u32 = 1 << 3;
556pub const GEM_LINK_STATUS: u32 = 1 << 2;
557pub const GEM_EXTENDED_CAPABILITIES: u32 = 1 << 0;
558
559/* General MAC PCS PHY Top ID register bit definitions */
560/* General MAC PCS PHY Bottom ID register bit definitions */
561
562pub const GEM_ID_CODE: u32 = 0xFFFF;
563
564/* General MAC PCS Autonegotiation Advertisment register bit definitions */
565
566pub const GEM_AN_AV_NEXT_PAGE: u32 = 1 << 15;
567pub const GEM_AN_AV_REMOTE_FAULT: u32 = (1 << 12) | (1 << 13);
568pub const GEM_AN_AV_PAUSE: u32 = (1 << 7) | (1 << 8);
569pub const GEM_AN_AV_HALF_DUPLEX: u32 = 1 << 6;
570pub const GEM_AN_AV_FULL_DUPLEX: u32 = 1 << 5;
571
572/* General MAC PCS Autonegotiation Link Partner Base register bit definitions */
573
574pub const GEM_LINK_PARTNER_NEXT_PAGE_STATUS: u32 = 1 << 15;
575pub const GEM_LINK_PARTNER_ACKNOWLEDGE: u32 = 1 << 14;
576pub const GEM_LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE: u32 = (1 << 12) | (1 << 13);
577pub const GEM_LINK_PARTNER_SPEED: u32 = (1 << 10) | (1 << 11);
578pub const GEM_LINK_PARTNER_PAUSE: u32 = (1 << 7) | (1 << 8);
579pub const GEM_LINK_PARTNER_HALF_DUPLEX: u32 = 1 << 6;
580pub const GEM_LINK_PARTNER_FULL_DUPLEX: u32 = 1 << 5;
581
582/* General MAC PCS Autonegotiation Next Page Ability register bit definitions */
583
584pub const GEM_NEXT_PAGE_CAPABILITY: u32 = 1 << 2;
585pub const GEM_PAGE_RECEIVED: u32 = 1 << 1;
586
587/* General MAC PCS Autonegotiation Next Page Transmit register bit definitions */
588/* General MAC PCS Autonegotiation Next Page Receive register bit definitions */
589
590pub const GEM_NEXT_PAGE_TO_TRANSMIT: u32 = 1 << 15;
591pub const GEM_NEXT_PAGE_TO_RECEIVE: u32 = 1 << 15;
592pub const GEM_ACKNOWLEDGE: u32 = 1 << 14;
593pub const GEM_MESSAGE_PAGE_INDICATOR: u32 = 1 << 13;
594pub const GEM_ACKNOWLEDGE_2: u32 = 1 << 12;
595pub const GEM_TOGGLE: u32 = 1 << 11;
596pub const GEM_AN_MESSAGE: u32 = 0b11111111111;
597
598/* General MAC PCS Autonegotiation Extended Status register bit definitions */
599
600pub const GEM_FULL_DUPLEX_1000BASE_X: u32 = 1 << 15;
601pub const GEM_HALF_DUPLEX_1000BASE_X: u32 = 1 << 14;
602pub const GEM_FULL_DUPLEX_1000BASE_T: u32 = 1 << 13;
603pub const GEM_HALF_DUPLEX_1000BASE_T: u32 = 1 << 12;
604
605/* General MAC Received LPI Transitions register bit definitions */
606/* General MAC Transmitted LPI Transitions register bit definitions */
607/* eMAC Received LPI Transitions register bit definitions */
608/* eMAC Transmitted LPI Transitions register bit definitions */
609
610pub const GEM_LPI_COUNT: u32 = 0xFFFF;
611
612/* General MAC Received LPI Time register bit definitions */
613/* General MAC Transmitted LPI Time register bit definitions */
614/* eMAC Received LPI Time register bit definitions */
615/* eMAC Transmitted LPI Time register bit definitions */
616
617pub const GEM_LPI_TIME: u32 = 0xFFFFFF;
618
619/* General MAC Design Configuration Debug 1 register bit definitions */
620/* eMAC Design Configuration Debug 1 register bit definitions */
621
622pub const GEM_AXI_CACHE_VALUE: u32 = 0b1111 << 28;
623pub const GEM_DMA_BUS_WIDTH: u32 = (1 << 25) | (1 << 26) | (1 << 27);
624pub const GEM_EXCLUDE_CBS: u32 = 1 << 24;
625pub const GEM_IRQ_READ_CLEAR: u32 = 1 << 23;
626pub const GEM_NO_SNAPSHOT: u32 = 1 << 22;
627pub const GEM_NO_STATS: u32 = 1 << 21;
628pub const GEM_USER_IN_WIDTH: u32 = 0b11111 << 15;
629pub const GEM_USER_OUT_WIDTH: u32 = 0b11111 << 10;
630pub const GEM_USER_IO: u32 = 1 << 9;
631pub const GEM_EXT_FIFO_INTERFACE: u32 = 1 << 6;
632pub const GEM_INT_LOOPBACK: u32 = 1 << 4;
633pub const GEM_EXCLUDE_QBV: u32 = 1 << 1;
634pub const GEM_NO_PCS: u32 = 1 << 0;
635
636/* General MAC Design Configuration Debug 2 register bit definitions */
637/* eMAC Design Configuration Debug 2 register bit definitions */
638
639pub const GEM_SPRAM: u32 = 1 << 31;
640pub const GEM_AXI: u32 = 1 << 30;
641pub const GEM_TX_PBUF_ADDR: u32 = 0xF << 26;
642pub const GEM_RX_PBUF_ADDR: u32 = 0xF << 22;
643pub const GEM_TX_PKT_BUFFER: u32 = 1 << 21;
644pub const GEM_RX_PKT_BUFFER: u32 = 1 << 20;
645pub const GEM_HPROT_VALUE: u32 = 0xF << 16;
646pub const GEM_JUMBO_MAX_LENGTH: u32 = 0x3FFF;
647
648/* General MAC Design Configuration Debug 3 register bit definitions */
649/* eMAC Design Configuration Debug 3 register bit definitions */
650
651pub const GEM_NUM_SPEC_ADD_FILTERS: u32 = 0x3F << 24;
652
653/* General MAC Design Configuration Debug 5 register bit definitions */
654/* eMAC Design Configuration Debug 5 register bit definitions */
655
656pub const GEM_AXI_PROT_VALUE: u32 = (1 << 29) | (1 << 30) | (1 << 31);
657pub const GEM_TSU_CLK: u32 = 1 << 28;
658pub const GEM_RX_BUFFER_LENGTH_DEF: u32 = 0xFF << 20;
659pub const GEM_TX_PBUF_SIZE_DEF: u32 = 1 << 19;
660pub const GEM_RX_PBUF_SIZE_DEF: u32 = (1 << 17) | (1 << 18);
661pub const GEM_ENDIAN_SWAP_DEF: u32 = (1 << 15) | (1 << 16);
662pub const GEM_MDC_CLOCK_DIV: u32 = (1 << 12) | (1 << 13) | (1 << 14);
663pub const GEM_DMA_BUS_WIDTH_DEF: u32 = (1 << 10) | (1 << 11);
664pub const GEM_PHY_IDENT: u32 = 1 << 9;
665pub const GEM_TSU: u32 = 1 << 8;
666pub const GEM_TX_FIFO_CNT_WIDTH: u32 = 0xF << 4;
667pub const GEM_RX_FIFO_CNT_WIDTH: u32 = 0xF;
668
669/* General MAC Design Configuration Debug 6 register bit definitions */
670/* eMAC Design Configuration Debug 6 register bit definitions */
671
672pub const GEM_PBUF_LSO: u32 = 1 << 27;
673pub const GEM_PBUF_RSC: u32 = 1 << 26;
674pub const GEM_PBUF_CUTTHRU: u32 = 1 << 25;
675pub const GEM_PFC_MULTI_QUANTUM: u32 = 1 << 24;
676pub const GEM_DMA_ADDR_WIDTH_IS_64B: u32 = 1 << 23;
677pub const GEM_HOST_IF_SOFT_SEL: u32 = 1 << 22;
678pub const GEM_TX_ADD_FIFO_IF: u32 = 1 << 21;
679pub const GEM_EXT_TSU_TIMER: u32 = 1 << 20;
680pub const GEM_TX_PBUF_QUEUE_SEGMENT_SIZE: u32 = 0xF << 16;
681pub const GEM_DMA_PRIORITY_QUEUE15: u32 = 1 << 15;
682pub const GEM_DMA_PRIORITY_QUEUE14: u32 = 1 << 14;
683pub const GEM_DMA_PRIORITY_QUEUE13: u32 = 1 << 13;
684pub const GEM_DMA_PRIORITY_QUEUE12: u32 = 1 << 12;
685pub const GEM_DMA_PRIORITY_QUEUE11: u32 = 1 << 11;
686pub const GEM_DMA_PRIORITY_QUEUE10: u32 = 1 << 10;
687pub const GEM_DMA_PRIORITY_QUEUE9: u32 = 1 << 9;
688pub const GEM_DMA_PRIORITY_QUEUE8: u32 = 1 << 8;
689pub const GEM_DMA_PRIORITY_QUEUE7: u32 = 1 << 7;
690pub const GEM_DMA_PRIORITY_QUEUE6: u32 = 1 << 6;
691pub const GEM_DMA_PRIORITY_QUEUE5: u32 = 1 << 5;
692pub const GEM_DMA_PRIORITY_QUEUE4: u32 = 1 << 4;
693pub const GEM_DMA_PRIORITY_QUEUE3: u32 = 1 << 3;
694pub const GEM_DMA_PRIORITY_QUEUE2: u32 = 1 << 2;
695pub const GEM_DMA_PRIORITY_QUEUE1: u32 = 1 << 1;
696
697/* General MAC Design Configuration Debug 7 register bit definitions */
698/* eMAC Design Configuration Debug 7 register bit definitions */
699
700pub const GEM_TX_PBUF_NUM_SEGMENTS_Q7: u32 = 0xF << 28;
701pub const GEM_TX_PBUF_NUM_SEGMENTS_Q6: u32 = 0xF << 24;
702pub const GEM_TX_PBUF_NUM_SEGMENTS_Q5: u32 = 0xF << 20;
703pub const GEM_TX_PBUF_NUM_SEGMENTS_Q4: u32 = 0xF << 16;
704pub const GEM_TX_PBUF_NUM_SEGMENTS_Q3: u32 = 0xF << 12;
705pub const GEM_TX_PBUF_NUM_SEGMENTS_Q2: u32 = 0xF << 8;
706pub const GEM_TX_PBUF_NUM_SEGMENTS_Q1: u32 = 0xF << 4;
707pub const GEM_TX_PBUF_NUM_SEGMENTS_Q0: u32 = 0xF;
708
709/* General MAC Design Configuration Debug 8 register bit definitions */
710/* eMAC Design Configuration Debug 8 register bit definitions */
711
712pub const GEM_NUM_TYPE1_SCREENERS: u32 = 0x3F << 24;
713pub const GEM_NUM_TYPE2_SCREENERS: u32 = 0x3F << 16;
714pub const GEM_NUM_SCR2_ETHTYPE_REGS: u32 = 0x3F << 8;
715pub const GEM_NUM_SCR2_COMPARE_REGS: u32 = 0xF;
716
717/* General MAC Design Configuration Debug 9 register bit definitions */
718/* eMAC Design Configuration Debug 9 register bit definitions */
719
720pub const GEM_TX_PBUF_NUM_SEGMENTS_Q15: u32 = 0xF << 28;
721pub const GEM_TX_PBUF_NUM_SEGMENTS_Q14: u32 = 0xF << 24;
722pub const GEM_TX_PBUF_NUM_SEGMENTS_Q13: u32 = 0xF << 20;
723pub const GEM_TX_PBUF_NUM_SEGMENTS_Q12: u32 = 0xF << 16;
724pub const GEM_TX_PBUF_NUM_SEGMENTS_Q11: u32 = 0xF << 12;
725pub const GEM_TX_PBUF_NUM_SEGMENTS_Q10: u32 = 0xF << 8;
726pub const GEM_TX_PBUF_NUM_SEGMENTS_Q9: u32 = 0xF << 4;
727pub const GEM_TX_PBUF_NUM_SEGMENTS_Q8: u32 = 0xF;
728
729/* General MAC Design Configuration Debug 10 register bit definitions */
730/* eMAC Design Configuration Debug 10 register bit definitions */
731
732pub const GEM_EMAC_BUS_WIDTH: u32 = 0xF << 28;
733pub const GEM_TX_PBUF_DATA: u32 = 0xF << 24;
734pub const GEM_RX_PBUF_DATA: u32 = 0xF << 20;
735pub const GEM_AXI_ACCESS_PIPELINE_BITS: u32 = 0xF << 16;
736pub const GEM_AXI_TX_DESCR_RD_BUFF_BITS: u32 = 0xF << 12;
737pub const GEM_AXI_RX_DESCR_RD_BUFF_BITS: u32 = 0xF << 8;
738pub const GEM_AXI_TX_DESCR_WR_BUFF_BITS: u32 = 0xF << 4;
739pub const GEM_AXI_RX_DESCR_WR_BUFF_BITS: u32 = 0xF;
740
741/* General MAC Design Configuration Debug 11 register bit definitions */
742/* eMAC Design Configuration Debug 11 register bit definitions */
743
744pub const GEM_PROTECT_DESCR_ADDR: u32 = 1 << 4;
745pub const GEM_PROTECT_TSU: u32 = 1 << 3;
746pub const GEM_ADD_CSR_PARITY: u32 = 1 << 2;
747pub const GEM_ADD_DP_PARITY: u32 = 1 << 1;
748pub const GEM_ADD_ECC_DPRAM: u32 = 1 << 0;
749
750/* General MAC Design Configuration Debug 12 register bit definitions */
751/* eMAC Design Configuration Debug 12 register bit definitions */
752
753pub const GEM_GEM_HAS_802P3_BR: u32 = 1 << 25;
754pub const GEM_EMAC_TX_PBUF_ADDR: u32 = 0xF << 21;
755pub const GEM_EMAC_RX_PBUF_ADDR: u32 = 0xF << 17;
756pub const GEM_GEM_HAS_CB: u32 = 1 << 16;
757pub const GEM_GEM_CB_HISTORY_LEN: u32 = 0xFF << 8;
758pub const GEM_GEM_NUM_CB_STREAMS: u32 = 0xF;
759
760/* General MAC Queue 1 DMA Receive Buffer Size register bit definitions */
761/* General MAC Queue 2 DMA Receive Buffer Size register bit definitions */
762/* General MAC Queue 3 DMA Receive Buffer Size register bit definitions */
763
764pub const GEM_DMA_RX_Q_BUF_SIZE: u32 = 0xFF;
765
766/* General MAC CBS Control register bit definitions */
767/* eMAC CBS Control register bit definitions */
768
769pub const GEM_CBS_ENABLE_QUEUE_B: u32 = 1 << 1;
770pub const GEM_CBS_ENABLE_QUEUE_A: u32 = 1 << 0;
771
772/* General MAC TX BD Control register bit definitions */
773/* General MAC RX BD Control register bit definitions */
774/* eMAC TX BD Control register bit definitions */
775/* eMAC RX BD Control register bit definitions */
776
777pub const GEM_BD_TS_MODE: u32 = (1 << 4) | (1 << 5);
778pub const GEM_BD_TS_MODE_SHIFT: u32 = 4;
779
780/* General MAC WD Counter register bit definitions */
781
782pub const GEM_RX_BD_REREAD_TIMER: u32 = 0xFF;
783
784/* General MAC AXI TX Full Threshold 0 register bit definitions */
785
786pub const GEM_AXI_TX_FULL_ADJ_0: u32 = 0x3FFF << 16;
787pub const GEM_AXI_TX_FULL_ADJ_1: u32 = 0xFFF;
788
789/* General MAC AXI TX Full Threshold 1 register bit definitions */
790
791pub const GEM_AXI_TX_FULL_ADJ_2: u32 = 0x3FFF << 16;
792pub const GEM_AXI_TX_FULL_ADJ_3: u32 = 0xFFF;
793
794/* General Screening Type 1 Register register bit definitions */
795
796pub const GEM_DROP_ON_MATCH: u32 = 1 << 30;
797pub const GEM_UDP_PORT_MATCH_ENABLE: u32 = 1 << 29;
798pub const GEM_DSTC_ENABLE: u32 = 1 << 28;
799pub const GEM_UDP_PORT_MATCH: u32 = 0xF << 12;
800pub const GEM_DSTC_MATCH: u32 = 0xF << 4;
801pub const GEM_QUEUE_NUMBER: u32 = 0xF;
802
803pub const GEM_UDP_PORT_MATCH_SHIFT: u32 = 12;
804pub const GEM_DSTC_MATCH_SHIFT: u32 = 4;
805
806/* General Screening Type 2 Register register bit definitions */
807
808pub const GEM_T2_DROP_ON_MATCH: u32 = 1 << 31;
809pub const GEM_COMPARE_C_ENABLE: u32 = 1 << 30;
810pub const GEM_COMPARE_C: u32 = 0xF << 25;
811pub const GEM_COMPARE_B_ENABLE: u32 = 1 << 24;
812pub const GEM_COMPARE_B: u32 = 0xF << 19;
813pub const GEM_COMPARE_A_ENABLE: u32 = 1 << 18;
814pub const GEM_COMPARE_A: u32 = 0xF << 13;
815pub const GEM_ETHERTYPE_ENABLE: u32 = 1 << 12;
816pub const GEM_ETHERTYPE_REG_INDEX: u32 = 0x3F << 9;
817pub const GEM_VLAN_ENABLE: u32 = 1 << 8;
818pub const GEM_VLAN_PRIORITY: u32 = 0xF << 4;
819
820pub const GEM_COMPARE_C_SHIFT: u32 = 25;
821pub const GEM_COMPARE_B_SHIFT: u32 = 19;
822pub const GEM_COMPARE_A_SHIFT: u32 = 13;
823pub const GEM_ETHERTYPE_REG_INDEX_SHIFT: u32 = 9;
824pub const GEM_VLAN_PRIORITY_SHIFT: u32 = 4;
825
826/* General MAC TX Schedule Control register bit definitions */
827
828pub const GEM_TX_SCHED_Q3: u32 = 1 << 6 | 1 << 7;
829pub const GEM_TX_SCHED_Q2: u32 = 1 << 4 | 1 << 5;
830pub const GEM_TX_SCHED_Q1: u32 = 1 << 2 | 1 << 3;
831pub const GEM_TX_SCHED_Q0: u32 = 1 << 0 | 1 << 1;
832
833/* General MAC TX Bandwidth Rate Limit Queue 0 to 3 register bit definitions */
834
835pub const GEM_DWRR_ETS_WEIGHT_Q3: u32 = 0xFF << 24;
836pub const GEM_DWRR_ETS_WEIGHT_Q2: u32 = 0xFF << 16;
837pub const GEM_DWRR_ETS_WEIGHT_Q1: u32 = 0xFF << 8;
838pub const GEM_DWRR_ETS_WEIGHT_Q0: u32 = 0xFF;
839
840/* General MAC TX Queue Segment Alloc Queue 0 to 3 register bit definitions */
841
842pub const GEM_SEGMENT_ALLOC_Q3: u32 = 1 << 12 | 1 << 13 | 1 << 14;
843pub const GEM_SEGMENT_ALLOC_Q2: u32 = 1 << 8 | 1 << 9 | 1 << 10;
844pub const GEM_SEGMENT_ALLOC_Q1: u32 = 1 << 4 | 1 << 5 | 1 << 6;
845pub const GEM_SEGMENT_ALLOC_Q0: u32 = 1 << 0 | 1 << 1 | 1 << 2;
846
847/* General MAC Screening Type 2 Ethertype Reg 0 register bit definitions */
848
849pub const GEM_COMPARE_VALUE: u32 = 0xFFFF;
850
851/* General MAC Type 2 Compare 0 Word 0 register bit definitions */
852/* eMAC Type 2 Compare 0 Word 0 register bit definitions */
853/* eMAC Type 2 Compare 1 Word 0 register bit definitions */
854/* eMAC Type 2 Compare 2 Word 0 register bit definitions */
855/* eMAC Type 2 Compare 3 Word 0 register bit definitions */
856/* eMAC Type 2 Compare 4 Word 0 register bit definitions */
857/* eMAC Type 2 Compare 5 Word 0 register bit definitions */
858
859pub const GEM_W0_COMPARE_VALUE: u32 = 0xFFFF << 16;
860pub const GEM_W0_MASK_VALUE: u32 = 0xFFFF;
861
862/* General MAC Type 2 Compare 0 Word 1 register bit definitions */
863/* eMAC Type 2 Compare 0 Word 1 register bit definitions */
864/* eMAC Type 2 Compare 1 Word 1 register bit definitions */
865/* eMAC Type 2 Compare 2 Word 1 register bit definitions */
866/* eMAC Type 2 Compare 3 Word 1 register bit definitions */
867/* eMAC Type 2 Compare 4 Word 1 register bit definitions */
868/* eMAC Type 2 Compare 5 Word 1 register bit definitions */
869
870pub const GEM_COMPARE_VLAN_ID: u32 = 1 << 10;
871pub const GEM_DISABLE_MASK: u32 = 1 << 9;
872pub const GEM_COMPARE_OFFSET: u32 = 1 << 7 | 1 << 8;
873pub const GEM_COMPARE_S_TAG: u32 = 1 << 7;
874pub const GEM_OFFSET_VALUE: u32 = 0x7F;
875
876pub const GEM_COMPARE_OFFSET_SHIFT: u32 = 7;
877
878/* General MAC Enst Start Time Queue 0 register bit definitions */
879/* General MAC Enst Start Time Queue 1 register bit definitions */
880/* General MAC Enst Start Time Queue 2 register bit definitions */
881/* General MAC Enst Start Time Queue 3 register bit definitions */
882/* eMAC Enst Start Time register bit definitions */
883
884pub const GEM_START_TIME_SEC: u32 = 1 << 30 | 1 << 31;
885pub const GEM_START_TIME_NSEC: u32 = 0x3FFFFFFF;
886
887/* General MAC Enst Start Time Queue 0 register bit definitions */
888/* General MAC Enst Start Time Queue 1 register bit definitions */
889/* General MAC Enst Start Time Queue 2 register bit definitions */
890/* General MAC Enst Start Time Queue 3 register bit definitions */
891/* General MAC Enst Off Time Queue 0 register bit definitions */
892/* General MAC Enst Off Time Queue 1 register bit definitions */
893/* General MAC Enst Off Time Queue 2 register bit definitions */
894/* General MAC Enst Off Time Queue 3 register bit definitions */
895/* eMAC Enst Start Time register bit definitions */
896/* eMAC Enst Off Time register bit definitions */
897
898pub const GEM_ON_OFF_TIME: u32 = 0x1FFFF;
899
900/* General MAC Enst Control register bit definitions */
901/* eMAC Enst Control register bit definitions */
902
903pub const GEM_ENST_DISABLE_Q_3: u32 = 1 << 19;
904pub const GEM_ENST_DISABLE_Q_2: u32 = 1 << 18;
905pub const GEM_ENST_DISABLE_Q_1: u32 = 1 << 17;
906pub const GEM_ENST_DISABLE_Q_0: u32 = 1 << 16;
907pub const GEM_ENST_ENABLE_Q_3: u32 = 1 << 3;
908pub const GEM_ENST_ENABLE_Q_2: u32 = 1 << 2;
909pub const GEM_ENST_ENABLE_Q_1: u32 = 1 << 1;
910pub const GEM_ENST_ENABLE_Q_0: u32 = 1 << 0;
911
912/* General MAC MMSL Control register bit definitions */
913
914pub const GEM_MMSL_DEBUG_MODE: u32 = 1 << 6;
915pub const GEM_ROUTE_RX_TO_PMAC: u32 = 1 << 5;
916pub const GEM_RESTART_VER: u32 = 1 << 4;
917pub const GEM_PRE_ENABLE: u32 = 1 << 3;
918pub const GEM_VERIFY_DISABLE: u32 = 1 << 2;
919pub const GEM_ADD_FRAG_SIZE: u32 = 1 << 1 | 1 << 0;
920
921/* General MAC MMSL Status register bit definitions */
922
923pub const GEM_SMD_ERROR: u32 = 1 << 10;
924pub const GEM_FRER_COUNT_ERR: u32 = 1 << 9;
925pub const GEM_SMDC_ERROR: u32 = 1 << 8;
926pub const GEM_SMDS_ERROR: u32 = 1 << 7;
927pub const GEM_RCV_V_ERROR: u32 = 1 << 6;
928pub const GEM_RCV_R_ERROR: u32 = 1 << 5;
929pub const GEM_VERIFY_STATUS: u32 = 1 << 4 | 1 << 5 | 1 << 6;
930pub const GEM_RESPOND_STATUS: u32 = 1 << 1;
931pub const GEM_PRE_ACTIVE: u32 = 1 << 0;
932
933pub const GEM_VERIFY_STATUS_SHIFT: u32 = 2;
934
935pub const GEM_VERIFY_INIT: u32 = 0x00;
936pub const GEM_VERIFY_IDLE: u32 = 0x01;
937pub const GEM_VERIFY_SEND: u32 = 0x02;
938pub const GEM_VERIFY_WAIT: u32 = 0x03;
939pub const GEM_VERIFY_DONE_OK: u32 = 0x04;
940pub const GEM_VERIFY_DONE_FAIL: u32 = 0x05;
941
942/* General MAC MMSL Error Stats register bit definitions */
943
944pub const GEM_SMD_ERR_COUNT: u32 = 0xFF << 16;
945pub const GEM_ASS_ERR_COUNT: u32 = 0xFF;
946
947pub const GEM_SMD_ERR_COUNT_SHIFT: u32 = 16;
948
949/* General MAC MMSL Ass OK Count register bit definitions */
950
951pub const GEM_ASS_OK_COUNT: u32 = 0x1FFFF;
952
953/* General MAC MMSL Frag Count RX register bit definitions */
954/* General MAC MMSL Frag Count TX register bit definitions */
955
956pub const GEM_FRAG_COUNT: u32 = 0x1FFFF;
957
958/* General MAC MMSL Interrupt Status register bit definitions */
959/* General MAC MMSL Interrupt Enable register bit definitions */
960/* General MAC MMSL Interrupt Disable register bit definitions */
961/* General MAC MMSL Interrupt Mask register bit definitions */
962
963pub const GEM_INT_SMD_ERROR: u32 = 1 << 5;
964pub const GEM_INT_FRER_COUNT_ERR: u32 = 1 << 4;
965pub const GEM_INT_SMDC_ERROR: u32 = 1 << 3;
966pub const GEM_INT_SMDS_ERROR: u32 = 1 << 2;
967pub const GEM_INT_RCV_V_ERROR: u32 = 1 << 1;
968pub const GEM_INT_RCV_R_ERROR: u32 = 1 << 0;
mpfs_pac/ethernet.rs

mpfs_pac/
ethernet.rs
