[−][src]Module moore_vhdl_syntax::lexer
A VHDL lexer. This module implements lexical analysis of VHDL source files. It converts a stream of input bytes into a stream of language tokens such as identifiers, literals, and symbols.
Modules
bundler | |
categorizer | |
token | |
tokenizer |
Structs
Lexer | A VHDL lexer. Converts a stream of bytes to VHDL tokens. Emits errors backwards up the pipeline. |