moondancer_pac/generated/leds/
set_clr.rs

1#[doc = "Register `SetClr` reader"]
2pub type R = crate::R<SET_CLR_SPEC>;
3#[doc = "Register `SetClr` writer"]
4pub type W = crate::W<SET_CLR_SPEC>;
5#[doc = "Field `pin_0_set` writer - pin_0_set field"]
6pub type PIN_0_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `pin_0_clr` writer - pin_0_clr field"]
8pub type PIN_0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `pin_1_set` writer - pin_1_set field"]
10pub type PIN_1_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `pin_1_clr` writer - pin_1_clr field"]
12pub type PIN_1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `pin_2_set` writer - pin_2_set field"]
14pub type PIN_2_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `pin_2_clr` writer - pin_2_clr field"]
16pub type PIN_2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `pin_3_set` writer - pin_3_set field"]
18pub type PIN_3_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `pin_3_clr` writer - pin_3_clr field"]
20pub type PIN_3_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `pin_4_set` writer - pin_4_set field"]
22pub type PIN_4_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `pin_4_clr` writer - pin_4_clr field"]
24pub type PIN_4_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `pin_5_set` writer - pin_5_set field"]
26pub type PIN_5_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `pin_5_clr` writer - pin_5_clr field"]
28pub type PIN_5_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl W {
30    #[doc = "Bit 0 - pin_0_set field"]
31    #[inline(always)]
32    pub fn pin_0_set(&mut self) -> PIN_0_SET_W<SET_CLR_SPEC> {
33        PIN_0_SET_W::new(self, 0)
34    }
35    #[doc = "Bit 1 - pin_0_clr field"]
36    #[inline(always)]
37    pub fn pin_0_clr(&mut self) -> PIN_0_CLR_W<SET_CLR_SPEC> {
38        PIN_0_CLR_W::new(self, 1)
39    }
40    #[doc = "Bit 2 - pin_1_set field"]
41    #[inline(always)]
42    pub fn pin_1_set(&mut self) -> PIN_1_SET_W<SET_CLR_SPEC> {
43        PIN_1_SET_W::new(self, 2)
44    }
45    #[doc = "Bit 3 - pin_1_clr field"]
46    #[inline(always)]
47    pub fn pin_1_clr(&mut self) -> PIN_1_CLR_W<SET_CLR_SPEC> {
48        PIN_1_CLR_W::new(self, 3)
49    }
50    #[doc = "Bit 4 - pin_2_set field"]
51    #[inline(always)]
52    pub fn pin_2_set(&mut self) -> PIN_2_SET_W<SET_CLR_SPEC> {
53        PIN_2_SET_W::new(self, 4)
54    }
55    #[doc = "Bit 5 - pin_2_clr field"]
56    #[inline(always)]
57    pub fn pin_2_clr(&mut self) -> PIN_2_CLR_W<SET_CLR_SPEC> {
58        PIN_2_CLR_W::new(self, 5)
59    }
60    #[doc = "Bit 6 - pin_3_set field"]
61    #[inline(always)]
62    pub fn pin_3_set(&mut self) -> PIN_3_SET_W<SET_CLR_SPEC> {
63        PIN_3_SET_W::new(self, 6)
64    }
65    #[doc = "Bit 7 - pin_3_clr field"]
66    #[inline(always)]
67    pub fn pin_3_clr(&mut self) -> PIN_3_CLR_W<SET_CLR_SPEC> {
68        PIN_3_CLR_W::new(self, 7)
69    }
70    #[doc = "Bit 8 - pin_4_set field"]
71    #[inline(always)]
72    pub fn pin_4_set(&mut self) -> PIN_4_SET_W<SET_CLR_SPEC> {
73        PIN_4_SET_W::new(self, 8)
74    }
75    #[doc = "Bit 9 - pin_4_clr field"]
76    #[inline(always)]
77    pub fn pin_4_clr(&mut self) -> PIN_4_CLR_W<SET_CLR_SPEC> {
78        PIN_4_CLR_W::new(self, 9)
79    }
80    #[doc = "Bit 10 - pin_5_set field"]
81    #[inline(always)]
82    pub fn pin_5_set(&mut self) -> PIN_5_SET_W<SET_CLR_SPEC> {
83        PIN_5_SET_W::new(self, 10)
84    }
85    #[doc = "Bit 11 - pin_5_clr field"]
86    #[inline(always)]
87    pub fn pin_5_clr(&mut self) -> PIN_5_CLR_W<SET_CLR_SPEC> {
88        PIN_5_CLR_W::new(self, 11)
89    }
90}
91#[doc = "Output set/clear register. This :class:`csr.Register` contains an array of ``pin_count`` write-only fields. Each field is 2-bit wide; writing it can modify its associated :class:`~Peripheral.Output` field as a side-effect. If ``pin_count`` is 8, then the register has the following fields: .. bitfield:: :bits: 16 \\[ { \"name\": \"pin\\[0\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[1\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[2\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[3\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[4\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[5\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[6\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[7\\]\", \"bits\": 2, \"attr\": \"W\" }, \\]
92- Writing `0b01` to a field sets its associated :class:`~Peripheral.Output` field. - Writing `0b10` to a field clears its associated :class:`~Peripheral.Output` field. - Writing `0b00` or `0b11` to a field has no side-effect. Parameters ---------- pin_count : :class:`int` Number of GPIO pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`set_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`set_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
93pub struct SET_CLR_SPEC;
94impl crate::RegisterSpec for SET_CLR_SPEC {
95    type Ux = u16;
96}
97#[doc = "`read()` method returns [`set_clr::R`](R) reader structure"]
98impl crate::Readable for SET_CLR_SPEC {}
99#[doc = "`write(|w| ..)` method takes [`set_clr::W`](W) writer structure"]
100impl crate::Writable for SET_CLR_SPEC {
101    type Safety = crate::Unsafe;
102    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
103    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
104}
105#[doc = "`reset()` method sets SetClr to value 0"]
106impl crate::Resettable for SET_CLR_SPEC {
107    const RESET_VALUE: u16 = 0;
108}
moondancer_pac/generated/leds/set_clr.rs

moondancer_pac/generated/leds/
set_clr.rs
