moondancer_pac/
cpu.rs

1//! Support for various vendor defined softcore extensions.
2
3pub mod minerva {
4
5    pub mod register {
6        //! Micro-architecture specific CSR extensions for the Minerva RISC-V
7        //! soft processor.
8        //!
9        //! See: [ISA definition](https://github.com/minerva-cpu/minerva/blob/master/minerva/isa.py)
10        //!
11        //! These are somewhat weird because peripheral irq enable (0x330)
12        //! overlaps with the Machine Counter Setup `mhpmevent16`
13        //! performance-monitoring event selector.
14        //!
15        //! See: [Chapter 2 - Control and Status Registers](https://riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf)
16
17        /// Machine IRQ Mask
18        pub mod mim {
19            crate::macros::read_csr_as_usize!(0x330);
20            crate::macros::write_csr_as_usize!(0x330);
21        }
22
23        /// Machine IRQ Pending
24        pub mod mip {
25            crate::macros::read_csr_as_usize!(0x360);
26        }
27    }
28}
29
30pub mod vexriscv {
31
32    #[inline(always)]
33    pub fn flush_icache() {
34        unsafe {
35            core::arch::asm!(".word(0x100f)", "nop", "nop", "nop", "nop", "nop",);
36        }
37    }
38    #[inline(always)]
39    pub fn flush_dcache() {
40        unsafe {
41            core::arch::asm!(".word(0x500f)");
42        }
43    }
44
45    pub mod register {
46        //! Micro-architecture specific CSR extensions for the `VexRiscv` RISC-V
47        //! soft processor.
48        //!
49        //! See: [ExternalInterruptArrayPlugin.scala](https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala)
50
51        /// Machine IRQ Mask
52        pub mod mim {
53            crate::macros::read_csr_as_usize!(0xBC0);
54            crate::macros::write_csr_as_usize!(0xBC0);
55        }
56
57        /// Machine IRQ Pending
58        pub mod mip {
59            crate::macros::read_csr_as_usize!(0xFC0);
60        }
61
62        /// Supervisor IRQ Mask
63        pub mod sim {
64            crate::macros::read_csr_as_usize!(0x9C0);
65            crate::macros::write_csr_as_usize!(0x9C0);
66        }
67
68        /// Supervisor IRQ Pending
69        pub mod sip {
70            crate::macros::read_csr_as_usize!(0xDC0);
71        }
72
73        /// Data Cache Info
74        pub mod dci {
75            crate::macros::read_csr_as_usize!(0xCC0);
76        }
77    }
78}
moondancer_pac/cpu.rs

moondancer_pac/
cpu.rs
