moondancer_pac/generated/usb0_ep_out/
prime.rs

1#[doc = "Register `prime` reader"]
2pub type R = crate::R<PRIME_SPEC>;
3#[doc = "Register `prime` writer"]
4pub type W = crate::W<PRIME_SPEC>;
5#[doc = "Field `primed` writer - primed field"]
6pub type PRIMED_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `_0` reader - _0 field"]
8pub type _0_R = crate::FieldReader;
9#[doc = "Field `_0` writer - _0 field"]
10pub type _0_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
11impl R {
12    #[doc = "Bits 1:7 - _0 field"]
13    #[inline(always)]
14    pub fn _0(&self) -> _0_R {
15        _0_R::new((self.bits >> 1) & 0x7f)
16    }
17}
18impl W {
19    #[doc = "Bit 0 - primed field"]
20    #[inline(always)]
21    pub fn primed(&mut self) -> PRIMED_W<PRIME_SPEC> {
22        PRIMED_W::new(self, 0)
23    }
24    #[doc = "Bits 1:7 - _0 field"]
25    #[inline(always)]
26    pub fn _0(&mut self) -> _0_W<PRIME_SPEC> {
27        _0_W::new(self, 1)
28    }
29}
30#[doc = "Prime register primed: Controls \"priming\" an out endpoint. To receive data on any endpoint, the CPU must first select the endpoint with the `epno` register; and then write a '1' into the prime and enable register. This prepares our FIFO to receive data; and the next OUT transaction will be captured into the FIFO. When a transaction is complete, the `enable` bit is reset; the `prime` is not. This effectively means that `enable` controls receiving on _any_ of the primed endpoints; while `prime` can be used to build a collection of endpoints willing to participate in receipt. Note that this does not apply to the control endpoint. Once the control endpoint has received a packet it will be un-primed and need to be re-primed before it can receive again. This is to ensure that we can establish an order on the receipt of the setup packet and any associated data. Only one transaction / data packet is captured per `enable` write; repeated enabling is necessary to capture multiple packets.\n\nYou can [`read`](crate::Reg::read) this register and get [`prime::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prime::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31pub struct PRIME_SPEC;
32impl crate::RegisterSpec for PRIME_SPEC {
33    type Ux = u8;
34}
35#[doc = "`read()` method returns [`prime::R`](R) reader structure"]
36impl crate::Readable for PRIME_SPEC {}
37#[doc = "`write(|w| ..)` method takes [`prime::W`](W) writer structure"]
38impl crate::Writable for PRIME_SPEC {
39    type Safety = crate::Unsafe;
40    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
41    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
42}
43#[doc = "`reset()` method sets prime to value 0"]
44impl crate::Resettable for PRIME_SPEC {
45    const RESET_VALUE: u8 = 0;
46}
moondancer_pac/generated/usb0_ep_out/prime.rs

moondancer_pac/generated/usb0_ep_out/
prime.rs
