moondancer_pac/generated/gpio1/
set_clr.rs

1#[doc = "Register `SetClr` reader"]
2pub type R = crate::R<SET_CLR_SPEC>;
3#[doc = "Register `SetClr` writer"]
4pub type W = crate::W<SET_CLR_SPEC>;
5#[doc = "Field `pin_0_set` writer - pin_0_set field"]
6pub type PIN_0_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `pin_0_clr` writer - pin_0_clr field"]
8pub type PIN_0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `pin_1_set` writer - pin_1_set field"]
10pub type PIN_1_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `pin_1_clr` writer - pin_1_clr field"]
12pub type PIN_1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `pin_2_set` writer - pin_2_set field"]
14pub type PIN_2_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `pin_2_clr` writer - pin_2_clr field"]
16pub type PIN_2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `pin_3_set` writer - pin_3_set field"]
18pub type PIN_3_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `pin_3_clr` writer - pin_3_clr field"]
20pub type PIN_3_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `pin_4_set` writer - pin_4_set field"]
22pub type PIN_4_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `pin_4_clr` writer - pin_4_clr field"]
24pub type PIN_4_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `pin_5_set` writer - pin_5_set field"]
26pub type PIN_5_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `pin_5_clr` writer - pin_5_clr field"]
28pub type PIN_5_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `pin_6_set` writer - pin_6_set field"]
30pub type PIN_6_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `pin_6_clr` writer - pin_6_clr field"]
32pub type PIN_6_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `pin_7_set` writer - pin_7_set field"]
34pub type PIN_7_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `pin_7_clr` writer - pin_7_clr field"]
36pub type PIN_7_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl W {
38    #[doc = "Bit 0 - pin_0_set field"]
39    #[inline(always)]
40    pub fn pin_0_set(&mut self) -> PIN_0_SET_W<SET_CLR_SPEC> {
41        PIN_0_SET_W::new(self, 0)
42    }
43    #[doc = "Bit 1 - pin_0_clr field"]
44    #[inline(always)]
45    pub fn pin_0_clr(&mut self) -> PIN_0_CLR_W<SET_CLR_SPEC> {
46        PIN_0_CLR_W::new(self, 1)
47    }
48    #[doc = "Bit 2 - pin_1_set field"]
49    #[inline(always)]
50    pub fn pin_1_set(&mut self) -> PIN_1_SET_W<SET_CLR_SPEC> {
51        PIN_1_SET_W::new(self, 2)
52    }
53    #[doc = "Bit 3 - pin_1_clr field"]
54    #[inline(always)]
55    pub fn pin_1_clr(&mut self) -> PIN_1_CLR_W<SET_CLR_SPEC> {
56        PIN_1_CLR_W::new(self, 3)
57    }
58    #[doc = "Bit 4 - pin_2_set field"]
59    #[inline(always)]
60    pub fn pin_2_set(&mut self) -> PIN_2_SET_W<SET_CLR_SPEC> {
61        PIN_2_SET_W::new(self, 4)
62    }
63    #[doc = "Bit 5 - pin_2_clr field"]
64    #[inline(always)]
65    pub fn pin_2_clr(&mut self) -> PIN_2_CLR_W<SET_CLR_SPEC> {
66        PIN_2_CLR_W::new(self, 5)
67    }
68    #[doc = "Bit 6 - pin_3_set field"]
69    #[inline(always)]
70    pub fn pin_3_set(&mut self) -> PIN_3_SET_W<SET_CLR_SPEC> {
71        PIN_3_SET_W::new(self, 6)
72    }
73    #[doc = "Bit 7 - pin_3_clr field"]
74    #[inline(always)]
75    pub fn pin_3_clr(&mut self) -> PIN_3_CLR_W<SET_CLR_SPEC> {
76        PIN_3_CLR_W::new(self, 7)
77    }
78    #[doc = "Bit 8 - pin_4_set field"]
79    #[inline(always)]
80    pub fn pin_4_set(&mut self) -> PIN_4_SET_W<SET_CLR_SPEC> {
81        PIN_4_SET_W::new(self, 8)
82    }
83    #[doc = "Bit 9 - pin_4_clr field"]
84    #[inline(always)]
85    pub fn pin_4_clr(&mut self) -> PIN_4_CLR_W<SET_CLR_SPEC> {
86        PIN_4_CLR_W::new(self, 9)
87    }
88    #[doc = "Bit 10 - pin_5_set field"]
89    #[inline(always)]
90    pub fn pin_5_set(&mut self) -> PIN_5_SET_W<SET_CLR_SPEC> {
91        PIN_5_SET_W::new(self, 10)
92    }
93    #[doc = "Bit 11 - pin_5_clr field"]
94    #[inline(always)]
95    pub fn pin_5_clr(&mut self) -> PIN_5_CLR_W<SET_CLR_SPEC> {
96        PIN_5_CLR_W::new(self, 11)
97    }
98    #[doc = "Bit 12 - pin_6_set field"]
99    #[inline(always)]
100    pub fn pin_6_set(&mut self) -> PIN_6_SET_W<SET_CLR_SPEC> {
101        PIN_6_SET_W::new(self, 12)
102    }
103    #[doc = "Bit 13 - pin_6_clr field"]
104    #[inline(always)]
105    pub fn pin_6_clr(&mut self) -> PIN_6_CLR_W<SET_CLR_SPEC> {
106        PIN_6_CLR_W::new(self, 13)
107    }
108    #[doc = "Bit 14 - pin_7_set field"]
109    #[inline(always)]
110    pub fn pin_7_set(&mut self) -> PIN_7_SET_W<SET_CLR_SPEC> {
111        PIN_7_SET_W::new(self, 14)
112    }
113    #[doc = "Bit 15 - pin_7_clr field"]
114    #[inline(always)]
115    pub fn pin_7_clr(&mut self) -> PIN_7_CLR_W<SET_CLR_SPEC> {
116        PIN_7_CLR_W::new(self, 15)
117    }
118}
119#[doc = "Output set/clear register. This :class:`csr.Register` contains an array of ``pin_count`` write-only fields. Each field is 2-bit wide; writing it can modify its associated :class:`~Peripheral.Output` field as a side-effect. If ``pin_count`` is 8, then the register has the following fields: .. bitfield:: :bits: 16 \\[ { \"name\": \"pin\\[0\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[1\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[2\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[3\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[4\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[5\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[6\\]\", \"bits\": 2, \"attr\": \"W\" }, { \"name\": \"pin\\[7\\]\", \"bits\": 2, \"attr\": \"W\" }, \\]
120- Writing `0b01` to a field sets its associated :class:`~Peripheral.Output` field. - Writing `0b10` to a field clears its associated :class:`~Peripheral.Output` field. - Writing `0b00` or `0b11` to a field has no side-effect. Parameters ---------- pin_count : :class:`int` Number of GPIO pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`set_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`set_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
121pub struct SET_CLR_SPEC;
122impl crate::RegisterSpec for SET_CLR_SPEC {
123    type Ux = u16;
124}
125#[doc = "`read()` method returns [`set_clr::R`](R) reader structure"]
126impl crate::Readable for SET_CLR_SPEC {}
127#[doc = "`write(|w| ..)` method takes [`set_clr::W`](W) writer structure"]
128impl crate::Writable for SET_CLR_SPEC {
129    type Safety = crate::Unsafe;
130    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
131    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
132}
133#[doc = "`reset()` method sets SetClr to value 0"]
134impl crate::Resettable for SET_CLR_SPEC {
135    const RESET_VALUE: u16 = 0;
136}
moondancer_pac/generated/gpio1/set_clr.rs

moondancer_pac/generated/gpio1/
set_clr.rs
