Crate mm32f5

Source
Expand description

Peripheral access API for MM32F5277E microcontrollers (generated using svd2rust v0.28.0 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports§

pub use self::adc1 as adc2;
pub use self::dma1 as dma2;
pub use self::flexcan1 as flexcan2;
pub use self::gpioa as gpiob;
pub use self::gpioa as gpioc;
pub use self::gpioa as gpiod;
pub use self::gpioa as gpioe;
pub use self::gpioa as gpiof;
pub use self::gpioa as gpiog;
pub use self::gpioa as gpioh;
pub use self::gpioa as gpioi;
pub use self::i2c1 as i2c2;
pub use self::spi1 as spi2;
pub use self::spi1 as spi3;
pub use self::tim1 as tim8;
pub use self::tim2 as tim5;
pub use self::tim3 as tim4;
pub use self::tim6 as tim7;
pub use self::uart1 as uart2;
pub use self::uart1 as uart3;
pub use self::uart1 as uart4;
pub use self::uart1 as uart5;
pub use self::uart1 as uart6;
pub use self::uart1 as uart7;

Modules§

adc1
ADC1
bkp
BKP
comp
COMP
cordic
CORDIC
crc
CRC
crs
CRS
dac
DAC
dbgmcu
DBGMCU
dma1
DMA1
enet
ENET
exti
EXTI
flash
FLASH
flexcan1
FLEXCAN1
fsmc
FSMC
generic
Common register and bit access and modify traits
gpioa
GPIOA
i2c1
I2C1
iwdg
IWDG
lpt
LPT
lpu
LPU
mds
MDS
pwr
PWR
qspi
QSPI
rcc
RCC
rtc
RTC
spi1
SPI1
syscfg
SYSCFG
tim1
TIM1
tim2
TIM2
tim3
TIM3
tim6
TIM6
uart1
UART1
usb
USB
wwdg
WWDG

Structs§

ADC1
ADC1
ADC2
ADC2
BKP
BKP
CBP
Cache and branch predictor maintenance operations
COMP
COMP
CORDIC
CORDIC
CPUID
CPUID
CRC
CRC
CRS
CRS
CorePeripherals
Core peripherals
DAC
DAC
DBGMCU
DBGMCU
DCB
Debug Control Block
DMA1
DMA1
DMA2
DMA2
DWT
Data Watchpoint and Trace unit
ENET
ENET
EXTI
EXTI
FLASH
FLASH
FLEXCAN1
FLEXCAN1
FLEXCAN2
FLEXCAN2
FPB
Flash Patch and Breakpoint unit
FSMC
FSMC
GPIOA
GPIOA
GPIOB
GPIOB
GPIOC
GPIOC
GPIOD
GPIOD
GPIOE
GPIOE
GPIOF
GPIOF
GPIOG
GPIOG
GPIOH
GPIOH
GPIOI
GPIOI
I2C1
I2C1
I2C2
I2C2
ITM
Instrumentation Trace Macrocell
IWDG
IWDG
LPT
LPT
LPU
LPU
MDS
MDS
MPU
Memory Protection Unit
NVIC
Nested Vector Interrupt Controller
PWR
PWR
Peripherals
All the peripherals.
QSPI
QSPI
RCC
RCC
RTC
RTC
SCB
System Control Block
SPI1
SPI1
SPI2
SPI2
SPI3
SPI3
SYSCFG
SYSCFG
SYST
SysTick: System Timer
TIM1
TIM1
TIM2
TIM2
TIM3
TIM3
TIM4
TIM4
TIM5
TIM5
TIM6
TIM6
TIM7
TIM7
TIM8
TIM8
TPIU
Trace Port Interface Unit
UART1
UART1
UART2
UART2
UART3
UART3
UART4
UART4
UART5
UART5
UART6
UART6
UART7
UART7
USB
USB
WWDG
WWDG

Enums§

Interrupt
Enumeration of all the interrupts.

Constants§

NVIC_PRIO_BITS
Number available in the NVIC for configuring priority