mm32f3270_pac/cache/
ccr.rs

1#[doc = "Register `CCR` reader"]
2pub struct R(crate::R<CCR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CCR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CCR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CCR` writer"]
17pub struct W(crate::W<CCR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CCR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CCR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CCR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `EN` reader - Enable cache"]
38pub type EN_R = crate::BitReader<bool>;
39#[doc = "Field `EN` writer - Enable cache"]
40pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
41#[doc = "Field `INV_REQ` reader - Invalid manual set request"]
42pub type INV_REQ_R = crate::BitReader<bool>;
43#[doc = "Field `INV_REQ` writer - Invalid manual set request"]
44pub type INV_REQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
45#[doc = "Field `POW_REQ` reader - Manual SRAM power request"]
46pub type POW_REQ_R = crate::BitReader<bool>;
47#[doc = "Field `POW_REQ` writer - Manual SRAM power request"]
48pub type POW_REQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
49#[doc = "Field `SET_MAN_POW` reader - Set manual or automatic SRAM power request"]
50pub type SET_MAN_POW_R = crate::BitReader<bool>;
51#[doc = "Field `SET_MAN_POW` writer - Set manual or automatic SRAM power request"]
52pub type SET_MAN_POW_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
53#[doc = "Field `SET_MAN_INV` reader - Set manual or automatic invalid"]
54pub type SET_MAN_INV_R = crate::BitReader<bool>;
55#[doc = "Field `SET_MAN_INV` writer - Set manual or automatic invalid"]
56pub type SET_MAN_INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
57#[doc = "Field `SET_PREFETCH` reader - Prefetch value"]
58pub type SET_PREFETCH_R = crate::BitReader<bool>;
59#[doc = "Field `SET_PREFETCH` writer - Prefetch value"]
60pub type SET_PREFETCH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
61#[doc = "Field `STATISTIC_EN` reader - Enable statistics"]
62pub type STATISTIC_EN_R = crate::BitReader<bool>;
63#[doc = "Field `STATISTIC_EN` writer - Enable statistics"]
64pub type STATISTIC_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
65impl R {
66    #[doc = "Bit 0 - Enable cache"]
67    #[inline(always)]
68    pub fn en(&self) -> EN_R {
69        EN_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1 - Invalid manual set request"]
72    #[inline(always)]
73    pub fn inv_req(&self) -> INV_REQ_R {
74        INV_REQ_R::new(((self.bits >> 1) & 1) != 0)
75    }
76    #[doc = "Bit 2 - Manual SRAM power request"]
77    #[inline(always)]
78    pub fn pow_req(&self) -> POW_REQ_R {
79        POW_REQ_R::new(((self.bits >> 2) & 1) != 0)
80    }
81    #[doc = "Bit 3 - Set manual or automatic SRAM power request"]
82    #[inline(always)]
83    pub fn set_man_pow(&self) -> SET_MAN_POW_R {
84        SET_MAN_POW_R::new(((self.bits >> 3) & 1) != 0)
85    }
86    #[doc = "Bit 4 - Set manual or automatic invalid"]
87    #[inline(always)]
88    pub fn set_man_inv(&self) -> SET_MAN_INV_R {
89        SET_MAN_INV_R::new(((self.bits >> 4) & 1) != 0)
90    }
91    #[doc = "Bit 5 - Prefetch value"]
92    #[inline(always)]
93    pub fn set_prefetch(&self) -> SET_PREFETCH_R {
94        SET_PREFETCH_R::new(((self.bits >> 5) & 1) != 0)
95    }
96    #[doc = "Bit 6 - Enable statistics"]
97    #[inline(always)]
98    pub fn statistic_en(&self) -> STATISTIC_EN_R {
99        STATISTIC_EN_R::new(((self.bits >> 6) & 1) != 0)
100    }
101}
102impl W {
103    #[doc = "Bit 0 - Enable cache"]
104    #[inline(always)]
105    #[must_use]
106    pub fn en(&mut self) -> EN_W<0> {
107        EN_W::new(self)
108    }
109    #[doc = "Bit 1 - Invalid manual set request"]
110    #[inline(always)]
111    #[must_use]
112    pub fn inv_req(&mut self) -> INV_REQ_W<1> {
113        INV_REQ_W::new(self)
114    }
115    #[doc = "Bit 2 - Manual SRAM power request"]
116    #[inline(always)]
117    #[must_use]
118    pub fn pow_req(&mut self) -> POW_REQ_W<2> {
119        POW_REQ_W::new(self)
120    }
121    #[doc = "Bit 3 - Set manual or automatic SRAM power request"]
122    #[inline(always)]
123    #[must_use]
124    pub fn set_man_pow(&mut self) -> SET_MAN_POW_W<3> {
125        SET_MAN_POW_W::new(self)
126    }
127    #[doc = "Bit 4 - Set manual or automatic invalid"]
128    #[inline(always)]
129    #[must_use]
130    pub fn set_man_inv(&mut self) -> SET_MAN_INV_W<4> {
131        SET_MAN_INV_W::new(self)
132    }
133    #[doc = "Bit 5 - Prefetch value"]
134    #[inline(always)]
135    #[must_use]
136    pub fn set_prefetch(&mut self) -> SET_PREFETCH_W<5> {
137        SET_PREFETCH_W::new(self)
138    }
139    #[doc = "Bit 6 - Enable statistics"]
140    #[inline(always)]
141    #[must_use]
142    pub fn statistic_en(&mut self) -> STATISTIC_EN_W<6> {
143        STATISTIC_EN_W::new(self)
144    }
145    #[doc = "Writes raw bits to the register."]
146    #[inline(always)]
147    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
148        self.0.bits(bits);
149        self
150    }
151}
152#[doc = "Configuration and control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"]
153pub struct CCR_SPEC;
154impl crate::RegisterSpec for CCR_SPEC {
155    type Ux = u32;
156}
157#[doc = "`read()` method returns [ccr::R](R) reader structure"]
158impl crate::Readable for CCR_SPEC {
159    type Reader = R;
160}
161#[doc = "`write(|w| ..)` method takes [ccr::W](W) writer structure"]
162impl crate::Writable for CCR_SPEC {
163    type Writer = W;
164    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
165    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
166}
167#[doc = "`reset()` method sets CCR to value 0x40"]
168impl crate::Resettable for CCR_SPEC {
169    const RESET_VALUE: Self::Ux = 0x40;
170}
mm32f3270_pac/cache/ccr.rs

mm32f3270_pac/cache/
ccr.rs
