[−][src]Enum mkl25z4::adc0::sc1::ADCH_A
Input channel select
Value on reset: 31
Variants
0: When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
1: When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
2: When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
3: When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
4: When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
5: When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
6: When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
7: When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
8: When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
9: When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
10: When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
11: When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
12: When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
13: When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
14: When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
15: When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
16: When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
17: When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
18: When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
19: When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
20: When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
21: When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
22: When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
23: When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
26: When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
27: When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
29: When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
30: When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
31: Module is disabled.
Trait Implementations
impl Clone for ADCH_A
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fn clone(&self) -> ADCH_A
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fn clone_from(&mut self, source: &Self)
1.0.0[src]
impl Copy for ADCH_A
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impl Debug for ADCH_A
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impl From<ADCH_A> for u8
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impl PartialEq<ADCH_A> for ADCH_A
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impl StructuralPartialEq for ADCH_A
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Auto Trait Implementations
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
fn borrow_mut(&mut self) -> &mut T
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impl<T> From<T> for T
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impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T> Same<T> for T
type Output = T
Should always be Self
impl<T, U> TryFrom<U> for T where
U: Into<T>,
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U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
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impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
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U: TryFrom<T>,