Type Definition mk66f18::usbphy::debug_set::W

type W = W<u32, DEBUG_SET>;

Writer for register DEBUG_SET

Methods

impl W

pub fn otgidpiolock(&mut self) -> OTGIDPIOLOCK_W

Bit 0 - Once OTG ID from USBPHY_STATUS_OTGID_STATUS is sampled, use this to hold the value

pub fn debug_interface_hold(&mut self) -> DEBUG_INTERFACE_HOLD_W

Bit 1 - Use holding registers to assist in timing for external UTMI interface.

pub fn hstpulldown(&mut self) -> HSTPULLDOWN_W

Bits 2:3 - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through USBPHY_DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line

pub fn enhstpulldown(&mut self) -> ENHSTPULLDOWN_W

Bits 4:5 - This bit field selects host pulldown overdrive mode

pub fn tx2rxcount(&mut self) -> TX2RXCOUNT_W

Bits 8:11 - Delay in between the end of transmit to the beginning of receive

pub fn entx2rxcount(&mut self) -> ENTX2RXCOUNT_W

Bit 12 - Set this bit to allow a countdown to transition in between TX and RX.

pub fn squelchresetcount(&mut self) -> SQUELCHRESETCOUNT_W

Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX.

pub fn ensquelchreset(&mut self) -> ENSQUELCHRESET_W

Bit 24 - Set bit to allow squelch to reset high-speed receive.

pub fn squelchresetlength(&mut self) -> SQUELCHRESETLENGTH_W

Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles.

pub fn host_resume_debug(&mut self) -> HOST_RESUME_DEBUG_W

Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - Gate Test Clocks