[−][src]Module mk66f18::usbphy::anactrl
USB PHY Analog Control Register
Structs
| DEV_PULLDOWN_W | Write proxy for field |
| EMPH_CUR_CTRL_W | Write proxy for field |
| EMPH_EN_W | Write proxy for field |
| EMPH_PULSE_CTRL_W | Write proxy for field |
| PFD_CLKGATE_W | Write proxy for field |
| PFD_CLK_SEL_W | Write proxy for field |
| PFD_FRAC_W | Write proxy for field |
| TESTCLK_SEL_W | Write proxy for field |
Enums
| DEV_PULLDOWN_A | Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins |
| EMPH_CUR_CTRL_A | Controls the amount of pre-emphasis current added for the High-Speed TX drivers after each data transition when the USBPHY_ANACTRL[EMPH_EN] bit is set high to 1'b1 |
| EMPH_EN_A | Enables pre-emphasis for the High-Speed TX drivers |
| EMPH_PULSE_CTRL_A | Controls pre-emphasis time duration for the High Speed TX drivers after each data transition when the USBPHY_ANACTRL[EMPH_EN] bit is set high to 1'b1 |
| PFD_CLKGATE_A | This bit field controls clock gating (disabling) for the PFD pfd_clk output for power savings when the PFD is not used |
| PFD_CLK_SEL_A | This bit field for the PFD selects the frequency relationship between the local pfd_clk output and the exported USB1PFDCLK |
Type Definitions
| DEV_PULLDOWN_R | Reader of field |
| EMPH_CUR_CTRL_R | Reader of field |
| EMPH_EN_R | Reader of field |
| EMPH_PULSE_CTRL_R | Reader of field |
| PFD_CLKGATE_R | Reader of field |
| PFD_CLK_SEL_R | Reader of field |
| PFD_FRAC_R | Reader of field |
| PFD_STABLE_R | Reader of field |
| R | Reader of register ANACTRL |
| TESTCLK_SEL_R | Reader of field |
| W | Writer for register ANACTRL |