mk66f18/spi1/
mcr.rs

1#[doc = "Reader of register MCR"]
2pub type R = crate::R<u32, super::MCR>;
3#[doc = "Writer for register MCR"]
4pub type W = crate::W<u32, super::MCR>;
5#[doc = "Register MCR `reset()`'s with value 0x4001"]
6impl crate::ResetValue for super::MCR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x4001
11    }
12}
13#[doc = "Halt\n\nValue on reset: 1"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15pub enum HALT_A {
16    #[doc = "0: Start transfers."]
17    _0,
18    #[doc = "1: Stop transfers."]
19    _1,
20}
21impl From<HALT_A> for bool {
22    #[inline(always)]
23    fn from(variant: HALT_A) -> Self {
24        match variant {
25            HALT_A::_0 => false,
26            HALT_A::_1 => true,
27        }
28    }
29}
30#[doc = "Reader of field `HALT`"]
31pub type HALT_R = crate::R<bool, HALT_A>;
32impl HALT_R {
33    #[doc = r"Get enumerated values variant"]
34    #[inline(always)]
35    pub fn variant(&self) -> HALT_A {
36        match self.bits {
37            false => HALT_A::_0,
38            true => HALT_A::_1,
39        }
40    }
41    #[doc = "Checks if the value of the field is `_0`"]
42    #[inline(always)]
43    pub fn is_0(&self) -> bool {
44        *self == HALT_A::_0
45    }
46    #[doc = "Checks if the value of the field is `_1`"]
47    #[inline(always)]
48    pub fn is_1(&self) -> bool {
49        *self == HALT_A::_1
50    }
51}
52#[doc = "Write proxy for field `HALT`"]
53pub struct HALT_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> HALT_W<'a> {
57    #[doc = r"Writes `variant` to the field"]
58    #[inline(always)]
59    pub fn variant(self, variant: HALT_A) -> &'a mut W {
60        {
61            self.bit(variant.into())
62        }
63    }
64    #[doc = "Start transfers."]
65    #[inline(always)]
66    pub fn _0(self) -> &'a mut W {
67        self.variant(HALT_A::_0)
68    }
69    #[doc = "Stop transfers."]
70    #[inline(always)]
71    pub fn _1(self) -> &'a mut W {
72        self.variant(HALT_A::_1)
73    }
74    #[doc = r"Sets the field bit"]
75    #[inline(always)]
76    pub fn set_bit(self) -> &'a mut W {
77        self.bit(true)
78    }
79    #[doc = r"Clears the field bit"]
80    #[inline(always)]
81    pub fn clear_bit(self) -> &'a mut W {
82        self.bit(false)
83    }
84    #[doc = r"Writes raw bits to the field"]
85    #[inline(always)]
86    pub fn bit(self, value: bool) -> &'a mut W {
87        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
88        self.w
89    }
90}
91#[doc = "Sample Point\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq)]
93pub enum SMPL_PT_A {
94    #[doc = "0: 0 protocol clock cycles between SCK edge and SIN sample"]
95    _00,
96    #[doc = "1: 1 protocol clock cycle between SCK edge and SIN sample"]
97    _01,
98    #[doc = "2: 2 protocol clock cycles between SCK edge and SIN sample"]
99    _10,
100}
101impl From<SMPL_PT_A> for u8 {
102    #[inline(always)]
103    fn from(variant: SMPL_PT_A) -> Self {
104        match variant {
105            SMPL_PT_A::_00 => 0,
106            SMPL_PT_A::_01 => 1,
107            SMPL_PT_A::_10 => 2,
108        }
109    }
110}
111#[doc = "Reader of field `SMPL_PT`"]
112pub type SMPL_PT_R = crate::R<u8, SMPL_PT_A>;
113impl SMPL_PT_R {
114    #[doc = r"Get enumerated values variant"]
115    #[inline(always)]
116    pub fn variant(&self) -> crate::Variant<u8, SMPL_PT_A> {
117        use crate::Variant::*;
118        match self.bits {
119            0 => Val(SMPL_PT_A::_00),
120            1 => Val(SMPL_PT_A::_01),
121            2 => Val(SMPL_PT_A::_10),
122            i => Res(i),
123        }
124    }
125    #[doc = "Checks if the value of the field is `_00`"]
126    #[inline(always)]
127    pub fn is_00(&self) -> bool {
128        *self == SMPL_PT_A::_00
129    }
130    #[doc = "Checks if the value of the field is `_01`"]
131    #[inline(always)]
132    pub fn is_01(&self) -> bool {
133        *self == SMPL_PT_A::_01
134    }
135    #[doc = "Checks if the value of the field is `_10`"]
136    #[inline(always)]
137    pub fn is_10(&self) -> bool {
138        *self == SMPL_PT_A::_10
139    }
140}
141#[doc = "Write proxy for field `SMPL_PT`"]
142pub struct SMPL_PT_W<'a> {
143    w: &'a mut W,
144}
145impl<'a> SMPL_PT_W<'a> {
146    #[doc = r"Writes `variant` to the field"]
147    #[inline(always)]
148    pub fn variant(self, variant: SMPL_PT_A) -> &'a mut W {
149        unsafe { self.bits(variant.into()) }
150    }
151    #[doc = "0 protocol clock cycles between SCK edge and SIN sample"]
152    #[inline(always)]
153    pub fn _00(self) -> &'a mut W {
154        self.variant(SMPL_PT_A::_00)
155    }
156    #[doc = "1 protocol clock cycle between SCK edge and SIN sample"]
157    #[inline(always)]
158    pub fn _01(self) -> &'a mut W {
159        self.variant(SMPL_PT_A::_01)
160    }
161    #[doc = "2 protocol clock cycles between SCK edge and SIN sample"]
162    #[inline(always)]
163    pub fn _10(self) -> &'a mut W {
164        self.variant(SMPL_PT_A::_10)
165    }
166    #[doc = r"Writes raw bits to the field"]
167    #[inline(always)]
168    pub unsafe fn bits(self, value: u8) -> &'a mut W {
169        self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
170        self.w
171    }
172}
173#[doc = "CLR_RXF\n\nValue on reset: 0"]
174#[derive(Clone, Copy, Debug, PartialEq)]
175pub enum CLR_RXF_AW {
176    #[doc = "0: Do not clear the RX FIFO counter."]
177    _0,
178    #[doc = "1: Clear the RX FIFO counter."]
179    _1,
180}
181impl From<CLR_RXF_AW> for bool {
182    #[inline(always)]
183    fn from(variant: CLR_RXF_AW) -> Self {
184        match variant {
185            CLR_RXF_AW::_0 => false,
186            CLR_RXF_AW::_1 => true,
187        }
188    }
189}
190#[doc = "Write proxy for field `CLR_RXF`"]
191pub struct CLR_RXF_W<'a> {
192    w: &'a mut W,
193}
194impl<'a> CLR_RXF_W<'a> {
195    #[doc = r"Writes `variant` to the field"]
196    #[inline(always)]
197    pub fn variant(self, variant: CLR_RXF_AW) -> &'a mut W {
198        {
199            self.bit(variant.into())
200        }
201    }
202    #[doc = "Do not clear the RX FIFO counter."]
203    #[inline(always)]
204    pub fn _0(self) -> &'a mut W {
205        self.variant(CLR_RXF_AW::_0)
206    }
207    #[doc = "Clear the RX FIFO counter."]
208    #[inline(always)]
209    pub fn _1(self) -> &'a mut W {
210        self.variant(CLR_RXF_AW::_1)
211    }
212    #[doc = r"Sets the field bit"]
213    #[inline(always)]
214    pub fn set_bit(self) -> &'a mut W {
215        self.bit(true)
216    }
217    #[doc = r"Clears the field bit"]
218    #[inline(always)]
219    pub fn clear_bit(self) -> &'a mut W {
220        self.bit(false)
221    }
222    #[doc = r"Writes raw bits to the field"]
223    #[inline(always)]
224    pub fn bit(self, value: bool) -> &'a mut W {
225        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
226        self.w
227    }
228}
229#[doc = "Clear TX FIFO\n\nValue on reset: 0"]
230#[derive(Clone, Copy, Debug, PartialEq)]
231pub enum CLR_TXF_AW {
232    #[doc = "0: Do not clear the TX FIFO counter."]
233    _0,
234    #[doc = "1: Clear the TX FIFO counter."]
235    _1,
236}
237impl From<CLR_TXF_AW> for bool {
238    #[inline(always)]
239    fn from(variant: CLR_TXF_AW) -> Self {
240        match variant {
241            CLR_TXF_AW::_0 => false,
242            CLR_TXF_AW::_1 => true,
243        }
244    }
245}
246#[doc = "Write proxy for field `CLR_TXF`"]
247pub struct CLR_TXF_W<'a> {
248    w: &'a mut W,
249}
250impl<'a> CLR_TXF_W<'a> {
251    #[doc = r"Writes `variant` to the field"]
252    #[inline(always)]
253    pub fn variant(self, variant: CLR_TXF_AW) -> &'a mut W {
254        {
255            self.bit(variant.into())
256        }
257    }
258    #[doc = "Do not clear the TX FIFO counter."]
259    #[inline(always)]
260    pub fn _0(self) -> &'a mut W {
261        self.variant(CLR_TXF_AW::_0)
262    }
263    #[doc = "Clear the TX FIFO counter."]
264    #[inline(always)]
265    pub fn _1(self) -> &'a mut W {
266        self.variant(CLR_TXF_AW::_1)
267    }
268    #[doc = r"Sets the field bit"]
269    #[inline(always)]
270    pub fn set_bit(self) -> &'a mut W {
271        self.bit(true)
272    }
273    #[doc = r"Clears the field bit"]
274    #[inline(always)]
275    pub fn clear_bit(self) -> &'a mut W {
276        self.bit(false)
277    }
278    #[doc = r"Writes raw bits to the field"]
279    #[inline(always)]
280    pub fn bit(self, value: bool) -> &'a mut W {
281        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
282        self.w
283    }
284}
285#[doc = "Disable Receive FIFO\n\nValue on reset: 0"]
286#[derive(Clone, Copy, Debug, PartialEq)]
287pub enum DIS_RXF_A {
288    #[doc = "0: RX FIFO is enabled."]
289    _0,
290    #[doc = "1: RX FIFO is disabled."]
291    _1,
292}
293impl From<DIS_RXF_A> for bool {
294    #[inline(always)]
295    fn from(variant: DIS_RXF_A) -> Self {
296        match variant {
297            DIS_RXF_A::_0 => false,
298            DIS_RXF_A::_1 => true,
299        }
300    }
301}
302#[doc = "Reader of field `DIS_RXF`"]
303pub type DIS_RXF_R = crate::R<bool, DIS_RXF_A>;
304impl DIS_RXF_R {
305    #[doc = r"Get enumerated values variant"]
306    #[inline(always)]
307    pub fn variant(&self) -> DIS_RXF_A {
308        match self.bits {
309            false => DIS_RXF_A::_0,
310            true => DIS_RXF_A::_1,
311        }
312    }
313    #[doc = "Checks if the value of the field is `_0`"]
314    #[inline(always)]
315    pub fn is_0(&self) -> bool {
316        *self == DIS_RXF_A::_0
317    }
318    #[doc = "Checks if the value of the field is `_1`"]
319    #[inline(always)]
320    pub fn is_1(&self) -> bool {
321        *self == DIS_RXF_A::_1
322    }
323}
324#[doc = "Write proxy for field `DIS_RXF`"]
325pub struct DIS_RXF_W<'a> {
326    w: &'a mut W,
327}
328impl<'a> DIS_RXF_W<'a> {
329    #[doc = r"Writes `variant` to the field"]
330    #[inline(always)]
331    pub fn variant(self, variant: DIS_RXF_A) -> &'a mut W {
332        {
333            self.bit(variant.into())
334        }
335    }
336    #[doc = "RX FIFO is enabled."]
337    #[inline(always)]
338    pub fn _0(self) -> &'a mut W {
339        self.variant(DIS_RXF_A::_0)
340    }
341    #[doc = "RX FIFO is disabled."]
342    #[inline(always)]
343    pub fn _1(self) -> &'a mut W {
344        self.variant(DIS_RXF_A::_1)
345    }
346    #[doc = r"Sets the field bit"]
347    #[inline(always)]
348    pub fn set_bit(self) -> &'a mut W {
349        self.bit(true)
350    }
351    #[doc = r"Clears the field bit"]
352    #[inline(always)]
353    pub fn clear_bit(self) -> &'a mut W {
354        self.bit(false)
355    }
356    #[doc = r"Writes raw bits to the field"]
357    #[inline(always)]
358    pub fn bit(self, value: bool) -> &'a mut W {
359        self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
360        self.w
361    }
362}
363#[doc = "Disable Transmit FIFO\n\nValue on reset: 0"]
364#[derive(Clone, Copy, Debug, PartialEq)]
365pub enum DIS_TXF_A {
366    #[doc = "0: TX FIFO is enabled."]
367    _0,
368    #[doc = "1: TX FIFO is disabled."]
369    _1,
370}
371impl From<DIS_TXF_A> for bool {
372    #[inline(always)]
373    fn from(variant: DIS_TXF_A) -> Self {
374        match variant {
375            DIS_TXF_A::_0 => false,
376            DIS_TXF_A::_1 => true,
377        }
378    }
379}
380#[doc = "Reader of field `DIS_TXF`"]
381pub type DIS_TXF_R = crate::R<bool, DIS_TXF_A>;
382impl DIS_TXF_R {
383    #[doc = r"Get enumerated values variant"]
384    #[inline(always)]
385    pub fn variant(&self) -> DIS_TXF_A {
386        match self.bits {
387            false => DIS_TXF_A::_0,
388            true => DIS_TXF_A::_1,
389        }
390    }
391    #[doc = "Checks if the value of the field is `_0`"]
392    #[inline(always)]
393    pub fn is_0(&self) -> bool {
394        *self == DIS_TXF_A::_0
395    }
396    #[doc = "Checks if the value of the field is `_1`"]
397    #[inline(always)]
398    pub fn is_1(&self) -> bool {
399        *self == DIS_TXF_A::_1
400    }
401}
402#[doc = "Write proxy for field `DIS_TXF`"]
403pub struct DIS_TXF_W<'a> {
404    w: &'a mut W,
405}
406impl<'a> DIS_TXF_W<'a> {
407    #[doc = r"Writes `variant` to the field"]
408    #[inline(always)]
409    pub fn variant(self, variant: DIS_TXF_A) -> &'a mut W {
410        {
411            self.bit(variant.into())
412        }
413    }
414    #[doc = "TX FIFO is enabled."]
415    #[inline(always)]
416    pub fn _0(self) -> &'a mut W {
417        self.variant(DIS_TXF_A::_0)
418    }
419    #[doc = "TX FIFO is disabled."]
420    #[inline(always)]
421    pub fn _1(self) -> &'a mut W {
422        self.variant(DIS_TXF_A::_1)
423    }
424    #[doc = r"Sets the field bit"]
425    #[inline(always)]
426    pub fn set_bit(self) -> &'a mut W {
427        self.bit(true)
428    }
429    #[doc = r"Clears the field bit"]
430    #[inline(always)]
431    pub fn clear_bit(self) -> &'a mut W {
432        self.bit(false)
433    }
434    #[doc = r"Writes raw bits to the field"]
435    #[inline(always)]
436    pub fn bit(self, value: bool) -> &'a mut W {
437        self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
438        self.w
439    }
440}
441#[doc = "Module Disable\n\nValue on reset: 1"]
442#[derive(Clone, Copy, Debug, PartialEq)]
443pub enum MDIS_A {
444    #[doc = "0: Enables the module clocks."]
445    _0,
446    #[doc = "1: Allows external logic to disable the module clocks."]
447    _1,
448}
449impl From<MDIS_A> for bool {
450    #[inline(always)]
451    fn from(variant: MDIS_A) -> Self {
452        match variant {
453            MDIS_A::_0 => false,
454            MDIS_A::_1 => true,
455        }
456    }
457}
458#[doc = "Reader of field `MDIS`"]
459pub type MDIS_R = crate::R<bool, MDIS_A>;
460impl MDIS_R {
461    #[doc = r"Get enumerated values variant"]
462    #[inline(always)]
463    pub fn variant(&self) -> MDIS_A {
464        match self.bits {
465            false => MDIS_A::_0,
466            true => MDIS_A::_1,
467        }
468    }
469    #[doc = "Checks if the value of the field is `_0`"]
470    #[inline(always)]
471    pub fn is_0(&self) -> bool {
472        *self == MDIS_A::_0
473    }
474    #[doc = "Checks if the value of the field is `_1`"]
475    #[inline(always)]
476    pub fn is_1(&self) -> bool {
477        *self == MDIS_A::_1
478    }
479}
480#[doc = "Write proxy for field `MDIS`"]
481pub struct MDIS_W<'a> {
482    w: &'a mut W,
483}
484impl<'a> MDIS_W<'a> {
485    #[doc = r"Writes `variant` to the field"]
486    #[inline(always)]
487    pub fn variant(self, variant: MDIS_A) -> &'a mut W {
488        {
489            self.bit(variant.into())
490        }
491    }
492    #[doc = "Enables the module clocks."]
493    #[inline(always)]
494    pub fn _0(self) -> &'a mut W {
495        self.variant(MDIS_A::_0)
496    }
497    #[doc = "Allows external logic to disable the module clocks."]
498    #[inline(always)]
499    pub fn _1(self) -> &'a mut W {
500        self.variant(MDIS_A::_1)
501    }
502    #[doc = r"Sets the field bit"]
503    #[inline(always)]
504    pub fn set_bit(self) -> &'a mut W {
505        self.bit(true)
506    }
507    #[doc = r"Clears the field bit"]
508    #[inline(always)]
509    pub fn clear_bit(self) -> &'a mut W {
510        self.bit(false)
511    }
512    #[doc = r"Writes raw bits to the field"]
513    #[inline(always)]
514    pub fn bit(self, value: bool) -> &'a mut W {
515        self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
516        self.w
517    }
518}
519#[doc = "Doze Enable\n\nValue on reset: 0"]
520#[derive(Clone, Copy, Debug, PartialEq)]
521pub enum DOZE_A {
522    #[doc = "0: Doze mode has no effect on the module."]
523    _0,
524    #[doc = "1: Doze mode disables the module."]
525    _1,
526}
527impl From<DOZE_A> for bool {
528    #[inline(always)]
529    fn from(variant: DOZE_A) -> Self {
530        match variant {
531            DOZE_A::_0 => false,
532            DOZE_A::_1 => true,
533        }
534    }
535}
536#[doc = "Reader of field `DOZE`"]
537pub type DOZE_R = crate::R<bool, DOZE_A>;
538impl DOZE_R {
539    #[doc = r"Get enumerated values variant"]
540    #[inline(always)]
541    pub fn variant(&self) -> DOZE_A {
542        match self.bits {
543            false => DOZE_A::_0,
544            true => DOZE_A::_1,
545        }
546    }
547    #[doc = "Checks if the value of the field is `_0`"]
548    #[inline(always)]
549    pub fn is_0(&self) -> bool {
550        *self == DOZE_A::_0
551    }
552    #[doc = "Checks if the value of the field is `_1`"]
553    #[inline(always)]
554    pub fn is_1(&self) -> bool {
555        *self == DOZE_A::_1
556    }
557}
558#[doc = "Write proxy for field `DOZE`"]
559pub struct DOZE_W<'a> {
560    w: &'a mut W,
561}
562impl<'a> DOZE_W<'a> {
563    #[doc = r"Writes `variant` to the field"]
564    #[inline(always)]
565    pub fn variant(self, variant: DOZE_A) -> &'a mut W {
566        {
567            self.bit(variant.into())
568        }
569    }
570    #[doc = "Doze mode has no effect on the module."]
571    #[inline(always)]
572    pub fn _0(self) -> &'a mut W {
573        self.variant(DOZE_A::_0)
574    }
575    #[doc = "Doze mode disables the module."]
576    #[inline(always)]
577    pub fn _1(self) -> &'a mut W {
578        self.variant(DOZE_A::_1)
579    }
580    #[doc = r"Sets the field bit"]
581    #[inline(always)]
582    pub fn set_bit(self) -> &'a mut W {
583        self.bit(true)
584    }
585    #[doc = r"Clears the field bit"]
586    #[inline(always)]
587    pub fn clear_bit(self) -> &'a mut W {
588        self.bit(false)
589    }
590    #[doc = r"Writes raw bits to the field"]
591    #[inline(always)]
592    pub fn bit(self, value: bool) -> &'a mut W {
593        self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
594        self.w
595    }
596}
597#[doc = "Peripheral Chip Select x Inactive State\n\nValue on reset: 0"]
598#[derive(Clone, Copy, Debug, PartialEq)]
599pub enum PCSIS0_A {
600    #[doc = "0: The inactive state of PCSx is low."]
601    _0,
602    #[doc = "1: The inactive state of PCSx is high."]
603    _1,
604}
605impl From<PCSIS0_A> for bool {
606    #[inline(always)]
607    fn from(variant: PCSIS0_A) -> Self {
608        match variant {
609            PCSIS0_A::_0 => false,
610            PCSIS0_A::_1 => true,
611        }
612    }
613}
614#[doc = "Reader of field `PCSIS0`"]
615pub type PCSIS0_R = crate::R<bool, PCSIS0_A>;
616impl PCSIS0_R {
617    #[doc = r"Get enumerated values variant"]
618    #[inline(always)]
619    pub fn variant(&self) -> PCSIS0_A {
620        match self.bits {
621            false => PCSIS0_A::_0,
622            true => PCSIS0_A::_1,
623        }
624    }
625    #[doc = "Checks if the value of the field is `_0`"]
626    #[inline(always)]
627    pub fn is_0(&self) -> bool {
628        *self == PCSIS0_A::_0
629    }
630    #[doc = "Checks if the value of the field is `_1`"]
631    #[inline(always)]
632    pub fn is_1(&self) -> bool {
633        *self == PCSIS0_A::_1
634    }
635}
636#[doc = "Write proxy for field `PCSIS0`"]
637pub struct PCSIS0_W<'a> {
638    w: &'a mut W,
639}
640impl<'a> PCSIS0_W<'a> {
641    #[doc = r"Writes `variant` to the field"]
642    #[inline(always)]
643    pub fn variant(self, variant: PCSIS0_A) -> &'a mut W {
644        {
645            self.bit(variant.into())
646        }
647    }
648    #[doc = "The inactive state of PCSx is low."]
649    #[inline(always)]
650    pub fn _0(self) -> &'a mut W {
651        self.variant(PCSIS0_A::_0)
652    }
653    #[doc = "The inactive state of PCSx is high."]
654    #[inline(always)]
655    pub fn _1(self) -> &'a mut W {
656        self.variant(PCSIS0_A::_1)
657    }
658    #[doc = r"Sets the field bit"]
659    #[inline(always)]
660    pub fn set_bit(self) -> &'a mut W {
661        self.bit(true)
662    }
663    #[doc = r"Clears the field bit"]
664    #[inline(always)]
665    pub fn clear_bit(self) -> &'a mut W {
666        self.bit(false)
667    }
668    #[doc = r"Writes raw bits to the field"]
669    #[inline(always)]
670    pub fn bit(self, value: bool) -> &'a mut W {
671        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
672        self.w
673    }
674}
675#[doc = "Peripheral Chip Select x Inactive State\n\nValue on reset: 0"]
676#[derive(Clone, Copy, Debug, PartialEq)]
677pub enum PCSIS1_A {
678    #[doc = "0: The inactive state of PCSx is low."]
679    _0,
680    #[doc = "1: The inactive state of PCSx is high."]
681    _1,
682}
683impl From<PCSIS1_A> for bool {
684    #[inline(always)]
685    fn from(variant: PCSIS1_A) -> Self {
686        match variant {
687            PCSIS1_A::_0 => false,
688            PCSIS1_A::_1 => true,
689        }
690    }
691}
692#[doc = "Reader of field `PCSIS1`"]
693pub type PCSIS1_R = crate::R<bool, PCSIS1_A>;
694impl PCSIS1_R {
695    #[doc = r"Get enumerated values variant"]
696    #[inline(always)]
697    pub fn variant(&self) -> PCSIS1_A {
698        match self.bits {
699            false => PCSIS1_A::_0,
700            true => PCSIS1_A::_1,
701        }
702    }
703    #[doc = "Checks if the value of the field is `_0`"]
704    #[inline(always)]
705    pub fn is_0(&self) -> bool {
706        *self == PCSIS1_A::_0
707    }
708    #[doc = "Checks if the value of the field is `_1`"]
709    #[inline(always)]
710    pub fn is_1(&self) -> bool {
711        *self == PCSIS1_A::_1
712    }
713}
714#[doc = "Write proxy for field `PCSIS1`"]
715pub struct PCSIS1_W<'a> {
716    w: &'a mut W,
717}
718impl<'a> PCSIS1_W<'a> {
719    #[doc = r"Writes `variant` to the field"]
720    #[inline(always)]
721    pub fn variant(self, variant: PCSIS1_A) -> &'a mut W {
722        {
723            self.bit(variant.into())
724        }
725    }
726    #[doc = "The inactive state of PCSx is low."]
727    #[inline(always)]
728    pub fn _0(self) -> &'a mut W {
729        self.variant(PCSIS1_A::_0)
730    }
731    #[doc = "The inactive state of PCSx is high."]
732    #[inline(always)]
733    pub fn _1(self) -> &'a mut W {
734        self.variant(PCSIS1_A::_1)
735    }
736    #[doc = r"Sets the field bit"]
737    #[inline(always)]
738    pub fn set_bit(self) -> &'a mut W {
739        self.bit(true)
740    }
741    #[doc = r"Clears the field bit"]
742    #[inline(always)]
743    pub fn clear_bit(self) -> &'a mut W {
744        self.bit(false)
745    }
746    #[doc = r"Writes raw bits to the field"]
747    #[inline(always)]
748    pub fn bit(self, value: bool) -> &'a mut W {
749        self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
750        self.w
751    }
752}
753#[doc = "Peripheral Chip Select x Inactive State\n\nValue on reset: 0"]
754#[derive(Clone, Copy, Debug, PartialEq)]
755pub enum PCSIS2_A {
756    #[doc = "0: The inactive state of PCSx is low."]
757    _0,
758    #[doc = "1: The inactive state of PCSx is high."]
759    _1,
760}
761impl From<PCSIS2_A> for bool {
762    #[inline(always)]
763    fn from(variant: PCSIS2_A) -> Self {
764        match variant {
765            PCSIS2_A::_0 => false,
766            PCSIS2_A::_1 => true,
767        }
768    }
769}
770#[doc = "Reader of field `PCSIS2`"]
771pub type PCSIS2_R = crate::R<bool, PCSIS2_A>;
772impl PCSIS2_R {
773    #[doc = r"Get enumerated values variant"]
774    #[inline(always)]
775    pub fn variant(&self) -> PCSIS2_A {
776        match self.bits {
777            false => PCSIS2_A::_0,
778            true => PCSIS2_A::_1,
779        }
780    }
781    #[doc = "Checks if the value of the field is `_0`"]
782    #[inline(always)]
783    pub fn is_0(&self) -> bool {
784        *self == PCSIS2_A::_0
785    }
786    #[doc = "Checks if the value of the field is `_1`"]
787    #[inline(always)]
788    pub fn is_1(&self) -> bool {
789        *self == PCSIS2_A::_1
790    }
791}
792#[doc = "Write proxy for field `PCSIS2`"]
793pub struct PCSIS2_W<'a> {
794    w: &'a mut W,
795}
796impl<'a> PCSIS2_W<'a> {
797    #[doc = r"Writes `variant` to the field"]
798    #[inline(always)]
799    pub fn variant(self, variant: PCSIS2_A) -> &'a mut W {
800        {
801            self.bit(variant.into())
802        }
803    }
804    #[doc = "The inactive state of PCSx is low."]
805    #[inline(always)]
806    pub fn _0(self) -> &'a mut W {
807        self.variant(PCSIS2_A::_0)
808    }
809    #[doc = "The inactive state of PCSx is high."]
810    #[inline(always)]
811    pub fn _1(self) -> &'a mut W {
812        self.variant(PCSIS2_A::_1)
813    }
814    #[doc = r"Sets the field bit"]
815    #[inline(always)]
816    pub fn set_bit(self) -> &'a mut W {
817        self.bit(true)
818    }
819    #[doc = r"Clears the field bit"]
820    #[inline(always)]
821    pub fn clear_bit(self) -> &'a mut W {
822        self.bit(false)
823    }
824    #[doc = r"Writes raw bits to the field"]
825    #[inline(always)]
826    pub fn bit(self, value: bool) -> &'a mut W {
827        self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
828        self.w
829    }
830}
831#[doc = "Peripheral Chip Select x Inactive State\n\nValue on reset: 0"]
832#[derive(Clone, Copy, Debug, PartialEq)]
833pub enum PCSIS3_A {
834    #[doc = "0: The inactive state of PCSx is low."]
835    _0,
836    #[doc = "1: The inactive state of PCSx is high."]
837    _1,
838}
839impl From<PCSIS3_A> for bool {
840    #[inline(always)]
841    fn from(variant: PCSIS3_A) -> Self {
842        match variant {
843            PCSIS3_A::_0 => false,
844            PCSIS3_A::_1 => true,
845        }
846    }
847}
848#[doc = "Reader of field `PCSIS3`"]
849pub type PCSIS3_R = crate::R<bool, PCSIS3_A>;
850impl PCSIS3_R {
851    #[doc = r"Get enumerated values variant"]
852    #[inline(always)]
853    pub fn variant(&self) -> PCSIS3_A {
854        match self.bits {
855            false => PCSIS3_A::_0,
856            true => PCSIS3_A::_1,
857        }
858    }
859    #[doc = "Checks if the value of the field is `_0`"]
860    #[inline(always)]
861    pub fn is_0(&self) -> bool {
862        *self == PCSIS3_A::_0
863    }
864    #[doc = "Checks if the value of the field is `_1`"]
865    #[inline(always)]
866    pub fn is_1(&self) -> bool {
867        *self == PCSIS3_A::_1
868    }
869}
870#[doc = "Write proxy for field `PCSIS3`"]
871pub struct PCSIS3_W<'a> {
872    w: &'a mut W,
873}
874impl<'a> PCSIS3_W<'a> {
875    #[doc = r"Writes `variant` to the field"]
876    #[inline(always)]
877    pub fn variant(self, variant: PCSIS3_A) -> &'a mut W {
878        {
879            self.bit(variant.into())
880        }
881    }
882    #[doc = "The inactive state of PCSx is low."]
883    #[inline(always)]
884    pub fn _0(self) -> &'a mut W {
885        self.variant(PCSIS3_A::_0)
886    }
887    #[doc = "The inactive state of PCSx is high."]
888    #[inline(always)]
889    pub fn _1(self) -> &'a mut W {
890        self.variant(PCSIS3_A::_1)
891    }
892    #[doc = r"Sets the field bit"]
893    #[inline(always)]
894    pub fn set_bit(self) -> &'a mut W {
895        self.bit(true)
896    }
897    #[doc = r"Clears the field bit"]
898    #[inline(always)]
899    pub fn clear_bit(self) -> &'a mut W {
900        self.bit(false)
901    }
902    #[doc = r"Writes raw bits to the field"]
903    #[inline(always)]
904    pub fn bit(self, value: bool) -> &'a mut W {
905        self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
906        self.w
907    }
908}
909#[doc = "Peripheral Chip Select x Inactive State\n\nValue on reset: 0"]
910#[derive(Clone, Copy, Debug, PartialEq)]
911pub enum PCSIS4_A {
912    #[doc = "0: The inactive state of PCSx is low."]
913    _0,
914    #[doc = "1: The inactive state of PCSx is high."]
915    _1,
916}
917impl From<PCSIS4_A> for bool {
918    #[inline(always)]
919    fn from(variant: PCSIS4_A) -> Self {
920        match variant {
921            PCSIS4_A::_0 => false,
922            PCSIS4_A::_1 => true,
923        }
924    }
925}
926#[doc = "Reader of field `PCSIS4`"]
927pub type PCSIS4_R = crate::R<bool, PCSIS4_A>;
928impl PCSIS4_R {
929    #[doc = r"Get enumerated values variant"]
930    #[inline(always)]
931    pub fn variant(&self) -> PCSIS4_A {
932        match self.bits {
933            false => PCSIS4_A::_0,
934            true => PCSIS4_A::_1,
935        }
936    }
937    #[doc = "Checks if the value of the field is `_0`"]
938    #[inline(always)]
939    pub fn is_0(&self) -> bool {
940        *self == PCSIS4_A::_0
941    }
942    #[doc = "Checks if the value of the field is `_1`"]
943    #[inline(always)]
944    pub fn is_1(&self) -> bool {
945        *self == PCSIS4_A::_1
946    }
947}
948#[doc = "Write proxy for field `PCSIS4`"]
949pub struct PCSIS4_W<'a> {
950    w: &'a mut W,
951}
952impl<'a> PCSIS4_W<'a> {
953    #[doc = r"Writes `variant` to the field"]
954    #[inline(always)]
955    pub fn variant(self, variant: PCSIS4_A) -> &'a mut W {
956        {
957            self.bit(variant.into())
958        }
959    }
960    #[doc = "The inactive state of PCSx is low."]
961    #[inline(always)]
962    pub fn _0(self) -> &'a mut W {
963        self.variant(PCSIS4_A::_0)
964    }
965    #[doc = "The inactive state of PCSx is high."]
966    #[inline(always)]
967    pub fn _1(self) -> &'a mut W {
968        self.variant(PCSIS4_A::_1)
969    }
970    #[doc = r"Sets the field bit"]
971    #[inline(always)]
972    pub fn set_bit(self) -> &'a mut W {
973        self.bit(true)
974    }
975    #[doc = r"Clears the field bit"]
976    #[inline(always)]
977    pub fn clear_bit(self) -> &'a mut W {
978        self.bit(false)
979    }
980    #[doc = r"Writes raw bits to the field"]
981    #[inline(always)]
982    pub fn bit(self, value: bool) -> &'a mut W {
983        self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
984        self.w
985    }
986}
987#[doc = "Peripheral Chip Select x Inactive State\n\nValue on reset: 0"]
988#[derive(Clone, Copy, Debug, PartialEq)]
989pub enum PCSIS5_A {
990    #[doc = "0: The inactive state of PCSx is low."]
991    _0,
992    #[doc = "1: The inactive state of PCSx is high."]
993    _1,
994}
995impl From<PCSIS5_A> for bool {
996    #[inline(always)]
997    fn from(variant: PCSIS5_A) -> Self {
998        match variant {
999            PCSIS5_A::_0 => false,
1000            PCSIS5_A::_1 => true,
1001        }
1002    }
1003}
1004#[doc = "Reader of field `PCSIS5`"]
1005pub type PCSIS5_R = crate::R<bool, PCSIS5_A>;
1006impl PCSIS5_R {
1007    #[doc = r"Get enumerated values variant"]
1008    #[inline(always)]
1009    pub fn variant(&self) -> PCSIS5_A {
1010        match self.bits {
1011            false => PCSIS5_A::_0,
1012            true => PCSIS5_A::_1,
1013        }
1014    }
1015    #[doc = "Checks if the value of the field is `_0`"]
1016    #[inline(always)]
1017    pub fn is_0(&self) -> bool {
1018        *self == PCSIS5_A::_0
1019    }
1020    #[doc = "Checks if the value of the field is `_1`"]
1021    #[inline(always)]
1022    pub fn is_1(&self) -> bool {
1023        *self == PCSIS5_A::_1
1024    }
1025}
1026#[doc = "Write proxy for field `PCSIS5`"]
1027pub struct PCSIS5_W<'a> {
1028    w: &'a mut W,
1029}
1030impl<'a> PCSIS5_W<'a> {
1031    #[doc = r"Writes `variant` to the field"]
1032    #[inline(always)]
1033    pub fn variant(self, variant: PCSIS5_A) -> &'a mut W {
1034        {
1035            self.bit(variant.into())
1036        }
1037    }
1038    #[doc = "The inactive state of PCSx is low."]
1039    #[inline(always)]
1040    pub fn _0(self) -> &'a mut W {
1041        self.variant(PCSIS5_A::_0)
1042    }
1043    #[doc = "The inactive state of PCSx is high."]
1044    #[inline(always)]
1045    pub fn _1(self) -> &'a mut W {
1046        self.variant(PCSIS5_A::_1)
1047    }
1048    #[doc = r"Sets the field bit"]
1049    #[inline(always)]
1050    pub fn set_bit(self) -> &'a mut W {
1051        self.bit(true)
1052    }
1053    #[doc = r"Clears the field bit"]
1054    #[inline(always)]
1055    pub fn clear_bit(self) -> &'a mut W {
1056        self.bit(false)
1057    }
1058    #[doc = r"Writes raw bits to the field"]
1059    #[inline(always)]
1060    pub fn bit(self, value: bool) -> &'a mut W {
1061        self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
1062        self.w
1063    }
1064}
1065#[doc = "Receive FIFO Overflow Overwrite Enable\n\nValue on reset: 0"]
1066#[derive(Clone, Copy, Debug, PartialEq)]
1067pub enum ROOE_A {
1068    #[doc = "0: Incoming data is ignored."]
1069    _0,
1070    #[doc = "1: Incoming data is shifted into the shift register."]
1071    _1,
1072}
1073impl From<ROOE_A> for bool {
1074    #[inline(always)]
1075    fn from(variant: ROOE_A) -> Self {
1076        match variant {
1077            ROOE_A::_0 => false,
1078            ROOE_A::_1 => true,
1079        }
1080    }
1081}
1082#[doc = "Reader of field `ROOE`"]
1083pub type ROOE_R = crate::R<bool, ROOE_A>;
1084impl ROOE_R {
1085    #[doc = r"Get enumerated values variant"]
1086    #[inline(always)]
1087    pub fn variant(&self) -> ROOE_A {
1088        match self.bits {
1089            false => ROOE_A::_0,
1090            true => ROOE_A::_1,
1091        }
1092    }
1093    #[doc = "Checks if the value of the field is `_0`"]
1094    #[inline(always)]
1095    pub fn is_0(&self) -> bool {
1096        *self == ROOE_A::_0
1097    }
1098    #[doc = "Checks if the value of the field is `_1`"]
1099    #[inline(always)]
1100    pub fn is_1(&self) -> bool {
1101        *self == ROOE_A::_1
1102    }
1103}
1104#[doc = "Write proxy for field `ROOE`"]
1105pub struct ROOE_W<'a> {
1106    w: &'a mut W,
1107}
1108impl<'a> ROOE_W<'a> {
1109    #[doc = r"Writes `variant` to the field"]
1110    #[inline(always)]
1111    pub fn variant(self, variant: ROOE_A) -> &'a mut W {
1112        {
1113            self.bit(variant.into())
1114        }
1115    }
1116    #[doc = "Incoming data is ignored."]
1117    #[inline(always)]
1118    pub fn _0(self) -> &'a mut W {
1119        self.variant(ROOE_A::_0)
1120    }
1121    #[doc = "Incoming data is shifted into the shift register."]
1122    #[inline(always)]
1123    pub fn _1(self) -> &'a mut W {
1124        self.variant(ROOE_A::_1)
1125    }
1126    #[doc = r"Sets the field bit"]
1127    #[inline(always)]
1128    pub fn set_bit(self) -> &'a mut W {
1129        self.bit(true)
1130    }
1131    #[doc = r"Clears the field bit"]
1132    #[inline(always)]
1133    pub fn clear_bit(self) -> &'a mut W {
1134        self.bit(false)
1135    }
1136    #[doc = r"Writes raw bits to the field"]
1137    #[inline(always)]
1138    pub fn bit(self, value: bool) -> &'a mut W {
1139        self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
1140        self.w
1141    }
1142}
1143#[doc = "Peripheral Chip Select Strobe Enable\n\nValue on reset: 0"]
1144#[derive(Clone, Copy, Debug, PartialEq)]
1145pub enum PCSSE_A {
1146    #[doc = "0: PCS5/ PCSS is used as the Peripheral Chip Select\\[5\\] signal."]
1147    _0,
1148    #[doc = "1: PCS5/ PCSS is used as an active-low PCS Strobe signal."]
1149    _1,
1150}
1151impl From<PCSSE_A> for bool {
1152    #[inline(always)]
1153    fn from(variant: PCSSE_A) -> Self {
1154        match variant {
1155            PCSSE_A::_0 => false,
1156            PCSSE_A::_1 => true,
1157        }
1158    }
1159}
1160#[doc = "Reader of field `PCSSE`"]
1161pub type PCSSE_R = crate::R<bool, PCSSE_A>;
1162impl PCSSE_R {
1163    #[doc = r"Get enumerated values variant"]
1164    #[inline(always)]
1165    pub fn variant(&self) -> PCSSE_A {
1166        match self.bits {
1167            false => PCSSE_A::_0,
1168            true => PCSSE_A::_1,
1169        }
1170    }
1171    #[doc = "Checks if the value of the field is `_0`"]
1172    #[inline(always)]
1173    pub fn is_0(&self) -> bool {
1174        *self == PCSSE_A::_0
1175    }
1176    #[doc = "Checks if the value of the field is `_1`"]
1177    #[inline(always)]
1178    pub fn is_1(&self) -> bool {
1179        *self == PCSSE_A::_1
1180    }
1181}
1182#[doc = "Write proxy for field `PCSSE`"]
1183pub struct PCSSE_W<'a> {
1184    w: &'a mut W,
1185}
1186impl<'a> PCSSE_W<'a> {
1187    #[doc = r"Writes `variant` to the field"]
1188    #[inline(always)]
1189    pub fn variant(self, variant: PCSSE_A) -> &'a mut W {
1190        {
1191            self.bit(variant.into())
1192        }
1193    }
1194    #[doc = "PCS5/ PCSS is used as the Peripheral Chip Select\\[5\\] signal."]
1195    #[inline(always)]
1196    pub fn _0(self) -> &'a mut W {
1197        self.variant(PCSSE_A::_0)
1198    }
1199    #[doc = "PCS5/ PCSS is used as an active-low PCS Strobe signal."]
1200    #[inline(always)]
1201    pub fn _1(self) -> &'a mut W {
1202        self.variant(PCSSE_A::_1)
1203    }
1204    #[doc = r"Sets the field bit"]
1205    #[inline(always)]
1206    pub fn set_bit(self) -> &'a mut W {
1207        self.bit(true)
1208    }
1209    #[doc = r"Clears the field bit"]
1210    #[inline(always)]
1211    pub fn clear_bit(self) -> &'a mut W {
1212        self.bit(false)
1213    }
1214    #[doc = r"Writes raw bits to the field"]
1215    #[inline(always)]
1216    pub fn bit(self, value: bool) -> &'a mut W {
1217        self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
1218        self.w
1219    }
1220}
1221#[doc = "Modified Transfer Format Enable\n\nValue on reset: 0"]
1222#[derive(Clone, Copy, Debug, PartialEq)]
1223pub enum MTFE_A {
1224    #[doc = "0: Modified SPI transfer format disabled."]
1225    _0,
1226    #[doc = "1: Modified SPI transfer format enabled."]
1227    _1,
1228}
1229impl From<MTFE_A> for bool {
1230    #[inline(always)]
1231    fn from(variant: MTFE_A) -> Self {
1232        match variant {
1233            MTFE_A::_0 => false,
1234            MTFE_A::_1 => true,
1235        }
1236    }
1237}
1238#[doc = "Reader of field `MTFE`"]
1239pub type MTFE_R = crate::R<bool, MTFE_A>;
1240impl MTFE_R {
1241    #[doc = r"Get enumerated values variant"]
1242    #[inline(always)]
1243    pub fn variant(&self) -> MTFE_A {
1244        match self.bits {
1245            false => MTFE_A::_0,
1246            true => MTFE_A::_1,
1247        }
1248    }
1249    #[doc = "Checks if the value of the field is `_0`"]
1250    #[inline(always)]
1251    pub fn is_0(&self) -> bool {
1252        *self == MTFE_A::_0
1253    }
1254    #[doc = "Checks if the value of the field is `_1`"]
1255    #[inline(always)]
1256    pub fn is_1(&self) -> bool {
1257        *self == MTFE_A::_1
1258    }
1259}
1260#[doc = "Write proxy for field `MTFE`"]
1261pub struct MTFE_W<'a> {
1262    w: &'a mut W,
1263}
1264impl<'a> MTFE_W<'a> {
1265    #[doc = r"Writes `variant` to the field"]
1266    #[inline(always)]
1267    pub fn variant(self, variant: MTFE_A) -> &'a mut W {
1268        {
1269            self.bit(variant.into())
1270        }
1271    }
1272    #[doc = "Modified SPI transfer format disabled."]
1273    #[inline(always)]
1274    pub fn _0(self) -> &'a mut W {
1275        self.variant(MTFE_A::_0)
1276    }
1277    #[doc = "Modified SPI transfer format enabled."]
1278    #[inline(always)]
1279    pub fn _1(self) -> &'a mut W {
1280        self.variant(MTFE_A::_1)
1281    }
1282    #[doc = r"Sets the field bit"]
1283    #[inline(always)]
1284    pub fn set_bit(self) -> &'a mut W {
1285        self.bit(true)
1286    }
1287    #[doc = r"Clears the field bit"]
1288    #[inline(always)]
1289    pub fn clear_bit(self) -> &'a mut W {
1290        self.bit(false)
1291    }
1292    #[doc = r"Writes raw bits to the field"]
1293    #[inline(always)]
1294    pub fn bit(self, value: bool) -> &'a mut W {
1295        self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
1296        self.w
1297    }
1298}
1299#[doc = "Freeze\n\nValue on reset: 0"]
1300#[derive(Clone, Copy, Debug, PartialEq)]
1301pub enum FRZ_A {
1302    #[doc = "0: Do not halt serial transfers in Debug mode."]
1303    _0,
1304    #[doc = "1: Halt serial transfers in Debug mode."]
1305    _1,
1306}
1307impl From<FRZ_A> for bool {
1308    #[inline(always)]
1309    fn from(variant: FRZ_A) -> Self {
1310        match variant {
1311            FRZ_A::_0 => false,
1312            FRZ_A::_1 => true,
1313        }
1314    }
1315}
1316#[doc = "Reader of field `FRZ`"]
1317pub type FRZ_R = crate::R<bool, FRZ_A>;
1318impl FRZ_R {
1319    #[doc = r"Get enumerated values variant"]
1320    #[inline(always)]
1321    pub fn variant(&self) -> FRZ_A {
1322        match self.bits {
1323            false => FRZ_A::_0,
1324            true => FRZ_A::_1,
1325        }
1326    }
1327    #[doc = "Checks if the value of the field is `_0`"]
1328    #[inline(always)]
1329    pub fn is_0(&self) -> bool {
1330        *self == FRZ_A::_0
1331    }
1332    #[doc = "Checks if the value of the field is `_1`"]
1333    #[inline(always)]
1334    pub fn is_1(&self) -> bool {
1335        *self == FRZ_A::_1
1336    }
1337}
1338#[doc = "Write proxy for field `FRZ`"]
1339pub struct FRZ_W<'a> {
1340    w: &'a mut W,
1341}
1342impl<'a> FRZ_W<'a> {
1343    #[doc = r"Writes `variant` to the field"]
1344    #[inline(always)]
1345    pub fn variant(self, variant: FRZ_A) -> &'a mut W {
1346        {
1347            self.bit(variant.into())
1348        }
1349    }
1350    #[doc = "Do not halt serial transfers in Debug mode."]
1351    #[inline(always)]
1352    pub fn _0(self) -> &'a mut W {
1353        self.variant(FRZ_A::_0)
1354    }
1355    #[doc = "Halt serial transfers in Debug mode."]
1356    #[inline(always)]
1357    pub fn _1(self) -> &'a mut W {
1358        self.variant(FRZ_A::_1)
1359    }
1360    #[doc = r"Sets the field bit"]
1361    #[inline(always)]
1362    pub fn set_bit(self) -> &'a mut W {
1363        self.bit(true)
1364    }
1365    #[doc = r"Clears the field bit"]
1366    #[inline(always)]
1367    pub fn clear_bit(self) -> &'a mut W {
1368        self.bit(false)
1369    }
1370    #[doc = r"Writes raw bits to the field"]
1371    #[inline(always)]
1372    pub fn bit(self, value: bool) -> &'a mut W {
1373        self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
1374        self.w
1375    }
1376}
1377#[doc = "SPI Configuration.\n\nValue on reset: 0"]
1378#[derive(Clone, Copy, Debug, PartialEq)]
1379pub enum DCONF_A {
1380    #[doc = "0: SPI"]
1381    _00,
1382}
1383impl From<DCONF_A> for u8 {
1384    #[inline(always)]
1385    fn from(variant: DCONF_A) -> Self {
1386        match variant {
1387            DCONF_A::_00 => 0,
1388        }
1389    }
1390}
1391#[doc = "Reader of field `DCONF`"]
1392pub type DCONF_R = crate::R<u8, DCONF_A>;
1393impl DCONF_R {
1394    #[doc = r"Get enumerated values variant"]
1395    #[inline(always)]
1396    pub fn variant(&self) -> crate::Variant<u8, DCONF_A> {
1397        use crate::Variant::*;
1398        match self.bits {
1399            0 => Val(DCONF_A::_00),
1400            i => Res(i),
1401        }
1402    }
1403    #[doc = "Checks if the value of the field is `_00`"]
1404    #[inline(always)]
1405    pub fn is_00(&self) -> bool {
1406        *self == DCONF_A::_00
1407    }
1408}
1409#[doc = "Continuous SCK Enable\n\nValue on reset: 0"]
1410#[derive(Clone, Copy, Debug, PartialEq)]
1411pub enum CONT_SCKE_A {
1412    #[doc = "0: Continuous SCK disabled."]
1413    _0,
1414    #[doc = "1: Continuous SCK enabled."]
1415    _1,
1416}
1417impl From<CONT_SCKE_A> for bool {
1418    #[inline(always)]
1419    fn from(variant: CONT_SCKE_A) -> Self {
1420        match variant {
1421            CONT_SCKE_A::_0 => false,
1422            CONT_SCKE_A::_1 => true,
1423        }
1424    }
1425}
1426#[doc = "Reader of field `CONT_SCKE`"]
1427pub type CONT_SCKE_R = crate::R<bool, CONT_SCKE_A>;
1428impl CONT_SCKE_R {
1429    #[doc = r"Get enumerated values variant"]
1430    #[inline(always)]
1431    pub fn variant(&self) -> CONT_SCKE_A {
1432        match self.bits {
1433            false => CONT_SCKE_A::_0,
1434            true => CONT_SCKE_A::_1,
1435        }
1436    }
1437    #[doc = "Checks if the value of the field is `_0`"]
1438    #[inline(always)]
1439    pub fn is_0(&self) -> bool {
1440        *self == CONT_SCKE_A::_0
1441    }
1442    #[doc = "Checks if the value of the field is `_1`"]
1443    #[inline(always)]
1444    pub fn is_1(&self) -> bool {
1445        *self == CONT_SCKE_A::_1
1446    }
1447}
1448#[doc = "Write proxy for field `CONT_SCKE`"]
1449pub struct CONT_SCKE_W<'a> {
1450    w: &'a mut W,
1451}
1452impl<'a> CONT_SCKE_W<'a> {
1453    #[doc = r"Writes `variant` to the field"]
1454    #[inline(always)]
1455    pub fn variant(self, variant: CONT_SCKE_A) -> &'a mut W {
1456        {
1457            self.bit(variant.into())
1458        }
1459    }
1460    #[doc = "Continuous SCK disabled."]
1461    #[inline(always)]
1462    pub fn _0(self) -> &'a mut W {
1463        self.variant(CONT_SCKE_A::_0)
1464    }
1465    #[doc = "Continuous SCK enabled."]
1466    #[inline(always)]
1467    pub fn _1(self) -> &'a mut W {
1468        self.variant(CONT_SCKE_A::_1)
1469    }
1470    #[doc = r"Sets the field bit"]
1471    #[inline(always)]
1472    pub fn set_bit(self) -> &'a mut W {
1473        self.bit(true)
1474    }
1475    #[doc = r"Clears the field bit"]
1476    #[inline(always)]
1477    pub fn clear_bit(self) -> &'a mut W {
1478        self.bit(false)
1479    }
1480    #[doc = r"Writes raw bits to the field"]
1481    #[inline(always)]
1482    pub fn bit(self, value: bool) -> &'a mut W {
1483        self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
1484        self.w
1485    }
1486}
1487#[doc = "Master/Slave Mode Select\n\nValue on reset: 0"]
1488#[derive(Clone, Copy, Debug, PartialEq)]
1489pub enum MSTR_A {
1490    #[doc = "0: Enables Slave mode"]
1491    _0,
1492    #[doc = "1: Enables Master mode"]
1493    _1,
1494}
1495impl From<MSTR_A> for bool {
1496    #[inline(always)]
1497    fn from(variant: MSTR_A) -> Self {
1498        match variant {
1499            MSTR_A::_0 => false,
1500            MSTR_A::_1 => true,
1501        }
1502    }
1503}
1504#[doc = "Reader of field `MSTR`"]
1505pub type MSTR_R = crate::R<bool, MSTR_A>;
1506impl MSTR_R {
1507    #[doc = r"Get enumerated values variant"]
1508    #[inline(always)]
1509    pub fn variant(&self) -> MSTR_A {
1510        match self.bits {
1511            false => MSTR_A::_0,
1512            true => MSTR_A::_1,
1513        }
1514    }
1515    #[doc = "Checks if the value of the field is `_0`"]
1516    #[inline(always)]
1517    pub fn is_0(&self) -> bool {
1518        *self == MSTR_A::_0
1519    }
1520    #[doc = "Checks if the value of the field is `_1`"]
1521    #[inline(always)]
1522    pub fn is_1(&self) -> bool {
1523        *self == MSTR_A::_1
1524    }
1525}
1526#[doc = "Write proxy for field `MSTR`"]
1527pub struct MSTR_W<'a> {
1528    w: &'a mut W,
1529}
1530impl<'a> MSTR_W<'a> {
1531    #[doc = r"Writes `variant` to the field"]
1532    #[inline(always)]
1533    pub fn variant(self, variant: MSTR_A) -> &'a mut W {
1534        {
1535            self.bit(variant.into())
1536        }
1537    }
1538    #[doc = "Enables Slave mode"]
1539    #[inline(always)]
1540    pub fn _0(self) -> &'a mut W {
1541        self.variant(MSTR_A::_0)
1542    }
1543    #[doc = "Enables Master mode"]
1544    #[inline(always)]
1545    pub fn _1(self) -> &'a mut W {
1546        self.variant(MSTR_A::_1)
1547    }
1548    #[doc = r"Sets the field bit"]
1549    #[inline(always)]
1550    pub fn set_bit(self) -> &'a mut W {
1551        self.bit(true)
1552    }
1553    #[doc = r"Clears the field bit"]
1554    #[inline(always)]
1555    pub fn clear_bit(self) -> &'a mut W {
1556        self.bit(false)
1557    }
1558    #[doc = r"Writes raw bits to the field"]
1559    #[inline(always)]
1560    pub fn bit(self, value: bool) -> &'a mut W {
1561        self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
1562        self.w
1563    }
1564}
1565impl R {
1566    #[doc = "Bit 0 - Halt"]
1567    #[inline(always)]
1568    pub fn halt(&self) -> HALT_R {
1569        HALT_R::new((self.bits & 0x01) != 0)
1570    }
1571    #[doc = "Bits 8:9 - Sample Point"]
1572    #[inline(always)]
1573    pub fn smpl_pt(&self) -> SMPL_PT_R {
1574        SMPL_PT_R::new(((self.bits >> 8) & 0x03) as u8)
1575    }
1576    #[doc = "Bit 12 - Disable Receive FIFO"]
1577    #[inline(always)]
1578    pub fn dis_rxf(&self) -> DIS_RXF_R {
1579        DIS_RXF_R::new(((self.bits >> 12) & 0x01) != 0)
1580    }
1581    #[doc = "Bit 13 - Disable Transmit FIFO"]
1582    #[inline(always)]
1583    pub fn dis_txf(&self) -> DIS_TXF_R {
1584        DIS_TXF_R::new(((self.bits >> 13) & 0x01) != 0)
1585    }
1586    #[doc = "Bit 14 - Module Disable"]
1587    #[inline(always)]
1588    pub fn mdis(&self) -> MDIS_R {
1589        MDIS_R::new(((self.bits >> 14) & 0x01) != 0)
1590    }
1591    #[doc = "Bit 15 - Doze Enable"]
1592    #[inline(always)]
1593    pub fn doze(&self) -> DOZE_R {
1594        DOZE_R::new(((self.bits >> 15) & 0x01) != 0)
1595    }
1596    #[doc = "Bit 16 - Peripheral Chip Select x Inactive State"]
1597    #[inline(always)]
1598    pub fn pcsis0(&self) -> PCSIS0_R {
1599        PCSIS0_R::new(((self.bits >> 16) & 0x01) != 0)
1600    }
1601    #[doc = "Bit 17 - Peripheral Chip Select x Inactive State"]
1602    #[inline(always)]
1603    pub fn pcsis1(&self) -> PCSIS1_R {
1604        PCSIS1_R::new(((self.bits >> 17) & 0x01) != 0)
1605    }
1606    #[doc = "Bit 18 - Peripheral Chip Select x Inactive State"]
1607    #[inline(always)]
1608    pub fn pcsis2(&self) -> PCSIS2_R {
1609        PCSIS2_R::new(((self.bits >> 18) & 0x01) != 0)
1610    }
1611    #[doc = "Bit 19 - Peripheral Chip Select x Inactive State"]
1612    #[inline(always)]
1613    pub fn pcsis3(&self) -> PCSIS3_R {
1614        PCSIS3_R::new(((self.bits >> 19) & 0x01) != 0)
1615    }
1616    #[doc = "Bit 20 - Peripheral Chip Select x Inactive State"]
1617    #[inline(always)]
1618    pub fn pcsis4(&self) -> PCSIS4_R {
1619        PCSIS4_R::new(((self.bits >> 20) & 0x01) != 0)
1620    }
1621    #[doc = "Bit 21 - Peripheral Chip Select x Inactive State"]
1622    #[inline(always)]
1623    pub fn pcsis5(&self) -> PCSIS5_R {
1624        PCSIS5_R::new(((self.bits >> 21) & 0x01) != 0)
1625    }
1626    #[doc = "Bit 24 - Receive FIFO Overflow Overwrite Enable"]
1627    #[inline(always)]
1628    pub fn rooe(&self) -> ROOE_R {
1629        ROOE_R::new(((self.bits >> 24) & 0x01) != 0)
1630    }
1631    #[doc = "Bit 25 - Peripheral Chip Select Strobe Enable"]
1632    #[inline(always)]
1633    pub fn pcsse(&self) -> PCSSE_R {
1634        PCSSE_R::new(((self.bits >> 25) & 0x01) != 0)
1635    }
1636    #[doc = "Bit 26 - Modified Transfer Format Enable"]
1637    #[inline(always)]
1638    pub fn mtfe(&self) -> MTFE_R {
1639        MTFE_R::new(((self.bits >> 26) & 0x01) != 0)
1640    }
1641    #[doc = "Bit 27 - Freeze"]
1642    #[inline(always)]
1643    pub fn frz(&self) -> FRZ_R {
1644        FRZ_R::new(((self.bits >> 27) & 0x01) != 0)
1645    }
1646    #[doc = "Bits 28:29 - SPI Configuration."]
1647    #[inline(always)]
1648    pub fn dconf(&self) -> DCONF_R {
1649        DCONF_R::new(((self.bits >> 28) & 0x03) as u8)
1650    }
1651    #[doc = "Bit 30 - Continuous SCK Enable"]
1652    #[inline(always)]
1653    pub fn cont_scke(&self) -> CONT_SCKE_R {
1654        CONT_SCKE_R::new(((self.bits >> 30) & 0x01) != 0)
1655    }
1656    #[doc = "Bit 31 - Master/Slave Mode Select"]
1657    #[inline(always)]
1658    pub fn mstr(&self) -> MSTR_R {
1659        MSTR_R::new(((self.bits >> 31) & 0x01) != 0)
1660    }
1661}
1662impl W {
1663    #[doc = "Bit 0 - Halt"]
1664    #[inline(always)]
1665    pub fn halt(&mut self) -> HALT_W {
1666        HALT_W { w: self }
1667    }
1668    #[doc = "Bits 8:9 - Sample Point"]
1669    #[inline(always)]
1670    pub fn smpl_pt(&mut self) -> SMPL_PT_W {
1671        SMPL_PT_W { w: self }
1672    }
1673    #[doc = "Bit 10 - CLR_RXF"]
1674    #[inline(always)]
1675    pub fn clr_rxf(&mut self) -> CLR_RXF_W {
1676        CLR_RXF_W { w: self }
1677    }
1678    #[doc = "Bit 11 - Clear TX FIFO"]
1679    #[inline(always)]
1680    pub fn clr_txf(&mut self) -> CLR_TXF_W {
1681        CLR_TXF_W { w: self }
1682    }
1683    #[doc = "Bit 12 - Disable Receive FIFO"]
1684    #[inline(always)]
1685    pub fn dis_rxf(&mut self) -> DIS_RXF_W {
1686        DIS_RXF_W { w: self }
1687    }
1688    #[doc = "Bit 13 - Disable Transmit FIFO"]
1689    #[inline(always)]
1690    pub fn dis_txf(&mut self) -> DIS_TXF_W {
1691        DIS_TXF_W { w: self }
1692    }
1693    #[doc = "Bit 14 - Module Disable"]
1694    #[inline(always)]
1695    pub fn mdis(&mut self) -> MDIS_W {
1696        MDIS_W { w: self }
1697    }
1698    #[doc = "Bit 15 - Doze Enable"]
1699    #[inline(always)]
1700    pub fn doze(&mut self) -> DOZE_W {
1701        DOZE_W { w: self }
1702    }
1703    #[doc = "Bit 16 - Peripheral Chip Select x Inactive State"]
1704    #[inline(always)]
1705    pub fn pcsis0(&mut self) -> PCSIS0_W {
1706        PCSIS0_W { w: self }
1707    }
1708    #[doc = "Bit 17 - Peripheral Chip Select x Inactive State"]
1709    #[inline(always)]
1710    pub fn pcsis1(&mut self) -> PCSIS1_W {
1711        PCSIS1_W { w: self }
1712    }
1713    #[doc = "Bit 18 - Peripheral Chip Select x Inactive State"]
1714    #[inline(always)]
1715    pub fn pcsis2(&mut self) -> PCSIS2_W {
1716        PCSIS2_W { w: self }
1717    }
1718    #[doc = "Bit 19 - Peripheral Chip Select x Inactive State"]
1719    #[inline(always)]
1720    pub fn pcsis3(&mut self) -> PCSIS3_W {
1721        PCSIS3_W { w: self }
1722    }
1723    #[doc = "Bit 20 - Peripheral Chip Select x Inactive State"]
1724    #[inline(always)]
1725    pub fn pcsis4(&mut self) -> PCSIS4_W {
1726        PCSIS4_W { w: self }
1727    }
1728    #[doc = "Bit 21 - Peripheral Chip Select x Inactive State"]
1729    #[inline(always)]
1730    pub fn pcsis5(&mut self) -> PCSIS5_W {
1731        PCSIS5_W { w: self }
1732    }
1733    #[doc = "Bit 24 - Receive FIFO Overflow Overwrite Enable"]
1734    #[inline(always)]
1735    pub fn rooe(&mut self) -> ROOE_W {
1736        ROOE_W { w: self }
1737    }
1738    #[doc = "Bit 25 - Peripheral Chip Select Strobe Enable"]
1739    #[inline(always)]
1740    pub fn pcsse(&mut self) -> PCSSE_W {
1741        PCSSE_W { w: self }
1742    }
1743    #[doc = "Bit 26 - Modified Transfer Format Enable"]
1744    #[inline(always)]
1745    pub fn mtfe(&mut self) -> MTFE_W {
1746        MTFE_W { w: self }
1747    }
1748    #[doc = "Bit 27 - Freeze"]
1749    #[inline(always)]
1750    pub fn frz(&mut self) -> FRZ_W {
1751        FRZ_W { w: self }
1752    }
1753    #[doc = "Bit 30 - Continuous SCK Enable"]
1754    #[inline(always)]
1755    pub fn cont_scke(&mut self) -> CONT_SCKE_W {
1756        CONT_SCKE_W { w: self }
1757    }
1758    #[doc = "Bit 31 - Master/Slave Mode Select"]
1759    #[inline(always)]
1760    pub fn mstr(&mut self) -> MSTR_W {
1761        MSTR_W { w: self }
1762    }
1763}
mk66f18/spi1/mcr.rs

mk66f18/spi1/
mcr.rs
