1#[doc = "Reader of register ISFR"]
2pub type R = crate::R<u32, super::ISFR>;
3#[doc = "Writer for register ISFR"]
4pub type W = crate::W<u32, super::ISFR>;
5#[doc = "Register ISFR `reset()`'s with value 0"]
6impl crate::ResetValue for super::ISFR {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15pub enum ISF0_A {
16 #[doc = "0: Configured interrupt is not detected."]
17 _0,
18 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
19 _1,
20}
21impl From<ISF0_A> for bool {
22 #[inline(always)]
23 fn from(variant: ISF0_A) -> Self {
24 match variant {
25 ISF0_A::_0 => false,
26 ISF0_A::_1 => true,
27 }
28 }
29}
30#[doc = "Reader of field `ISF0`"]
31pub type ISF0_R = crate::R<bool, ISF0_A>;
32impl ISF0_R {
33 #[doc = r"Get enumerated values variant"]
34 #[inline(always)]
35 pub fn variant(&self) -> ISF0_A {
36 match self.bits {
37 false => ISF0_A::_0,
38 true => ISF0_A::_1,
39 }
40 }
41 #[doc = "Checks if the value of the field is `_0`"]
42 #[inline(always)]
43 pub fn is_0(&self) -> bool {
44 *self == ISF0_A::_0
45 }
46 #[doc = "Checks if the value of the field is `_1`"]
47 #[inline(always)]
48 pub fn is_1(&self) -> bool {
49 *self == ISF0_A::_1
50 }
51}
52#[doc = "Write proxy for field `ISF0`"]
53pub struct ISF0_W<'a> {
54 w: &'a mut W,
55}
56impl<'a> ISF0_W<'a> {
57 #[doc = r"Writes `variant` to the field"]
58 #[inline(always)]
59 pub fn variant(self, variant: ISF0_A) -> &'a mut W {
60 {
61 self.bit(variant.into())
62 }
63 }
64 #[doc = "Configured interrupt is not detected."]
65 #[inline(always)]
66 pub fn _0(self) -> &'a mut W {
67 self.variant(ISF0_A::_0)
68 }
69 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
70 #[inline(always)]
71 pub fn _1(self) -> &'a mut W {
72 self.variant(ISF0_A::_1)
73 }
74 #[doc = r"Sets the field bit"]
75 #[inline(always)]
76 pub fn set_bit(self) -> &'a mut W {
77 self.bit(true)
78 }
79 #[doc = r"Clears the field bit"]
80 #[inline(always)]
81 pub fn clear_bit(self) -> &'a mut W {
82 self.bit(false)
83 }
84 #[doc = r"Writes raw bits to the field"]
85 #[inline(always)]
86 pub fn bit(self, value: bool) -> &'a mut W {
87 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
88 self.w
89 }
90}
91#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq)]
93pub enum ISF1_A {
94 #[doc = "0: Configured interrupt is not detected."]
95 _0,
96 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
97 _1,
98}
99impl From<ISF1_A> for bool {
100 #[inline(always)]
101 fn from(variant: ISF1_A) -> Self {
102 match variant {
103 ISF1_A::_0 => false,
104 ISF1_A::_1 => true,
105 }
106 }
107}
108#[doc = "Reader of field `ISF1`"]
109pub type ISF1_R = crate::R<bool, ISF1_A>;
110impl ISF1_R {
111 #[doc = r"Get enumerated values variant"]
112 #[inline(always)]
113 pub fn variant(&self) -> ISF1_A {
114 match self.bits {
115 false => ISF1_A::_0,
116 true => ISF1_A::_1,
117 }
118 }
119 #[doc = "Checks if the value of the field is `_0`"]
120 #[inline(always)]
121 pub fn is_0(&self) -> bool {
122 *self == ISF1_A::_0
123 }
124 #[doc = "Checks if the value of the field is `_1`"]
125 #[inline(always)]
126 pub fn is_1(&self) -> bool {
127 *self == ISF1_A::_1
128 }
129}
130#[doc = "Write proxy for field `ISF1`"]
131pub struct ISF1_W<'a> {
132 w: &'a mut W,
133}
134impl<'a> ISF1_W<'a> {
135 #[doc = r"Writes `variant` to the field"]
136 #[inline(always)]
137 pub fn variant(self, variant: ISF1_A) -> &'a mut W {
138 {
139 self.bit(variant.into())
140 }
141 }
142 #[doc = "Configured interrupt is not detected."]
143 #[inline(always)]
144 pub fn _0(self) -> &'a mut W {
145 self.variant(ISF1_A::_0)
146 }
147 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
148 #[inline(always)]
149 pub fn _1(self) -> &'a mut W {
150 self.variant(ISF1_A::_1)
151 }
152 #[doc = r"Sets the field bit"]
153 #[inline(always)]
154 pub fn set_bit(self) -> &'a mut W {
155 self.bit(true)
156 }
157 #[doc = r"Clears the field bit"]
158 #[inline(always)]
159 pub fn clear_bit(self) -> &'a mut W {
160 self.bit(false)
161 }
162 #[doc = r"Writes raw bits to the field"]
163 #[inline(always)]
164 pub fn bit(self, value: bool) -> &'a mut W {
165 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
166 self.w
167 }
168}
169#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
170#[derive(Clone, Copy, Debug, PartialEq)]
171pub enum ISF2_A {
172 #[doc = "0: Configured interrupt is not detected."]
173 _0,
174 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
175 _1,
176}
177impl From<ISF2_A> for bool {
178 #[inline(always)]
179 fn from(variant: ISF2_A) -> Self {
180 match variant {
181 ISF2_A::_0 => false,
182 ISF2_A::_1 => true,
183 }
184 }
185}
186#[doc = "Reader of field `ISF2`"]
187pub type ISF2_R = crate::R<bool, ISF2_A>;
188impl ISF2_R {
189 #[doc = r"Get enumerated values variant"]
190 #[inline(always)]
191 pub fn variant(&self) -> ISF2_A {
192 match self.bits {
193 false => ISF2_A::_0,
194 true => ISF2_A::_1,
195 }
196 }
197 #[doc = "Checks if the value of the field is `_0`"]
198 #[inline(always)]
199 pub fn is_0(&self) -> bool {
200 *self == ISF2_A::_0
201 }
202 #[doc = "Checks if the value of the field is `_1`"]
203 #[inline(always)]
204 pub fn is_1(&self) -> bool {
205 *self == ISF2_A::_1
206 }
207}
208#[doc = "Write proxy for field `ISF2`"]
209pub struct ISF2_W<'a> {
210 w: &'a mut W,
211}
212impl<'a> ISF2_W<'a> {
213 #[doc = r"Writes `variant` to the field"]
214 #[inline(always)]
215 pub fn variant(self, variant: ISF2_A) -> &'a mut W {
216 {
217 self.bit(variant.into())
218 }
219 }
220 #[doc = "Configured interrupt is not detected."]
221 #[inline(always)]
222 pub fn _0(self) -> &'a mut W {
223 self.variant(ISF2_A::_0)
224 }
225 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
226 #[inline(always)]
227 pub fn _1(self) -> &'a mut W {
228 self.variant(ISF2_A::_1)
229 }
230 #[doc = r"Sets the field bit"]
231 #[inline(always)]
232 pub fn set_bit(self) -> &'a mut W {
233 self.bit(true)
234 }
235 #[doc = r"Clears the field bit"]
236 #[inline(always)]
237 pub fn clear_bit(self) -> &'a mut W {
238 self.bit(false)
239 }
240 #[doc = r"Writes raw bits to the field"]
241 #[inline(always)]
242 pub fn bit(self, value: bool) -> &'a mut W {
243 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
244 self.w
245 }
246}
247#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
248#[derive(Clone, Copy, Debug, PartialEq)]
249pub enum ISF3_A {
250 #[doc = "0: Configured interrupt is not detected."]
251 _0,
252 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
253 _1,
254}
255impl From<ISF3_A> for bool {
256 #[inline(always)]
257 fn from(variant: ISF3_A) -> Self {
258 match variant {
259 ISF3_A::_0 => false,
260 ISF3_A::_1 => true,
261 }
262 }
263}
264#[doc = "Reader of field `ISF3`"]
265pub type ISF3_R = crate::R<bool, ISF3_A>;
266impl ISF3_R {
267 #[doc = r"Get enumerated values variant"]
268 #[inline(always)]
269 pub fn variant(&self) -> ISF3_A {
270 match self.bits {
271 false => ISF3_A::_0,
272 true => ISF3_A::_1,
273 }
274 }
275 #[doc = "Checks if the value of the field is `_0`"]
276 #[inline(always)]
277 pub fn is_0(&self) -> bool {
278 *self == ISF3_A::_0
279 }
280 #[doc = "Checks if the value of the field is `_1`"]
281 #[inline(always)]
282 pub fn is_1(&self) -> bool {
283 *self == ISF3_A::_1
284 }
285}
286#[doc = "Write proxy for field `ISF3`"]
287pub struct ISF3_W<'a> {
288 w: &'a mut W,
289}
290impl<'a> ISF3_W<'a> {
291 #[doc = r"Writes `variant` to the field"]
292 #[inline(always)]
293 pub fn variant(self, variant: ISF3_A) -> &'a mut W {
294 {
295 self.bit(variant.into())
296 }
297 }
298 #[doc = "Configured interrupt is not detected."]
299 #[inline(always)]
300 pub fn _0(self) -> &'a mut W {
301 self.variant(ISF3_A::_0)
302 }
303 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
304 #[inline(always)]
305 pub fn _1(self) -> &'a mut W {
306 self.variant(ISF3_A::_1)
307 }
308 #[doc = r"Sets the field bit"]
309 #[inline(always)]
310 pub fn set_bit(self) -> &'a mut W {
311 self.bit(true)
312 }
313 #[doc = r"Clears the field bit"]
314 #[inline(always)]
315 pub fn clear_bit(self) -> &'a mut W {
316 self.bit(false)
317 }
318 #[doc = r"Writes raw bits to the field"]
319 #[inline(always)]
320 pub fn bit(self, value: bool) -> &'a mut W {
321 self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
322 self.w
323 }
324}
325#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
326#[derive(Clone, Copy, Debug, PartialEq)]
327pub enum ISF4_A {
328 #[doc = "0: Configured interrupt is not detected."]
329 _0,
330 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
331 _1,
332}
333impl From<ISF4_A> for bool {
334 #[inline(always)]
335 fn from(variant: ISF4_A) -> Self {
336 match variant {
337 ISF4_A::_0 => false,
338 ISF4_A::_1 => true,
339 }
340 }
341}
342#[doc = "Reader of field `ISF4`"]
343pub type ISF4_R = crate::R<bool, ISF4_A>;
344impl ISF4_R {
345 #[doc = r"Get enumerated values variant"]
346 #[inline(always)]
347 pub fn variant(&self) -> ISF4_A {
348 match self.bits {
349 false => ISF4_A::_0,
350 true => ISF4_A::_1,
351 }
352 }
353 #[doc = "Checks if the value of the field is `_0`"]
354 #[inline(always)]
355 pub fn is_0(&self) -> bool {
356 *self == ISF4_A::_0
357 }
358 #[doc = "Checks if the value of the field is `_1`"]
359 #[inline(always)]
360 pub fn is_1(&self) -> bool {
361 *self == ISF4_A::_1
362 }
363}
364#[doc = "Write proxy for field `ISF4`"]
365pub struct ISF4_W<'a> {
366 w: &'a mut W,
367}
368impl<'a> ISF4_W<'a> {
369 #[doc = r"Writes `variant` to the field"]
370 #[inline(always)]
371 pub fn variant(self, variant: ISF4_A) -> &'a mut W {
372 {
373 self.bit(variant.into())
374 }
375 }
376 #[doc = "Configured interrupt is not detected."]
377 #[inline(always)]
378 pub fn _0(self) -> &'a mut W {
379 self.variant(ISF4_A::_0)
380 }
381 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
382 #[inline(always)]
383 pub fn _1(self) -> &'a mut W {
384 self.variant(ISF4_A::_1)
385 }
386 #[doc = r"Sets the field bit"]
387 #[inline(always)]
388 pub fn set_bit(self) -> &'a mut W {
389 self.bit(true)
390 }
391 #[doc = r"Clears the field bit"]
392 #[inline(always)]
393 pub fn clear_bit(self) -> &'a mut W {
394 self.bit(false)
395 }
396 #[doc = r"Writes raw bits to the field"]
397 #[inline(always)]
398 pub fn bit(self, value: bool) -> &'a mut W {
399 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
400 self.w
401 }
402}
403#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
404#[derive(Clone, Copy, Debug, PartialEq)]
405pub enum ISF5_A {
406 #[doc = "0: Configured interrupt is not detected."]
407 _0,
408 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
409 _1,
410}
411impl From<ISF5_A> for bool {
412 #[inline(always)]
413 fn from(variant: ISF5_A) -> Self {
414 match variant {
415 ISF5_A::_0 => false,
416 ISF5_A::_1 => true,
417 }
418 }
419}
420#[doc = "Reader of field `ISF5`"]
421pub type ISF5_R = crate::R<bool, ISF5_A>;
422impl ISF5_R {
423 #[doc = r"Get enumerated values variant"]
424 #[inline(always)]
425 pub fn variant(&self) -> ISF5_A {
426 match self.bits {
427 false => ISF5_A::_0,
428 true => ISF5_A::_1,
429 }
430 }
431 #[doc = "Checks if the value of the field is `_0`"]
432 #[inline(always)]
433 pub fn is_0(&self) -> bool {
434 *self == ISF5_A::_0
435 }
436 #[doc = "Checks if the value of the field is `_1`"]
437 #[inline(always)]
438 pub fn is_1(&self) -> bool {
439 *self == ISF5_A::_1
440 }
441}
442#[doc = "Write proxy for field `ISF5`"]
443pub struct ISF5_W<'a> {
444 w: &'a mut W,
445}
446impl<'a> ISF5_W<'a> {
447 #[doc = r"Writes `variant` to the field"]
448 #[inline(always)]
449 pub fn variant(self, variant: ISF5_A) -> &'a mut W {
450 {
451 self.bit(variant.into())
452 }
453 }
454 #[doc = "Configured interrupt is not detected."]
455 #[inline(always)]
456 pub fn _0(self) -> &'a mut W {
457 self.variant(ISF5_A::_0)
458 }
459 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
460 #[inline(always)]
461 pub fn _1(self) -> &'a mut W {
462 self.variant(ISF5_A::_1)
463 }
464 #[doc = r"Sets the field bit"]
465 #[inline(always)]
466 pub fn set_bit(self) -> &'a mut W {
467 self.bit(true)
468 }
469 #[doc = r"Clears the field bit"]
470 #[inline(always)]
471 pub fn clear_bit(self) -> &'a mut W {
472 self.bit(false)
473 }
474 #[doc = r"Writes raw bits to the field"]
475 #[inline(always)]
476 pub fn bit(self, value: bool) -> &'a mut W {
477 self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
478 self.w
479 }
480}
481#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
482#[derive(Clone, Copy, Debug, PartialEq)]
483pub enum ISF6_A {
484 #[doc = "0: Configured interrupt is not detected."]
485 _0,
486 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
487 _1,
488}
489impl From<ISF6_A> for bool {
490 #[inline(always)]
491 fn from(variant: ISF6_A) -> Self {
492 match variant {
493 ISF6_A::_0 => false,
494 ISF6_A::_1 => true,
495 }
496 }
497}
498#[doc = "Reader of field `ISF6`"]
499pub type ISF6_R = crate::R<bool, ISF6_A>;
500impl ISF6_R {
501 #[doc = r"Get enumerated values variant"]
502 #[inline(always)]
503 pub fn variant(&self) -> ISF6_A {
504 match self.bits {
505 false => ISF6_A::_0,
506 true => ISF6_A::_1,
507 }
508 }
509 #[doc = "Checks if the value of the field is `_0`"]
510 #[inline(always)]
511 pub fn is_0(&self) -> bool {
512 *self == ISF6_A::_0
513 }
514 #[doc = "Checks if the value of the field is `_1`"]
515 #[inline(always)]
516 pub fn is_1(&self) -> bool {
517 *self == ISF6_A::_1
518 }
519}
520#[doc = "Write proxy for field `ISF6`"]
521pub struct ISF6_W<'a> {
522 w: &'a mut W,
523}
524impl<'a> ISF6_W<'a> {
525 #[doc = r"Writes `variant` to the field"]
526 #[inline(always)]
527 pub fn variant(self, variant: ISF6_A) -> &'a mut W {
528 {
529 self.bit(variant.into())
530 }
531 }
532 #[doc = "Configured interrupt is not detected."]
533 #[inline(always)]
534 pub fn _0(self) -> &'a mut W {
535 self.variant(ISF6_A::_0)
536 }
537 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
538 #[inline(always)]
539 pub fn _1(self) -> &'a mut W {
540 self.variant(ISF6_A::_1)
541 }
542 #[doc = r"Sets the field bit"]
543 #[inline(always)]
544 pub fn set_bit(self) -> &'a mut W {
545 self.bit(true)
546 }
547 #[doc = r"Clears the field bit"]
548 #[inline(always)]
549 pub fn clear_bit(self) -> &'a mut W {
550 self.bit(false)
551 }
552 #[doc = r"Writes raw bits to the field"]
553 #[inline(always)]
554 pub fn bit(self, value: bool) -> &'a mut W {
555 self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
556 self.w
557 }
558}
559#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
560#[derive(Clone, Copy, Debug, PartialEq)]
561pub enum ISF7_A {
562 #[doc = "0: Configured interrupt is not detected."]
563 _0,
564 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
565 _1,
566}
567impl From<ISF7_A> for bool {
568 #[inline(always)]
569 fn from(variant: ISF7_A) -> Self {
570 match variant {
571 ISF7_A::_0 => false,
572 ISF7_A::_1 => true,
573 }
574 }
575}
576#[doc = "Reader of field `ISF7`"]
577pub type ISF7_R = crate::R<bool, ISF7_A>;
578impl ISF7_R {
579 #[doc = r"Get enumerated values variant"]
580 #[inline(always)]
581 pub fn variant(&self) -> ISF7_A {
582 match self.bits {
583 false => ISF7_A::_0,
584 true => ISF7_A::_1,
585 }
586 }
587 #[doc = "Checks if the value of the field is `_0`"]
588 #[inline(always)]
589 pub fn is_0(&self) -> bool {
590 *self == ISF7_A::_0
591 }
592 #[doc = "Checks if the value of the field is `_1`"]
593 #[inline(always)]
594 pub fn is_1(&self) -> bool {
595 *self == ISF7_A::_1
596 }
597}
598#[doc = "Write proxy for field `ISF7`"]
599pub struct ISF7_W<'a> {
600 w: &'a mut W,
601}
602impl<'a> ISF7_W<'a> {
603 #[doc = r"Writes `variant` to the field"]
604 #[inline(always)]
605 pub fn variant(self, variant: ISF7_A) -> &'a mut W {
606 {
607 self.bit(variant.into())
608 }
609 }
610 #[doc = "Configured interrupt is not detected."]
611 #[inline(always)]
612 pub fn _0(self) -> &'a mut W {
613 self.variant(ISF7_A::_0)
614 }
615 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
616 #[inline(always)]
617 pub fn _1(self) -> &'a mut W {
618 self.variant(ISF7_A::_1)
619 }
620 #[doc = r"Sets the field bit"]
621 #[inline(always)]
622 pub fn set_bit(self) -> &'a mut W {
623 self.bit(true)
624 }
625 #[doc = r"Clears the field bit"]
626 #[inline(always)]
627 pub fn clear_bit(self) -> &'a mut W {
628 self.bit(false)
629 }
630 #[doc = r"Writes raw bits to the field"]
631 #[inline(always)]
632 pub fn bit(self, value: bool) -> &'a mut W {
633 self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
634 self.w
635 }
636}
637#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
638#[derive(Clone, Copy, Debug, PartialEq)]
639pub enum ISF8_A {
640 #[doc = "0: Configured interrupt is not detected."]
641 _0,
642 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
643 _1,
644}
645impl From<ISF8_A> for bool {
646 #[inline(always)]
647 fn from(variant: ISF8_A) -> Self {
648 match variant {
649 ISF8_A::_0 => false,
650 ISF8_A::_1 => true,
651 }
652 }
653}
654#[doc = "Reader of field `ISF8`"]
655pub type ISF8_R = crate::R<bool, ISF8_A>;
656impl ISF8_R {
657 #[doc = r"Get enumerated values variant"]
658 #[inline(always)]
659 pub fn variant(&self) -> ISF8_A {
660 match self.bits {
661 false => ISF8_A::_0,
662 true => ISF8_A::_1,
663 }
664 }
665 #[doc = "Checks if the value of the field is `_0`"]
666 #[inline(always)]
667 pub fn is_0(&self) -> bool {
668 *self == ISF8_A::_0
669 }
670 #[doc = "Checks if the value of the field is `_1`"]
671 #[inline(always)]
672 pub fn is_1(&self) -> bool {
673 *self == ISF8_A::_1
674 }
675}
676#[doc = "Write proxy for field `ISF8`"]
677pub struct ISF8_W<'a> {
678 w: &'a mut W,
679}
680impl<'a> ISF8_W<'a> {
681 #[doc = r"Writes `variant` to the field"]
682 #[inline(always)]
683 pub fn variant(self, variant: ISF8_A) -> &'a mut W {
684 {
685 self.bit(variant.into())
686 }
687 }
688 #[doc = "Configured interrupt is not detected."]
689 #[inline(always)]
690 pub fn _0(self) -> &'a mut W {
691 self.variant(ISF8_A::_0)
692 }
693 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
694 #[inline(always)]
695 pub fn _1(self) -> &'a mut W {
696 self.variant(ISF8_A::_1)
697 }
698 #[doc = r"Sets the field bit"]
699 #[inline(always)]
700 pub fn set_bit(self) -> &'a mut W {
701 self.bit(true)
702 }
703 #[doc = r"Clears the field bit"]
704 #[inline(always)]
705 pub fn clear_bit(self) -> &'a mut W {
706 self.bit(false)
707 }
708 #[doc = r"Writes raw bits to the field"]
709 #[inline(always)]
710 pub fn bit(self, value: bool) -> &'a mut W {
711 self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
712 self.w
713 }
714}
715#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
716#[derive(Clone, Copy, Debug, PartialEq)]
717pub enum ISF9_A {
718 #[doc = "0: Configured interrupt is not detected."]
719 _0,
720 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
721 _1,
722}
723impl From<ISF9_A> for bool {
724 #[inline(always)]
725 fn from(variant: ISF9_A) -> Self {
726 match variant {
727 ISF9_A::_0 => false,
728 ISF9_A::_1 => true,
729 }
730 }
731}
732#[doc = "Reader of field `ISF9`"]
733pub type ISF9_R = crate::R<bool, ISF9_A>;
734impl ISF9_R {
735 #[doc = r"Get enumerated values variant"]
736 #[inline(always)]
737 pub fn variant(&self) -> ISF9_A {
738 match self.bits {
739 false => ISF9_A::_0,
740 true => ISF9_A::_1,
741 }
742 }
743 #[doc = "Checks if the value of the field is `_0`"]
744 #[inline(always)]
745 pub fn is_0(&self) -> bool {
746 *self == ISF9_A::_0
747 }
748 #[doc = "Checks if the value of the field is `_1`"]
749 #[inline(always)]
750 pub fn is_1(&self) -> bool {
751 *self == ISF9_A::_1
752 }
753}
754#[doc = "Write proxy for field `ISF9`"]
755pub struct ISF9_W<'a> {
756 w: &'a mut W,
757}
758impl<'a> ISF9_W<'a> {
759 #[doc = r"Writes `variant` to the field"]
760 #[inline(always)]
761 pub fn variant(self, variant: ISF9_A) -> &'a mut W {
762 {
763 self.bit(variant.into())
764 }
765 }
766 #[doc = "Configured interrupt is not detected."]
767 #[inline(always)]
768 pub fn _0(self) -> &'a mut W {
769 self.variant(ISF9_A::_0)
770 }
771 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
772 #[inline(always)]
773 pub fn _1(self) -> &'a mut W {
774 self.variant(ISF9_A::_1)
775 }
776 #[doc = r"Sets the field bit"]
777 #[inline(always)]
778 pub fn set_bit(self) -> &'a mut W {
779 self.bit(true)
780 }
781 #[doc = r"Clears the field bit"]
782 #[inline(always)]
783 pub fn clear_bit(self) -> &'a mut W {
784 self.bit(false)
785 }
786 #[doc = r"Writes raw bits to the field"]
787 #[inline(always)]
788 pub fn bit(self, value: bool) -> &'a mut W {
789 self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
790 self.w
791 }
792}
793#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
794#[derive(Clone, Copy, Debug, PartialEq)]
795pub enum ISF10_A {
796 #[doc = "0: Configured interrupt is not detected."]
797 _0,
798 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
799 _1,
800}
801impl From<ISF10_A> for bool {
802 #[inline(always)]
803 fn from(variant: ISF10_A) -> Self {
804 match variant {
805 ISF10_A::_0 => false,
806 ISF10_A::_1 => true,
807 }
808 }
809}
810#[doc = "Reader of field `ISF10`"]
811pub type ISF10_R = crate::R<bool, ISF10_A>;
812impl ISF10_R {
813 #[doc = r"Get enumerated values variant"]
814 #[inline(always)]
815 pub fn variant(&self) -> ISF10_A {
816 match self.bits {
817 false => ISF10_A::_0,
818 true => ISF10_A::_1,
819 }
820 }
821 #[doc = "Checks if the value of the field is `_0`"]
822 #[inline(always)]
823 pub fn is_0(&self) -> bool {
824 *self == ISF10_A::_0
825 }
826 #[doc = "Checks if the value of the field is `_1`"]
827 #[inline(always)]
828 pub fn is_1(&self) -> bool {
829 *self == ISF10_A::_1
830 }
831}
832#[doc = "Write proxy for field `ISF10`"]
833pub struct ISF10_W<'a> {
834 w: &'a mut W,
835}
836impl<'a> ISF10_W<'a> {
837 #[doc = r"Writes `variant` to the field"]
838 #[inline(always)]
839 pub fn variant(self, variant: ISF10_A) -> &'a mut W {
840 {
841 self.bit(variant.into())
842 }
843 }
844 #[doc = "Configured interrupt is not detected."]
845 #[inline(always)]
846 pub fn _0(self) -> &'a mut W {
847 self.variant(ISF10_A::_0)
848 }
849 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
850 #[inline(always)]
851 pub fn _1(self) -> &'a mut W {
852 self.variant(ISF10_A::_1)
853 }
854 #[doc = r"Sets the field bit"]
855 #[inline(always)]
856 pub fn set_bit(self) -> &'a mut W {
857 self.bit(true)
858 }
859 #[doc = r"Clears the field bit"]
860 #[inline(always)]
861 pub fn clear_bit(self) -> &'a mut W {
862 self.bit(false)
863 }
864 #[doc = r"Writes raw bits to the field"]
865 #[inline(always)]
866 pub fn bit(self, value: bool) -> &'a mut W {
867 self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
868 self.w
869 }
870}
871#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
872#[derive(Clone, Copy, Debug, PartialEq)]
873pub enum ISF11_A {
874 #[doc = "0: Configured interrupt is not detected."]
875 _0,
876 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
877 _1,
878}
879impl From<ISF11_A> for bool {
880 #[inline(always)]
881 fn from(variant: ISF11_A) -> Self {
882 match variant {
883 ISF11_A::_0 => false,
884 ISF11_A::_1 => true,
885 }
886 }
887}
888#[doc = "Reader of field `ISF11`"]
889pub type ISF11_R = crate::R<bool, ISF11_A>;
890impl ISF11_R {
891 #[doc = r"Get enumerated values variant"]
892 #[inline(always)]
893 pub fn variant(&self) -> ISF11_A {
894 match self.bits {
895 false => ISF11_A::_0,
896 true => ISF11_A::_1,
897 }
898 }
899 #[doc = "Checks if the value of the field is `_0`"]
900 #[inline(always)]
901 pub fn is_0(&self) -> bool {
902 *self == ISF11_A::_0
903 }
904 #[doc = "Checks if the value of the field is `_1`"]
905 #[inline(always)]
906 pub fn is_1(&self) -> bool {
907 *self == ISF11_A::_1
908 }
909}
910#[doc = "Write proxy for field `ISF11`"]
911pub struct ISF11_W<'a> {
912 w: &'a mut W,
913}
914impl<'a> ISF11_W<'a> {
915 #[doc = r"Writes `variant` to the field"]
916 #[inline(always)]
917 pub fn variant(self, variant: ISF11_A) -> &'a mut W {
918 {
919 self.bit(variant.into())
920 }
921 }
922 #[doc = "Configured interrupt is not detected."]
923 #[inline(always)]
924 pub fn _0(self) -> &'a mut W {
925 self.variant(ISF11_A::_0)
926 }
927 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
928 #[inline(always)]
929 pub fn _1(self) -> &'a mut W {
930 self.variant(ISF11_A::_1)
931 }
932 #[doc = r"Sets the field bit"]
933 #[inline(always)]
934 pub fn set_bit(self) -> &'a mut W {
935 self.bit(true)
936 }
937 #[doc = r"Clears the field bit"]
938 #[inline(always)]
939 pub fn clear_bit(self) -> &'a mut W {
940 self.bit(false)
941 }
942 #[doc = r"Writes raw bits to the field"]
943 #[inline(always)]
944 pub fn bit(self, value: bool) -> &'a mut W {
945 self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
946 self.w
947 }
948}
949#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
950#[derive(Clone, Copy, Debug, PartialEq)]
951pub enum ISF12_A {
952 #[doc = "0: Configured interrupt is not detected."]
953 _0,
954 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
955 _1,
956}
957impl From<ISF12_A> for bool {
958 #[inline(always)]
959 fn from(variant: ISF12_A) -> Self {
960 match variant {
961 ISF12_A::_0 => false,
962 ISF12_A::_1 => true,
963 }
964 }
965}
966#[doc = "Reader of field `ISF12`"]
967pub type ISF12_R = crate::R<bool, ISF12_A>;
968impl ISF12_R {
969 #[doc = r"Get enumerated values variant"]
970 #[inline(always)]
971 pub fn variant(&self) -> ISF12_A {
972 match self.bits {
973 false => ISF12_A::_0,
974 true => ISF12_A::_1,
975 }
976 }
977 #[doc = "Checks if the value of the field is `_0`"]
978 #[inline(always)]
979 pub fn is_0(&self) -> bool {
980 *self == ISF12_A::_0
981 }
982 #[doc = "Checks if the value of the field is `_1`"]
983 #[inline(always)]
984 pub fn is_1(&self) -> bool {
985 *self == ISF12_A::_1
986 }
987}
988#[doc = "Write proxy for field `ISF12`"]
989pub struct ISF12_W<'a> {
990 w: &'a mut W,
991}
992impl<'a> ISF12_W<'a> {
993 #[doc = r"Writes `variant` to the field"]
994 #[inline(always)]
995 pub fn variant(self, variant: ISF12_A) -> &'a mut W {
996 {
997 self.bit(variant.into())
998 }
999 }
1000 #[doc = "Configured interrupt is not detected."]
1001 #[inline(always)]
1002 pub fn _0(self) -> &'a mut W {
1003 self.variant(ISF12_A::_0)
1004 }
1005 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1006 #[inline(always)]
1007 pub fn _1(self) -> &'a mut W {
1008 self.variant(ISF12_A::_1)
1009 }
1010 #[doc = r"Sets the field bit"]
1011 #[inline(always)]
1012 pub fn set_bit(self) -> &'a mut W {
1013 self.bit(true)
1014 }
1015 #[doc = r"Clears the field bit"]
1016 #[inline(always)]
1017 pub fn clear_bit(self) -> &'a mut W {
1018 self.bit(false)
1019 }
1020 #[doc = r"Writes raw bits to the field"]
1021 #[inline(always)]
1022 pub fn bit(self, value: bool) -> &'a mut W {
1023 self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
1024 self.w
1025 }
1026}
1027#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1028#[derive(Clone, Copy, Debug, PartialEq)]
1029pub enum ISF13_A {
1030 #[doc = "0: Configured interrupt is not detected."]
1031 _0,
1032 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1033 _1,
1034}
1035impl From<ISF13_A> for bool {
1036 #[inline(always)]
1037 fn from(variant: ISF13_A) -> Self {
1038 match variant {
1039 ISF13_A::_0 => false,
1040 ISF13_A::_1 => true,
1041 }
1042 }
1043}
1044#[doc = "Reader of field `ISF13`"]
1045pub type ISF13_R = crate::R<bool, ISF13_A>;
1046impl ISF13_R {
1047 #[doc = r"Get enumerated values variant"]
1048 #[inline(always)]
1049 pub fn variant(&self) -> ISF13_A {
1050 match self.bits {
1051 false => ISF13_A::_0,
1052 true => ISF13_A::_1,
1053 }
1054 }
1055 #[doc = "Checks if the value of the field is `_0`"]
1056 #[inline(always)]
1057 pub fn is_0(&self) -> bool {
1058 *self == ISF13_A::_0
1059 }
1060 #[doc = "Checks if the value of the field is `_1`"]
1061 #[inline(always)]
1062 pub fn is_1(&self) -> bool {
1063 *self == ISF13_A::_1
1064 }
1065}
1066#[doc = "Write proxy for field `ISF13`"]
1067pub struct ISF13_W<'a> {
1068 w: &'a mut W,
1069}
1070impl<'a> ISF13_W<'a> {
1071 #[doc = r"Writes `variant` to the field"]
1072 #[inline(always)]
1073 pub fn variant(self, variant: ISF13_A) -> &'a mut W {
1074 {
1075 self.bit(variant.into())
1076 }
1077 }
1078 #[doc = "Configured interrupt is not detected."]
1079 #[inline(always)]
1080 pub fn _0(self) -> &'a mut W {
1081 self.variant(ISF13_A::_0)
1082 }
1083 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1084 #[inline(always)]
1085 pub fn _1(self) -> &'a mut W {
1086 self.variant(ISF13_A::_1)
1087 }
1088 #[doc = r"Sets the field bit"]
1089 #[inline(always)]
1090 pub fn set_bit(self) -> &'a mut W {
1091 self.bit(true)
1092 }
1093 #[doc = r"Clears the field bit"]
1094 #[inline(always)]
1095 pub fn clear_bit(self) -> &'a mut W {
1096 self.bit(false)
1097 }
1098 #[doc = r"Writes raw bits to the field"]
1099 #[inline(always)]
1100 pub fn bit(self, value: bool) -> &'a mut W {
1101 self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
1102 self.w
1103 }
1104}
1105#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1106#[derive(Clone, Copy, Debug, PartialEq)]
1107pub enum ISF14_A {
1108 #[doc = "0: Configured interrupt is not detected."]
1109 _0,
1110 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1111 _1,
1112}
1113impl From<ISF14_A> for bool {
1114 #[inline(always)]
1115 fn from(variant: ISF14_A) -> Self {
1116 match variant {
1117 ISF14_A::_0 => false,
1118 ISF14_A::_1 => true,
1119 }
1120 }
1121}
1122#[doc = "Reader of field `ISF14`"]
1123pub type ISF14_R = crate::R<bool, ISF14_A>;
1124impl ISF14_R {
1125 #[doc = r"Get enumerated values variant"]
1126 #[inline(always)]
1127 pub fn variant(&self) -> ISF14_A {
1128 match self.bits {
1129 false => ISF14_A::_0,
1130 true => ISF14_A::_1,
1131 }
1132 }
1133 #[doc = "Checks if the value of the field is `_0`"]
1134 #[inline(always)]
1135 pub fn is_0(&self) -> bool {
1136 *self == ISF14_A::_0
1137 }
1138 #[doc = "Checks if the value of the field is `_1`"]
1139 #[inline(always)]
1140 pub fn is_1(&self) -> bool {
1141 *self == ISF14_A::_1
1142 }
1143}
1144#[doc = "Write proxy for field `ISF14`"]
1145pub struct ISF14_W<'a> {
1146 w: &'a mut W,
1147}
1148impl<'a> ISF14_W<'a> {
1149 #[doc = r"Writes `variant` to the field"]
1150 #[inline(always)]
1151 pub fn variant(self, variant: ISF14_A) -> &'a mut W {
1152 {
1153 self.bit(variant.into())
1154 }
1155 }
1156 #[doc = "Configured interrupt is not detected."]
1157 #[inline(always)]
1158 pub fn _0(self) -> &'a mut W {
1159 self.variant(ISF14_A::_0)
1160 }
1161 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1162 #[inline(always)]
1163 pub fn _1(self) -> &'a mut W {
1164 self.variant(ISF14_A::_1)
1165 }
1166 #[doc = r"Sets the field bit"]
1167 #[inline(always)]
1168 pub fn set_bit(self) -> &'a mut W {
1169 self.bit(true)
1170 }
1171 #[doc = r"Clears the field bit"]
1172 #[inline(always)]
1173 pub fn clear_bit(self) -> &'a mut W {
1174 self.bit(false)
1175 }
1176 #[doc = r"Writes raw bits to the field"]
1177 #[inline(always)]
1178 pub fn bit(self, value: bool) -> &'a mut W {
1179 self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
1180 self.w
1181 }
1182}
1183#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1184#[derive(Clone, Copy, Debug, PartialEq)]
1185pub enum ISF15_A {
1186 #[doc = "0: Configured interrupt is not detected."]
1187 _0,
1188 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1189 _1,
1190}
1191impl From<ISF15_A> for bool {
1192 #[inline(always)]
1193 fn from(variant: ISF15_A) -> Self {
1194 match variant {
1195 ISF15_A::_0 => false,
1196 ISF15_A::_1 => true,
1197 }
1198 }
1199}
1200#[doc = "Reader of field `ISF15`"]
1201pub type ISF15_R = crate::R<bool, ISF15_A>;
1202impl ISF15_R {
1203 #[doc = r"Get enumerated values variant"]
1204 #[inline(always)]
1205 pub fn variant(&self) -> ISF15_A {
1206 match self.bits {
1207 false => ISF15_A::_0,
1208 true => ISF15_A::_1,
1209 }
1210 }
1211 #[doc = "Checks if the value of the field is `_0`"]
1212 #[inline(always)]
1213 pub fn is_0(&self) -> bool {
1214 *self == ISF15_A::_0
1215 }
1216 #[doc = "Checks if the value of the field is `_1`"]
1217 #[inline(always)]
1218 pub fn is_1(&self) -> bool {
1219 *self == ISF15_A::_1
1220 }
1221}
1222#[doc = "Write proxy for field `ISF15`"]
1223pub struct ISF15_W<'a> {
1224 w: &'a mut W,
1225}
1226impl<'a> ISF15_W<'a> {
1227 #[doc = r"Writes `variant` to the field"]
1228 #[inline(always)]
1229 pub fn variant(self, variant: ISF15_A) -> &'a mut W {
1230 {
1231 self.bit(variant.into())
1232 }
1233 }
1234 #[doc = "Configured interrupt is not detected."]
1235 #[inline(always)]
1236 pub fn _0(self) -> &'a mut W {
1237 self.variant(ISF15_A::_0)
1238 }
1239 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1240 #[inline(always)]
1241 pub fn _1(self) -> &'a mut W {
1242 self.variant(ISF15_A::_1)
1243 }
1244 #[doc = r"Sets the field bit"]
1245 #[inline(always)]
1246 pub fn set_bit(self) -> &'a mut W {
1247 self.bit(true)
1248 }
1249 #[doc = r"Clears the field bit"]
1250 #[inline(always)]
1251 pub fn clear_bit(self) -> &'a mut W {
1252 self.bit(false)
1253 }
1254 #[doc = r"Writes raw bits to the field"]
1255 #[inline(always)]
1256 pub fn bit(self, value: bool) -> &'a mut W {
1257 self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
1258 self.w
1259 }
1260}
1261#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1262#[derive(Clone, Copy, Debug, PartialEq)]
1263pub enum ISF16_A {
1264 #[doc = "0: Configured interrupt is not detected."]
1265 _0,
1266 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1267 _1,
1268}
1269impl From<ISF16_A> for bool {
1270 #[inline(always)]
1271 fn from(variant: ISF16_A) -> Self {
1272 match variant {
1273 ISF16_A::_0 => false,
1274 ISF16_A::_1 => true,
1275 }
1276 }
1277}
1278#[doc = "Reader of field `ISF16`"]
1279pub type ISF16_R = crate::R<bool, ISF16_A>;
1280impl ISF16_R {
1281 #[doc = r"Get enumerated values variant"]
1282 #[inline(always)]
1283 pub fn variant(&self) -> ISF16_A {
1284 match self.bits {
1285 false => ISF16_A::_0,
1286 true => ISF16_A::_1,
1287 }
1288 }
1289 #[doc = "Checks if the value of the field is `_0`"]
1290 #[inline(always)]
1291 pub fn is_0(&self) -> bool {
1292 *self == ISF16_A::_0
1293 }
1294 #[doc = "Checks if the value of the field is `_1`"]
1295 #[inline(always)]
1296 pub fn is_1(&self) -> bool {
1297 *self == ISF16_A::_1
1298 }
1299}
1300#[doc = "Write proxy for field `ISF16`"]
1301pub struct ISF16_W<'a> {
1302 w: &'a mut W,
1303}
1304impl<'a> ISF16_W<'a> {
1305 #[doc = r"Writes `variant` to the field"]
1306 #[inline(always)]
1307 pub fn variant(self, variant: ISF16_A) -> &'a mut W {
1308 {
1309 self.bit(variant.into())
1310 }
1311 }
1312 #[doc = "Configured interrupt is not detected."]
1313 #[inline(always)]
1314 pub fn _0(self) -> &'a mut W {
1315 self.variant(ISF16_A::_0)
1316 }
1317 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1318 #[inline(always)]
1319 pub fn _1(self) -> &'a mut W {
1320 self.variant(ISF16_A::_1)
1321 }
1322 #[doc = r"Sets the field bit"]
1323 #[inline(always)]
1324 pub fn set_bit(self) -> &'a mut W {
1325 self.bit(true)
1326 }
1327 #[doc = r"Clears the field bit"]
1328 #[inline(always)]
1329 pub fn clear_bit(self) -> &'a mut W {
1330 self.bit(false)
1331 }
1332 #[doc = r"Writes raw bits to the field"]
1333 #[inline(always)]
1334 pub fn bit(self, value: bool) -> &'a mut W {
1335 self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
1336 self.w
1337 }
1338}
1339#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1340#[derive(Clone, Copy, Debug, PartialEq)]
1341pub enum ISF17_A {
1342 #[doc = "0: Configured interrupt is not detected."]
1343 _0,
1344 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1345 _1,
1346}
1347impl From<ISF17_A> for bool {
1348 #[inline(always)]
1349 fn from(variant: ISF17_A) -> Self {
1350 match variant {
1351 ISF17_A::_0 => false,
1352 ISF17_A::_1 => true,
1353 }
1354 }
1355}
1356#[doc = "Reader of field `ISF17`"]
1357pub type ISF17_R = crate::R<bool, ISF17_A>;
1358impl ISF17_R {
1359 #[doc = r"Get enumerated values variant"]
1360 #[inline(always)]
1361 pub fn variant(&self) -> ISF17_A {
1362 match self.bits {
1363 false => ISF17_A::_0,
1364 true => ISF17_A::_1,
1365 }
1366 }
1367 #[doc = "Checks if the value of the field is `_0`"]
1368 #[inline(always)]
1369 pub fn is_0(&self) -> bool {
1370 *self == ISF17_A::_0
1371 }
1372 #[doc = "Checks if the value of the field is `_1`"]
1373 #[inline(always)]
1374 pub fn is_1(&self) -> bool {
1375 *self == ISF17_A::_1
1376 }
1377}
1378#[doc = "Write proxy for field `ISF17`"]
1379pub struct ISF17_W<'a> {
1380 w: &'a mut W,
1381}
1382impl<'a> ISF17_W<'a> {
1383 #[doc = r"Writes `variant` to the field"]
1384 #[inline(always)]
1385 pub fn variant(self, variant: ISF17_A) -> &'a mut W {
1386 {
1387 self.bit(variant.into())
1388 }
1389 }
1390 #[doc = "Configured interrupt is not detected."]
1391 #[inline(always)]
1392 pub fn _0(self) -> &'a mut W {
1393 self.variant(ISF17_A::_0)
1394 }
1395 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1396 #[inline(always)]
1397 pub fn _1(self) -> &'a mut W {
1398 self.variant(ISF17_A::_1)
1399 }
1400 #[doc = r"Sets the field bit"]
1401 #[inline(always)]
1402 pub fn set_bit(self) -> &'a mut W {
1403 self.bit(true)
1404 }
1405 #[doc = r"Clears the field bit"]
1406 #[inline(always)]
1407 pub fn clear_bit(self) -> &'a mut W {
1408 self.bit(false)
1409 }
1410 #[doc = r"Writes raw bits to the field"]
1411 #[inline(always)]
1412 pub fn bit(self, value: bool) -> &'a mut W {
1413 self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
1414 self.w
1415 }
1416}
1417#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1418#[derive(Clone, Copy, Debug, PartialEq)]
1419pub enum ISF18_A {
1420 #[doc = "0: Configured interrupt is not detected."]
1421 _0,
1422 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1423 _1,
1424}
1425impl From<ISF18_A> for bool {
1426 #[inline(always)]
1427 fn from(variant: ISF18_A) -> Self {
1428 match variant {
1429 ISF18_A::_0 => false,
1430 ISF18_A::_1 => true,
1431 }
1432 }
1433}
1434#[doc = "Reader of field `ISF18`"]
1435pub type ISF18_R = crate::R<bool, ISF18_A>;
1436impl ISF18_R {
1437 #[doc = r"Get enumerated values variant"]
1438 #[inline(always)]
1439 pub fn variant(&self) -> ISF18_A {
1440 match self.bits {
1441 false => ISF18_A::_0,
1442 true => ISF18_A::_1,
1443 }
1444 }
1445 #[doc = "Checks if the value of the field is `_0`"]
1446 #[inline(always)]
1447 pub fn is_0(&self) -> bool {
1448 *self == ISF18_A::_0
1449 }
1450 #[doc = "Checks if the value of the field is `_1`"]
1451 #[inline(always)]
1452 pub fn is_1(&self) -> bool {
1453 *self == ISF18_A::_1
1454 }
1455}
1456#[doc = "Write proxy for field `ISF18`"]
1457pub struct ISF18_W<'a> {
1458 w: &'a mut W,
1459}
1460impl<'a> ISF18_W<'a> {
1461 #[doc = r"Writes `variant` to the field"]
1462 #[inline(always)]
1463 pub fn variant(self, variant: ISF18_A) -> &'a mut W {
1464 {
1465 self.bit(variant.into())
1466 }
1467 }
1468 #[doc = "Configured interrupt is not detected."]
1469 #[inline(always)]
1470 pub fn _0(self) -> &'a mut W {
1471 self.variant(ISF18_A::_0)
1472 }
1473 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1474 #[inline(always)]
1475 pub fn _1(self) -> &'a mut W {
1476 self.variant(ISF18_A::_1)
1477 }
1478 #[doc = r"Sets the field bit"]
1479 #[inline(always)]
1480 pub fn set_bit(self) -> &'a mut W {
1481 self.bit(true)
1482 }
1483 #[doc = r"Clears the field bit"]
1484 #[inline(always)]
1485 pub fn clear_bit(self) -> &'a mut W {
1486 self.bit(false)
1487 }
1488 #[doc = r"Writes raw bits to the field"]
1489 #[inline(always)]
1490 pub fn bit(self, value: bool) -> &'a mut W {
1491 self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
1492 self.w
1493 }
1494}
1495#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1496#[derive(Clone, Copy, Debug, PartialEq)]
1497pub enum ISF19_A {
1498 #[doc = "0: Configured interrupt is not detected."]
1499 _0,
1500 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1501 _1,
1502}
1503impl From<ISF19_A> for bool {
1504 #[inline(always)]
1505 fn from(variant: ISF19_A) -> Self {
1506 match variant {
1507 ISF19_A::_0 => false,
1508 ISF19_A::_1 => true,
1509 }
1510 }
1511}
1512#[doc = "Reader of field `ISF19`"]
1513pub type ISF19_R = crate::R<bool, ISF19_A>;
1514impl ISF19_R {
1515 #[doc = r"Get enumerated values variant"]
1516 #[inline(always)]
1517 pub fn variant(&self) -> ISF19_A {
1518 match self.bits {
1519 false => ISF19_A::_0,
1520 true => ISF19_A::_1,
1521 }
1522 }
1523 #[doc = "Checks if the value of the field is `_0`"]
1524 #[inline(always)]
1525 pub fn is_0(&self) -> bool {
1526 *self == ISF19_A::_0
1527 }
1528 #[doc = "Checks if the value of the field is `_1`"]
1529 #[inline(always)]
1530 pub fn is_1(&self) -> bool {
1531 *self == ISF19_A::_1
1532 }
1533}
1534#[doc = "Write proxy for field `ISF19`"]
1535pub struct ISF19_W<'a> {
1536 w: &'a mut W,
1537}
1538impl<'a> ISF19_W<'a> {
1539 #[doc = r"Writes `variant` to the field"]
1540 #[inline(always)]
1541 pub fn variant(self, variant: ISF19_A) -> &'a mut W {
1542 {
1543 self.bit(variant.into())
1544 }
1545 }
1546 #[doc = "Configured interrupt is not detected."]
1547 #[inline(always)]
1548 pub fn _0(self) -> &'a mut W {
1549 self.variant(ISF19_A::_0)
1550 }
1551 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1552 #[inline(always)]
1553 pub fn _1(self) -> &'a mut W {
1554 self.variant(ISF19_A::_1)
1555 }
1556 #[doc = r"Sets the field bit"]
1557 #[inline(always)]
1558 pub fn set_bit(self) -> &'a mut W {
1559 self.bit(true)
1560 }
1561 #[doc = r"Clears the field bit"]
1562 #[inline(always)]
1563 pub fn clear_bit(self) -> &'a mut W {
1564 self.bit(false)
1565 }
1566 #[doc = r"Writes raw bits to the field"]
1567 #[inline(always)]
1568 pub fn bit(self, value: bool) -> &'a mut W {
1569 self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
1570 self.w
1571 }
1572}
1573#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1574#[derive(Clone, Copy, Debug, PartialEq)]
1575pub enum ISF20_A {
1576 #[doc = "0: Configured interrupt is not detected."]
1577 _0,
1578 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1579 _1,
1580}
1581impl From<ISF20_A> for bool {
1582 #[inline(always)]
1583 fn from(variant: ISF20_A) -> Self {
1584 match variant {
1585 ISF20_A::_0 => false,
1586 ISF20_A::_1 => true,
1587 }
1588 }
1589}
1590#[doc = "Reader of field `ISF20`"]
1591pub type ISF20_R = crate::R<bool, ISF20_A>;
1592impl ISF20_R {
1593 #[doc = r"Get enumerated values variant"]
1594 #[inline(always)]
1595 pub fn variant(&self) -> ISF20_A {
1596 match self.bits {
1597 false => ISF20_A::_0,
1598 true => ISF20_A::_1,
1599 }
1600 }
1601 #[doc = "Checks if the value of the field is `_0`"]
1602 #[inline(always)]
1603 pub fn is_0(&self) -> bool {
1604 *self == ISF20_A::_0
1605 }
1606 #[doc = "Checks if the value of the field is `_1`"]
1607 #[inline(always)]
1608 pub fn is_1(&self) -> bool {
1609 *self == ISF20_A::_1
1610 }
1611}
1612#[doc = "Write proxy for field `ISF20`"]
1613pub struct ISF20_W<'a> {
1614 w: &'a mut W,
1615}
1616impl<'a> ISF20_W<'a> {
1617 #[doc = r"Writes `variant` to the field"]
1618 #[inline(always)]
1619 pub fn variant(self, variant: ISF20_A) -> &'a mut W {
1620 {
1621 self.bit(variant.into())
1622 }
1623 }
1624 #[doc = "Configured interrupt is not detected."]
1625 #[inline(always)]
1626 pub fn _0(self) -> &'a mut W {
1627 self.variant(ISF20_A::_0)
1628 }
1629 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1630 #[inline(always)]
1631 pub fn _1(self) -> &'a mut W {
1632 self.variant(ISF20_A::_1)
1633 }
1634 #[doc = r"Sets the field bit"]
1635 #[inline(always)]
1636 pub fn set_bit(self) -> &'a mut W {
1637 self.bit(true)
1638 }
1639 #[doc = r"Clears the field bit"]
1640 #[inline(always)]
1641 pub fn clear_bit(self) -> &'a mut W {
1642 self.bit(false)
1643 }
1644 #[doc = r"Writes raw bits to the field"]
1645 #[inline(always)]
1646 pub fn bit(self, value: bool) -> &'a mut W {
1647 self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
1648 self.w
1649 }
1650}
1651#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1652#[derive(Clone, Copy, Debug, PartialEq)]
1653pub enum ISF21_A {
1654 #[doc = "0: Configured interrupt is not detected."]
1655 _0,
1656 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1657 _1,
1658}
1659impl From<ISF21_A> for bool {
1660 #[inline(always)]
1661 fn from(variant: ISF21_A) -> Self {
1662 match variant {
1663 ISF21_A::_0 => false,
1664 ISF21_A::_1 => true,
1665 }
1666 }
1667}
1668#[doc = "Reader of field `ISF21`"]
1669pub type ISF21_R = crate::R<bool, ISF21_A>;
1670impl ISF21_R {
1671 #[doc = r"Get enumerated values variant"]
1672 #[inline(always)]
1673 pub fn variant(&self) -> ISF21_A {
1674 match self.bits {
1675 false => ISF21_A::_0,
1676 true => ISF21_A::_1,
1677 }
1678 }
1679 #[doc = "Checks if the value of the field is `_0`"]
1680 #[inline(always)]
1681 pub fn is_0(&self) -> bool {
1682 *self == ISF21_A::_0
1683 }
1684 #[doc = "Checks if the value of the field is `_1`"]
1685 #[inline(always)]
1686 pub fn is_1(&self) -> bool {
1687 *self == ISF21_A::_1
1688 }
1689}
1690#[doc = "Write proxy for field `ISF21`"]
1691pub struct ISF21_W<'a> {
1692 w: &'a mut W,
1693}
1694impl<'a> ISF21_W<'a> {
1695 #[doc = r"Writes `variant` to the field"]
1696 #[inline(always)]
1697 pub fn variant(self, variant: ISF21_A) -> &'a mut W {
1698 {
1699 self.bit(variant.into())
1700 }
1701 }
1702 #[doc = "Configured interrupt is not detected."]
1703 #[inline(always)]
1704 pub fn _0(self) -> &'a mut W {
1705 self.variant(ISF21_A::_0)
1706 }
1707 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1708 #[inline(always)]
1709 pub fn _1(self) -> &'a mut W {
1710 self.variant(ISF21_A::_1)
1711 }
1712 #[doc = r"Sets the field bit"]
1713 #[inline(always)]
1714 pub fn set_bit(self) -> &'a mut W {
1715 self.bit(true)
1716 }
1717 #[doc = r"Clears the field bit"]
1718 #[inline(always)]
1719 pub fn clear_bit(self) -> &'a mut W {
1720 self.bit(false)
1721 }
1722 #[doc = r"Writes raw bits to the field"]
1723 #[inline(always)]
1724 pub fn bit(self, value: bool) -> &'a mut W {
1725 self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
1726 self.w
1727 }
1728}
1729#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1730#[derive(Clone, Copy, Debug, PartialEq)]
1731pub enum ISF22_A {
1732 #[doc = "0: Configured interrupt is not detected."]
1733 _0,
1734 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1735 _1,
1736}
1737impl From<ISF22_A> for bool {
1738 #[inline(always)]
1739 fn from(variant: ISF22_A) -> Self {
1740 match variant {
1741 ISF22_A::_0 => false,
1742 ISF22_A::_1 => true,
1743 }
1744 }
1745}
1746#[doc = "Reader of field `ISF22`"]
1747pub type ISF22_R = crate::R<bool, ISF22_A>;
1748impl ISF22_R {
1749 #[doc = r"Get enumerated values variant"]
1750 #[inline(always)]
1751 pub fn variant(&self) -> ISF22_A {
1752 match self.bits {
1753 false => ISF22_A::_0,
1754 true => ISF22_A::_1,
1755 }
1756 }
1757 #[doc = "Checks if the value of the field is `_0`"]
1758 #[inline(always)]
1759 pub fn is_0(&self) -> bool {
1760 *self == ISF22_A::_0
1761 }
1762 #[doc = "Checks if the value of the field is `_1`"]
1763 #[inline(always)]
1764 pub fn is_1(&self) -> bool {
1765 *self == ISF22_A::_1
1766 }
1767}
1768#[doc = "Write proxy for field `ISF22`"]
1769pub struct ISF22_W<'a> {
1770 w: &'a mut W,
1771}
1772impl<'a> ISF22_W<'a> {
1773 #[doc = r"Writes `variant` to the field"]
1774 #[inline(always)]
1775 pub fn variant(self, variant: ISF22_A) -> &'a mut W {
1776 {
1777 self.bit(variant.into())
1778 }
1779 }
1780 #[doc = "Configured interrupt is not detected."]
1781 #[inline(always)]
1782 pub fn _0(self) -> &'a mut W {
1783 self.variant(ISF22_A::_0)
1784 }
1785 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1786 #[inline(always)]
1787 pub fn _1(self) -> &'a mut W {
1788 self.variant(ISF22_A::_1)
1789 }
1790 #[doc = r"Sets the field bit"]
1791 #[inline(always)]
1792 pub fn set_bit(self) -> &'a mut W {
1793 self.bit(true)
1794 }
1795 #[doc = r"Clears the field bit"]
1796 #[inline(always)]
1797 pub fn clear_bit(self) -> &'a mut W {
1798 self.bit(false)
1799 }
1800 #[doc = r"Writes raw bits to the field"]
1801 #[inline(always)]
1802 pub fn bit(self, value: bool) -> &'a mut W {
1803 self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
1804 self.w
1805 }
1806}
1807#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1808#[derive(Clone, Copy, Debug, PartialEq)]
1809pub enum ISF23_A {
1810 #[doc = "0: Configured interrupt is not detected."]
1811 _0,
1812 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1813 _1,
1814}
1815impl From<ISF23_A> for bool {
1816 #[inline(always)]
1817 fn from(variant: ISF23_A) -> Self {
1818 match variant {
1819 ISF23_A::_0 => false,
1820 ISF23_A::_1 => true,
1821 }
1822 }
1823}
1824#[doc = "Reader of field `ISF23`"]
1825pub type ISF23_R = crate::R<bool, ISF23_A>;
1826impl ISF23_R {
1827 #[doc = r"Get enumerated values variant"]
1828 #[inline(always)]
1829 pub fn variant(&self) -> ISF23_A {
1830 match self.bits {
1831 false => ISF23_A::_0,
1832 true => ISF23_A::_1,
1833 }
1834 }
1835 #[doc = "Checks if the value of the field is `_0`"]
1836 #[inline(always)]
1837 pub fn is_0(&self) -> bool {
1838 *self == ISF23_A::_0
1839 }
1840 #[doc = "Checks if the value of the field is `_1`"]
1841 #[inline(always)]
1842 pub fn is_1(&self) -> bool {
1843 *self == ISF23_A::_1
1844 }
1845}
1846#[doc = "Write proxy for field `ISF23`"]
1847pub struct ISF23_W<'a> {
1848 w: &'a mut W,
1849}
1850impl<'a> ISF23_W<'a> {
1851 #[doc = r"Writes `variant` to the field"]
1852 #[inline(always)]
1853 pub fn variant(self, variant: ISF23_A) -> &'a mut W {
1854 {
1855 self.bit(variant.into())
1856 }
1857 }
1858 #[doc = "Configured interrupt is not detected."]
1859 #[inline(always)]
1860 pub fn _0(self) -> &'a mut W {
1861 self.variant(ISF23_A::_0)
1862 }
1863 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1864 #[inline(always)]
1865 pub fn _1(self) -> &'a mut W {
1866 self.variant(ISF23_A::_1)
1867 }
1868 #[doc = r"Sets the field bit"]
1869 #[inline(always)]
1870 pub fn set_bit(self) -> &'a mut W {
1871 self.bit(true)
1872 }
1873 #[doc = r"Clears the field bit"]
1874 #[inline(always)]
1875 pub fn clear_bit(self) -> &'a mut W {
1876 self.bit(false)
1877 }
1878 #[doc = r"Writes raw bits to the field"]
1879 #[inline(always)]
1880 pub fn bit(self, value: bool) -> &'a mut W {
1881 self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
1882 self.w
1883 }
1884}
1885#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1886#[derive(Clone, Copy, Debug, PartialEq)]
1887pub enum ISF24_A {
1888 #[doc = "0: Configured interrupt is not detected."]
1889 _0,
1890 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1891 _1,
1892}
1893impl From<ISF24_A> for bool {
1894 #[inline(always)]
1895 fn from(variant: ISF24_A) -> Self {
1896 match variant {
1897 ISF24_A::_0 => false,
1898 ISF24_A::_1 => true,
1899 }
1900 }
1901}
1902#[doc = "Reader of field `ISF24`"]
1903pub type ISF24_R = crate::R<bool, ISF24_A>;
1904impl ISF24_R {
1905 #[doc = r"Get enumerated values variant"]
1906 #[inline(always)]
1907 pub fn variant(&self) -> ISF24_A {
1908 match self.bits {
1909 false => ISF24_A::_0,
1910 true => ISF24_A::_1,
1911 }
1912 }
1913 #[doc = "Checks if the value of the field is `_0`"]
1914 #[inline(always)]
1915 pub fn is_0(&self) -> bool {
1916 *self == ISF24_A::_0
1917 }
1918 #[doc = "Checks if the value of the field is `_1`"]
1919 #[inline(always)]
1920 pub fn is_1(&self) -> bool {
1921 *self == ISF24_A::_1
1922 }
1923}
1924#[doc = "Write proxy for field `ISF24`"]
1925pub struct ISF24_W<'a> {
1926 w: &'a mut W,
1927}
1928impl<'a> ISF24_W<'a> {
1929 #[doc = r"Writes `variant` to the field"]
1930 #[inline(always)]
1931 pub fn variant(self, variant: ISF24_A) -> &'a mut W {
1932 {
1933 self.bit(variant.into())
1934 }
1935 }
1936 #[doc = "Configured interrupt is not detected."]
1937 #[inline(always)]
1938 pub fn _0(self) -> &'a mut W {
1939 self.variant(ISF24_A::_0)
1940 }
1941 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1942 #[inline(always)]
1943 pub fn _1(self) -> &'a mut W {
1944 self.variant(ISF24_A::_1)
1945 }
1946 #[doc = r"Sets the field bit"]
1947 #[inline(always)]
1948 pub fn set_bit(self) -> &'a mut W {
1949 self.bit(true)
1950 }
1951 #[doc = r"Clears the field bit"]
1952 #[inline(always)]
1953 pub fn clear_bit(self) -> &'a mut W {
1954 self.bit(false)
1955 }
1956 #[doc = r"Writes raw bits to the field"]
1957 #[inline(always)]
1958 pub fn bit(self, value: bool) -> &'a mut W {
1959 self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
1960 self.w
1961 }
1962}
1963#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
1964#[derive(Clone, Copy, Debug, PartialEq)]
1965pub enum ISF25_A {
1966 #[doc = "0: Configured interrupt is not detected."]
1967 _0,
1968 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1969 _1,
1970}
1971impl From<ISF25_A> for bool {
1972 #[inline(always)]
1973 fn from(variant: ISF25_A) -> Self {
1974 match variant {
1975 ISF25_A::_0 => false,
1976 ISF25_A::_1 => true,
1977 }
1978 }
1979}
1980#[doc = "Reader of field `ISF25`"]
1981pub type ISF25_R = crate::R<bool, ISF25_A>;
1982impl ISF25_R {
1983 #[doc = r"Get enumerated values variant"]
1984 #[inline(always)]
1985 pub fn variant(&self) -> ISF25_A {
1986 match self.bits {
1987 false => ISF25_A::_0,
1988 true => ISF25_A::_1,
1989 }
1990 }
1991 #[doc = "Checks if the value of the field is `_0`"]
1992 #[inline(always)]
1993 pub fn is_0(&self) -> bool {
1994 *self == ISF25_A::_0
1995 }
1996 #[doc = "Checks if the value of the field is `_1`"]
1997 #[inline(always)]
1998 pub fn is_1(&self) -> bool {
1999 *self == ISF25_A::_1
2000 }
2001}
2002#[doc = "Write proxy for field `ISF25`"]
2003pub struct ISF25_W<'a> {
2004 w: &'a mut W,
2005}
2006impl<'a> ISF25_W<'a> {
2007 #[doc = r"Writes `variant` to the field"]
2008 #[inline(always)]
2009 pub fn variant(self, variant: ISF25_A) -> &'a mut W {
2010 {
2011 self.bit(variant.into())
2012 }
2013 }
2014 #[doc = "Configured interrupt is not detected."]
2015 #[inline(always)]
2016 pub fn _0(self) -> &'a mut W {
2017 self.variant(ISF25_A::_0)
2018 }
2019 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2020 #[inline(always)]
2021 pub fn _1(self) -> &'a mut W {
2022 self.variant(ISF25_A::_1)
2023 }
2024 #[doc = r"Sets the field bit"]
2025 #[inline(always)]
2026 pub fn set_bit(self) -> &'a mut W {
2027 self.bit(true)
2028 }
2029 #[doc = r"Clears the field bit"]
2030 #[inline(always)]
2031 pub fn clear_bit(self) -> &'a mut W {
2032 self.bit(false)
2033 }
2034 #[doc = r"Writes raw bits to the field"]
2035 #[inline(always)]
2036 pub fn bit(self, value: bool) -> &'a mut W {
2037 self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
2038 self.w
2039 }
2040}
2041#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
2042#[derive(Clone, Copy, Debug, PartialEq)]
2043pub enum ISF26_A {
2044 #[doc = "0: Configured interrupt is not detected."]
2045 _0,
2046 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2047 _1,
2048}
2049impl From<ISF26_A> for bool {
2050 #[inline(always)]
2051 fn from(variant: ISF26_A) -> Self {
2052 match variant {
2053 ISF26_A::_0 => false,
2054 ISF26_A::_1 => true,
2055 }
2056 }
2057}
2058#[doc = "Reader of field `ISF26`"]
2059pub type ISF26_R = crate::R<bool, ISF26_A>;
2060impl ISF26_R {
2061 #[doc = r"Get enumerated values variant"]
2062 #[inline(always)]
2063 pub fn variant(&self) -> ISF26_A {
2064 match self.bits {
2065 false => ISF26_A::_0,
2066 true => ISF26_A::_1,
2067 }
2068 }
2069 #[doc = "Checks if the value of the field is `_0`"]
2070 #[inline(always)]
2071 pub fn is_0(&self) -> bool {
2072 *self == ISF26_A::_0
2073 }
2074 #[doc = "Checks if the value of the field is `_1`"]
2075 #[inline(always)]
2076 pub fn is_1(&self) -> bool {
2077 *self == ISF26_A::_1
2078 }
2079}
2080#[doc = "Write proxy for field `ISF26`"]
2081pub struct ISF26_W<'a> {
2082 w: &'a mut W,
2083}
2084impl<'a> ISF26_W<'a> {
2085 #[doc = r"Writes `variant` to the field"]
2086 #[inline(always)]
2087 pub fn variant(self, variant: ISF26_A) -> &'a mut W {
2088 {
2089 self.bit(variant.into())
2090 }
2091 }
2092 #[doc = "Configured interrupt is not detected."]
2093 #[inline(always)]
2094 pub fn _0(self) -> &'a mut W {
2095 self.variant(ISF26_A::_0)
2096 }
2097 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2098 #[inline(always)]
2099 pub fn _1(self) -> &'a mut W {
2100 self.variant(ISF26_A::_1)
2101 }
2102 #[doc = r"Sets the field bit"]
2103 #[inline(always)]
2104 pub fn set_bit(self) -> &'a mut W {
2105 self.bit(true)
2106 }
2107 #[doc = r"Clears the field bit"]
2108 #[inline(always)]
2109 pub fn clear_bit(self) -> &'a mut W {
2110 self.bit(false)
2111 }
2112 #[doc = r"Writes raw bits to the field"]
2113 #[inline(always)]
2114 pub fn bit(self, value: bool) -> &'a mut W {
2115 self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
2116 self.w
2117 }
2118}
2119#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
2120#[derive(Clone, Copy, Debug, PartialEq)]
2121pub enum ISF27_A {
2122 #[doc = "0: Configured interrupt is not detected."]
2123 _0,
2124 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2125 _1,
2126}
2127impl From<ISF27_A> for bool {
2128 #[inline(always)]
2129 fn from(variant: ISF27_A) -> Self {
2130 match variant {
2131 ISF27_A::_0 => false,
2132 ISF27_A::_1 => true,
2133 }
2134 }
2135}
2136#[doc = "Reader of field `ISF27`"]
2137pub type ISF27_R = crate::R<bool, ISF27_A>;
2138impl ISF27_R {
2139 #[doc = r"Get enumerated values variant"]
2140 #[inline(always)]
2141 pub fn variant(&self) -> ISF27_A {
2142 match self.bits {
2143 false => ISF27_A::_0,
2144 true => ISF27_A::_1,
2145 }
2146 }
2147 #[doc = "Checks if the value of the field is `_0`"]
2148 #[inline(always)]
2149 pub fn is_0(&self) -> bool {
2150 *self == ISF27_A::_0
2151 }
2152 #[doc = "Checks if the value of the field is `_1`"]
2153 #[inline(always)]
2154 pub fn is_1(&self) -> bool {
2155 *self == ISF27_A::_1
2156 }
2157}
2158#[doc = "Write proxy for field `ISF27`"]
2159pub struct ISF27_W<'a> {
2160 w: &'a mut W,
2161}
2162impl<'a> ISF27_W<'a> {
2163 #[doc = r"Writes `variant` to the field"]
2164 #[inline(always)]
2165 pub fn variant(self, variant: ISF27_A) -> &'a mut W {
2166 {
2167 self.bit(variant.into())
2168 }
2169 }
2170 #[doc = "Configured interrupt is not detected."]
2171 #[inline(always)]
2172 pub fn _0(self) -> &'a mut W {
2173 self.variant(ISF27_A::_0)
2174 }
2175 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2176 #[inline(always)]
2177 pub fn _1(self) -> &'a mut W {
2178 self.variant(ISF27_A::_1)
2179 }
2180 #[doc = r"Sets the field bit"]
2181 #[inline(always)]
2182 pub fn set_bit(self) -> &'a mut W {
2183 self.bit(true)
2184 }
2185 #[doc = r"Clears the field bit"]
2186 #[inline(always)]
2187 pub fn clear_bit(self) -> &'a mut W {
2188 self.bit(false)
2189 }
2190 #[doc = r"Writes raw bits to the field"]
2191 #[inline(always)]
2192 pub fn bit(self, value: bool) -> &'a mut W {
2193 self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
2194 self.w
2195 }
2196}
2197#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
2198#[derive(Clone, Copy, Debug, PartialEq)]
2199pub enum ISF28_A {
2200 #[doc = "0: Configured interrupt is not detected."]
2201 _0,
2202 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2203 _1,
2204}
2205impl From<ISF28_A> for bool {
2206 #[inline(always)]
2207 fn from(variant: ISF28_A) -> Self {
2208 match variant {
2209 ISF28_A::_0 => false,
2210 ISF28_A::_1 => true,
2211 }
2212 }
2213}
2214#[doc = "Reader of field `ISF28`"]
2215pub type ISF28_R = crate::R<bool, ISF28_A>;
2216impl ISF28_R {
2217 #[doc = r"Get enumerated values variant"]
2218 #[inline(always)]
2219 pub fn variant(&self) -> ISF28_A {
2220 match self.bits {
2221 false => ISF28_A::_0,
2222 true => ISF28_A::_1,
2223 }
2224 }
2225 #[doc = "Checks if the value of the field is `_0`"]
2226 #[inline(always)]
2227 pub fn is_0(&self) -> bool {
2228 *self == ISF28_A::_0
2229 }
2230 #[doc = "Checks if the value of the field is `_1`"]
2231 #[inline(always)]
2232 pub fn is_1(&self) -> bool {
2233 *self == ISF28_A::_1
2234 }
2235}
2236#[doc = "Write proxy for field `ISF28`"]
2237pub struct ISF28_W<'a> {
2238 w: &'a mut W,
2239}
2240impl<'a> ISF28_W<'a> {
2241 #[doc = r"Writes `variant` to the field"]
2242 #[inline(always)]
2243 pub fn variant(self, variant: ISF28_A) -> &'a mut W {
2244 {
2245 self.bit(variant.into())
2246 }
2247 }
2248 #[doc = "Configured interrupt is not detected."]
2249 #[inline(always)]
2250 pub fn _0(self) -> &'a mut W {
2251 self.variant(ISF28_A::_0)
2252 }
2253 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2254 #[inline(always)]
2255 pub fn _1(self) -> &'a mut W {
2256 self.variant(ISF28_A::_1)
2257 }
2258 #[doc = r"Sets the field bit"]
2259 #[inline(always)]
2260 pub fn set_bit(self) -> &'a mut W {
2261 self.bit(true)
2262 }
2263 #[doc = r"Clears the field bit"]
2264 #[inline(always)]
2265 pub fn clear_bit(self) -> &'a mut W {
2266 self.bit(false)
2267 }
2268 #[doc = r"Writes raw bits to the field"]
2269 #[inline(always)]
2270 pub fn bit(self, value: bool) -> &'a mut W {
2271 self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
2272 self.w
2273 }
2274}
2275#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
2276#[derive(Clone, Copy, Debug, PartialEq)]
2277pub enum ISF29_A {
2278 #[doc = "0: Configured interrupt is not detected."]
2279 _0,
2280 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2281 _1,
2282}
2283impl From<ISF29_A> for bool {
2284 #[inline(always)]
2285 fn from(variant: ISF29_A) -> Self {
2286 match variant {
2287 ISF29_A::_0 => false,
2288 ISF29_A::_1 => true,
2289 }
2290 }
2291}
2292#[doc = "Reader of field `ISF29`"]
2293pub type ISF29_R = crate::R<bool, ISF29_A>;
2294impl ISF29_R {
2295 #[doc = r"Get enumerated values variant"]
2296 #[inline(always)]
2297 pub fn variant(&self) -> ISF29_A {
2298 match self.bits {
2299 false => ISF29_A::_0,
2300 true => ISF29_A::_1,
2301 }
2302 }
2303 #[doc = "Checks if the value of the field is `_0`"]
2304 #[inline(always)]
2305 pub fn is_0(&self) -> bool {
2306 *self == ISF29_A::_0
2307 }
2308 #[doc = "Checks if the value of the field is `_1`"]
2309 #[inline(always)]
2310 pub fn is_1(&self) -> bool {
2311 *self == ISF29_A::_1
2312 }
2313}
2314#[doc = "Write proxy for field `ISF29`"]
2315pub struct ISF29_W<'a> {
2316 w: &'a mut W,
2317}
2318impl<'a> ISF29_W<'a> {
2319 #[doc = r"Writes `variant` to the field"]
2320 #[inline(always)]
2321 pub fn variant(self, variant: ISF29_A) -> &'a mut W {
2322 {
2323 self.bit(variant.into())
2324 }
2325 }
2326 #[doc = "Configured interrupt is not detected."]
2327 #[inline(always)]
2328 pub fn _0(self) -> &'a mut W {
2329 self.variant(ISF29_A::_0)
2330 }
2331 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2332 #[inline(always)]
2333 pub fn _1(self) -> &'a mut W {
2334 self.variant(ISF29_A::_1)
2335 }
2336 #[doc = r"Sets the field bit"]
2337 #[inline(always)]
2338 pub fn set_bit(self) -> &'a mut W {
2339 self.bit(true)
2340 }
2341 #[doc = r"Clears the field bit"]
2342 #[inline(always)]
2343 pub fn clear_bit(self) -> &'a mut W {
2344 self.bit(false)
2345 }
2346 #[doc = r"Writes raw bits to the field"]
2347 #[inline(always)]
2348 pub fn bit(self, value: bool) -> &'a mut W {
2349 self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
2350 self.w
2351 }
2352}
2353#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
2354#[derive(Clone, Copy, Debug, PartialEq)]
2355pub enum ISF30_A {
2356 #[doc = "0: Configured interrupt is not detected."]
2357 _0,
2358 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2359 _1,
2360}
2361impl From<ISF30_A> for bool {
2362 #[inline(always)]
2363 fn from(variant: ISF30_A) -> Self {
2364 match variant {
2365 ISF30_A::_0 => false,
2366 ISF30_A::_1 => true,
2367 }
2368 }
2369}
2370#[doc = "Reader of field `ISF30`"]
2371pub type ISF30_R = crate::R<bool, ISF30_A>;
2372impl ISF30_R {
2373 #[doc = r"Get enumerated values variant"]
2374 #[inline(always)]
2375 pub fn variant(&self) -> ISF30_A {
2376 match self.bits {
2377 false => ISF30_A::_0,
2378 true => ISF30_A::_1,
2379 }
2380 }
2381 #[doc = "Checks if the value of the field is `_0`"]
2382 #[inline(always)]
2383 pub fn is_0(&self) -> bool {
2384 *self == ISF30_A::_0
2385 }
2386 #[doc = "Checks if the value of the field is `_1`"]
2387 #[inline(always)]
2388 pub fn is_1(&self) -> bool {
2389 *self == ISF30_A::_1
2390 }
2391}
2392#[doc = "Write proxy for field `ISF30`"]
2393pub struct ISF30_W<'a> {
2394 w: &'a mut W,
2395}
2396impl<'a> ISF30_W<'a> {
2397 #[doc = r"Writes `variant` to the field"]
2398 #[inline(always)]
2399 pub fn variant(self, variant: ISF30_A) -> &'a mut W {
2400 {
2401 self.bit(variant.into())
2402 }
2403 }
2404 #[doc = "Configured interrupt is not detected."]
2405 #[inline(always)]
2406 pub fn _0(self) -> &'a mut W {
2407 self.variant(ISF30_A::_0)
2408 }
2409 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2410 #[inline(always)]
2411 pub fn _1(self) -> &'a mut W {
2412 self.variant(ISF30_A::_1)
2413 }
2414 #[doc = r"Sets the field bit"]
2415 #[inline(always)]
2416 pub fn set_bit(self) -> &'a mut W {
2417 self.bit(true)
2418 }
2419 #[doc = r"Clears the field bit"]
2420 #[inline(always)]
2421 pub fn clear_bit(self) -> &'a mut W {
2422 self.bit(false)
2423 }
2424 #[doc = r"Writes raw bits to the field"]
2425 #[inline(always)]
2426 pub fn bit(self, value: bool) -> &'a mut W {
2427 self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
2428 self.w
2429 }
2430}
2431#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
2432#[derive(Clone, Copy, Debug, PartialEq)]
2433pub enum ISF31_A {
2434 #[doc = "0: Configured interrupt is not detected."]
2435 _0,
2436 #[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2437 _1,
2438}
2439impl From<ISF31_A> for bool {
2440 #[inline(always)]
2441 fn from(variant: ISF31_A) -> Self {
2442 match variant {
2443 ISF31_A::_0 => false,
2444 ISF31_A::_1 => true,
2445 }
2446 }
2447}
2448#[doc = "Reader of field `ISF31`"]
2449pub type ISF31_R = crate::R<bool, ISF31_A>;
2450impl ISF31_R {
2451 #[doc = r"Get enumerated values variant"]
2452 #[inline(always)]
2453 pub fn variant(&self) -> ISF31_A {
2454 match self.bits {
2455 false => ISF31_A::_0,
2456 true => ISF31_A::_1,
2457 }
2458 }
2459 #[doc = "Checks if the value of the field is `_0`"]
2460 #[inline(always)]
2461 pub fn is_0(&self) -> bool {
2462 *self == ISF31_A::_0
2463 }
2464 #[doc = "Checks if the value of the field is `_1`"]
2465 #[inline(always)]
2466 pub fn is_1(&self) -> bool {
2467 *self == ISF31_A::_1
2468 }
2469}
2470#[doc = "Write proxy for field `ISF31`"]
2471pub struct ISF31_W<'a> {
2472 w: &'a mut W,
2473}
2474impl<'a> ISF31_W<'a> {
2475 #[doc = r"Writes `variant` to the field"]
2476 #[inline(always)]
2477 pub fn variant(self, variant: ISF31_A) -> &'a mut W {
2478 {
2479 self.bit(variant.into())
2480 }
2481 }
2482 #[doc = "Configured interrupt is not detected."]
2483 #[inline(always)]
2484 pub fn _0(self) -> &'a mut W {
2485 self.variant(ISF31_A::_0)
2486 }
2487 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
2488 #[inline(always)]
2489 pub fn _1(self) -> &'a mut W {
2490 self.variant(ISF31_A::_1)
2491 }
2492 #[doc = r"Sets the field bit"]
2493 #[inline(always)]
2494 pub fn set_bit(self) -> &'a mut W {
2495 self.bit(true)
2496 }
2497 #[doc = r"Clears the field bit"]
2498 #[inline(always)]
2499 pub fn clear_bit(self) -> &'a mut W {
2500 self.bit(false)
2501 }
2502 #[doc = r"Writes raw bits to the field"]
2503 #[inline(always)]
2504 pub fn bit(self, value: bool) -> &'a mut W {
2505 self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
2506 self.w
2507 }
2508}
2509impl R {
2510 #[doc = "Bit 0 - Interrupt Status Flag"]
2511 #[inline(always)]
2512 pub fn isf0(&self) -> ISF0_R {
2513 ISF0_R::new((self.bits & 0x01) != 0)
2514 }
2515 #[doc = "Bit 1 - Interrupt Status Flag"]
2516 #[inline(always)]
2517 pub fn isf1(&self) -> ISF1_R {
2518 ISF1_R::new(((self.bits >> 1) & 0x01) != 0)
2519 }
2520 #[doc = "Bit 2 - Interrupt Status Flag"]
2521 #[inline(always)]
2522 pub fn isf2(&self) -> ISF2_R {
2523 ISF2_R::new(((self.bits >> 2) & 0x01) != 0)
2524 }
2525 #[doc = "Bit 3 - Interrupt Status Flag"]
2526 #[inline(always)]
2527 pub fn isf3(&self) -> ISF3_R {
2528 ISF3_R::new(((self.bits >> 3) & 0x01) != 0)
2529 }
2530 #[doc = "Bit 4 - Interrupt Status Flag"]
2531 #[inline(always)]
2532 pub fn isf4(&self) -> ISF4_R {
2533 ISF4_R::new(((self.bits >> 4) & 0x01) != 0)
2534 }
2535 #[doc = "Bit 5 - Interrupt Status Flag"]
2536 #[inline(always)]
2537 pub fn isf5(&self) -> ISF5_R {
2538 ISF5_R::new(((self.bits >> 5) & 0x01) != 0)
2539 }
2540 #[doc = "Bit 6 - Interrupt Status Flag"]
2541 #[inline(always)]
2542 pub fn isf6(&self) -> ISF6_R {
2543 ISF6_R::new(((self.bits >> 6) & 0x01) != 0)
2544 }
2545 #[doc = "Bit 7 - Interrupt Status Flag"]
2546 #[inline(always)]
2547 pub fn isf7(&self) -> ISF7_R {
2548 ISF7_R::new(((self.bits >> 7) & 0x01) != 0)
2549 }
2550 #[doc = "Bit 8 - Interrupt Status Flag"]
2551 #[inline(always)]
2552 pub fn isf8(&self) -> ISF8_R {
2553 ISF8_R::new(((self.bits >> 8) & 0x01) != 0)
2554 }
2555 #[doc = "Bit 9 - Interrupt Status Flag"]
2556 #[inline(always)]
2557 pub fn isf9(&self) -> ISF9_R {
2558 ISF9_R::new(((self.bits >> 9) & 0x01) != 0)
2559 }
2560 #[doc = "Bit 10 - Interrupt Status Flag"]
2561 #[inline(always)]
2562 pub fn isf10(&self) -> ISF10_R {
2563 ISF10_R::new(((self.bits >> 10) & 0x01) != 0)
2564 }
2565 #[doc = "Bit 11 - Interrupt Status Flag"]
2566 #[inline(always)]
2567 pub fn isf11(&self) -> ISF11_R {
2568 ISF11_R::new(((self.bits >> 11) & 0x01) != 0)
2569 }
2570 #[doc = "Bit 12 - Interrupt Status Flag"]
2571 #[inline(always)]
2572 pub fn isf12(&self) -> ISF12_R {
2573 ISF12_R::new(((self.bits >> 12) & 0x01) != 0)
2574 }
2575 #[doc = "Bit 13 - Interrupt Status Flag"]
2576 #[inline(always)]
2577 pub fn isf13(&self) -> ISF13_R {
2578 ISF13_R::new(((self.bits >> 13) & 0x01) != 0)
2579 }
2580 #[doc = "Bit 14 - Interrupt Status Flag"]
2581 #[inline(always)]
2582 pub fn isf14(&self) -> ISF14_R {
2583 ISF14_R::new(((self.bits >> 14) & 0x01) != 0)
2584 }
2585 #[doc = "Bit 15 - Interrupt Status Flag"]
2586 #[inline(always)]
2587 pub fn isf15(&self) -> ISF15_R {
2588 ISF15_R::new(((self.bits >> 15) & 0x01) != 0)
2589 }
2590 #[doc = "Bit 16 - Interrupt Status Flag"]
2591 #[inline(always)]
2592 pub fn isf16(&self) -> ISF16_R {
2593 ISF16_R::new(((self.bits >> 16) & 0x01) != 0)
2594 }
2595 #[doc = "Bit 17 - Interrupt Status Flag"]
2596 #[inline(always)]
2597 pub fn isf17(&self) -> ISF17_R {
2598 ISF17_R::new(((self.bits >> 17) & 0x01) != 0)
2599 }
2600 #[doc = "Bit 18 - Interrupt Status Flag"]
2601 #[inline(always)]
2602 pub fn isf18(&self) -> ISF18_R {
2603 ISF18_R::new(((self.bits >> 18) & 0x01) != 0)
2604 }
2605 #[doc = "Bit 19 - Interrupt Status Flag"]
2606 #[inline(always)]
2607 pub fn isf19(&self) -> ISF19_R {
2608 ISF19_R::new(((self.bits >> 19) & 0x01) != 0)
2609 }
2610 #[doc = "Bit 20 - Interrupt Status Flag"]
2611 #[inline(always)]
2612 pub fn isf20(&self) -> ISF20_R {
2613 ISF20_R::new(((self.bits >> 20) & 0x01) != 0)
2614 }
2615 #[doc = "Bit 21 - Interrupt Status Flag"]
2616 #[inline(always)]
2617 pub fn isf21(&self) -> ISF21_R {
2618 ISF21_R::new(((self.bits >> 21) & 0x01) != 0)
2619 }
2620 #[doc = "Bit 22 - Interrupt Status Flag"]
2621 #[inline(always)]
2622 pub fn isf22(&self) -> ISF22_R {
2623 ISF22_R::new(((self.bits >> 22) & 0x01) != 0)
2624 }
2625 #[doc = "Bit 23 - Interrupt Status Flag"]
2626 #[inline(always)]
2627 pub fn isf23(&self) -> ISF23_R {
2628 ISF23_R::new(((self.bits >> 23) & 0x01) != 0)
2629 }
2630 #[doc = "Bit 24 - Interrupt Status Flag"]
2631 #[inline(always)]
2632 pub fn isf24(&self) -> ISF24_R {
2633 ISF24_R::new(((self.bits >> 24) & 0x01) != 0)
2634 }
2635 #[doc = "Bit 25 - Interrupt Status Flag"]
2636 #[inline(always)]
2637 pub fn isf25(&self) -> ISF25_R {
2638 ISF25_R::new(((self.bits >> 25) & 0x01) != 0)
2639 }
2640 #[doc = "Bit 26 - Interrupt Status Flag"]
2641 #[inline(always)]
2642 pub fn isf26(&self) -> ISF26_R {
2643 ISF26_R::new(((self.bits >> 26) & 0x01) != 0)
2644 }
2645 #[doc = "Bit 27 - Interrupt Status Flag"]
2646 #[inline(always)]
2647 pub fn isf27(&self) -> ISF27_R {
2648 ISF27_R::new(((self.bits >> 27) & 0x01) != 0)
2649 }
2650 #[doc = "Bit 28 - Interrupt Status Flag"]
2651 #[inline(always)]
2652 pub fn isf28(&self) -> ISF28_R {
2653 ISF28_R::new(((self.bits >> 28) & 0x01) != 0)
2654 }
2655 #[doc = "Bit 29 - Interrupt Status Flag"]
2656 #[inline(always)]
2657 pub fn isf29(&self) -> ISF29_R {
2658 ISF29_R::new(((self.bits >> 29) & 0x01) != 0)
2659 }
2660 #[doc = "Bit 30 - Interrupt Status Flag"]
2661 #[inline(always)]
2662 pub fn isf30(&self) -> ISF30_R {
2663 ISF30_R::new(((self.bits >> 30) & 0x01) != 0)
2664 }
2665 #[doc = "Bit 31 - Interrupt Status Flag"]
2666 #[inline(always)]
2667 pub fn isf31(&self) -> ISF31_R {
2668 ISF31_R::new(((self.bits >> 31) & 0x01) != 0)
2669 }
2670}
2671impl W {
2672 #[doc = "Bit 0 - Interrupt Status Flag"]
2673 #[inline(always)]
2674 pub fn isf0(&mut self) -> ISF0_W {
2675 ISF0_W { w: self }
2676 }
2677 #[doc = "Bit 1 - Interrupt Status Flag"]
2678 #[inline(always)]
2679 pub fn isf1(&mut self) -> ISF1_W {
2680 ISF1_W { w: self }
2681 }
2682 #[doc = "Bit 2 - Interrupt Status Flag"]
2683 #[inline(always)]
2684 pub fn isf2(&mut self) -> ISF2_W {
2685 ISF2_W { w: self }
2686 }
2687 #[doc = "Bit 3 - Interrupt Status Flag"]
2688 #[inline(always)]
2689 pub fn isf3(&mut self) -> ISF3_W {
2690 ISF3_W { w: self }
2691 }
2692 #[doc = "Bit 4 - Interrupt Status Flag"]
2693 #[inline(always)]
2694 pub fn isf4(&mut self) -> ISF4_W {
2695 ISF4_W { w: self }
2696 }
2697 #[doc = "Bit 5 - Interrupt Status Flag"]
2698 #[inline(always)]
2699 pub fn isf5(&mut self) -> ISF5_W {
2700 ISF5_W { w: self }
2701 }
2702 #[doc = "Bit 6 - Interrupt Status Flag"]
2703 #[inline(always)]
2704 pub fn isf6(&mut self) -> ISF6_W {
2705 ISF6_W { w: self }
2706 }
2707 #[doc = "Bit 7 - Interrupt Status Flag"]
2708 #[inline(always)]
2709 pub fn isf7(&mut self) -> ISF7_W {
2710 ISF7_W { w: self }
2711 }
2712 #[doc = "Bit 8 - Interrupt Status Flag"]
2713 #[inline(always)]
2714 pub fn isf8(&mut self) -> ISF8_W {
2715 ISF8_W { w: self }
2716 }
2717 #[doc = "Bit 9 - Interrupt Status Flag"]
2718 #[inline(always)]
2719 pub fn isf9(&mut self) -> ISF9_W {
2720 ISF9_W { w: self }
2721 }
2722 #[doc = "Bit 10 - Interrupt Status Flag"]
2723 #[inline(always)]
2724 pub fn isf10(&mut self) -> ISF10_W {
2725 ISF10_W { w: self }
2726 }
2727 #[doc = "Bit 11 - Interrupt Status Flag"]
2728 #[inline(always)]
2729 pub fn isf11(&mut self) -> ISF11_W {
2730 ISF11_W { w: self }
2731 }
2732 #[doc = "Bit 12 - Interrupt Status Flag"]
2733 #[inline(always)]
2734 pub fn isf12(&mut self) -> ISF12_W {
2735 ISF12_W { w: self }
2736 }
2737 #[doc = "Bit 13 - Interrupt Status Flag"]
2738 #[inline(always)]
2739 pub fn isf13(&mut self) -> ISF13_W {
2740 ISF13_W { w: self }
2741 }
2742 #[doc = "Bit 14 - Interrupt Status Flag"]
2743 #[inline(always)]
2744 pub fn isf14(&mut self) -> ISF14_W {
2745 ISF14_W { w: self }
2746 }
2747 #[doc = "Bit 15 - Interrupt Status Flag"]
2748 #[inline(always)]
2749 pub fn isf15(&mut self) -> ISF15_W {
2750 ISF15_W { w: self }
2751 }
2752 #[doc = "Bit 16 - Interrupt Status Flag"]
2753 #[inline(always)]
2754 pub fn isf16(&mut self) -> ISF16_W {
2755 ISF16_W { w: self }
2756 }
2757 #[doc = "Bit 17 - Interrupt Status Flag"]
2758 #[inline(always)]
2759 pub fn isf17(&mut self) -> ISF17_W {
2760 ISF17_W { w: self }
2761 }
2762 #[doc = "Bit 18 - Interrupt Status Flag"]
2763 #[inline(always)]
2764 pub fn isf18(&mut self) -> ISF18_W {
2765 ISF18_W { w: self }
2766 }
2767 #[doc = "Bit 19 - Interrupt Status Flag"]
2768 #[inline(always)]
2769 pub fn isf19(&mut self) -> ISF19_W {
2770 ISF19_W { w: self }
2771 }
2772 #[doc = "Bit 20 - Interrupt Status Flag"]
2773 #[inline(always)]
2774 pub fn isf20(&mut self) -> ISF20_W {
2775 ISF20_W { w: self }
2776 }
2777 #[doc = "Bit 21 - Interrupt Status Flag"]
2778 #[inline(always)]
2779 pub fn isf21(&mut self) -> ISF21_W {
2780 ISF21_W { w: self }
2781 }
2782 #[doc = "Bit 22 - Interrupt Status Flag"]
2783 #[inline(always)]
2784 pub fn isf22(&mut self) -> ISF22_W {
2785 ISF22_W { w: self }
2786 }
2787 #[doc = "Bit 23 - Interrupt Status Flag"]
2788 #[inline(always)]
2789 pub fn isf23(&mut self) -> ISF23_W {
2790 ISF23_W { w: self }
2791 }
2792 #[doc = "Bit 24 - Interrupt Status Flag"]
2793 #[inline(always)]
2794 pub fn isf24(&mut self) -> ISF24_W {
2795 ISF24_W { w: self }
2796 }
2797 #[doc = "Bit 25 - Interrupt Status Flag"]
2798 #[inline(always)]
2799 pub fn isf25(&mut self) -> ISF25_W {
2800 ISF25_W { w: self }
2801 }
2802 #[doc = "Bit 26 - Interrupt Status Flag"]
2803 #[inline(always)]
2804 pub fn isf26(&mut self) -> ISF26_W {
2805 ISF26_W { w: self }
2806 }
2807 #[doc = "Bit 27 - Interrupt Status Flag"]
2808 #[inline(always)]
2809 pub fn isf27(&mut self) -> ISF27_W {
2810 ISF27_W { w: self }
2811 }
2812 #[doc = "Bit 28 - Interrupt Status Flag"]
2813 #[inline(always)]
2814 pub fn isf28(&mut self) -> ISF28_W {
2815 ISF28_W { w: self }
2816 }
2817 #[doc = "Bit 29 - Interrupt Status Flag"]
2818 #[inline(always)]
2819 pub fn isf29(&mut self) -> ISF29_W {
2820 ISF29_W { w: self }
2821 }
2822 #[doc = "Bit 30 - Interrupt Status Flag"]
2823 #[inline(always)]
2824 pub fn isf30(&mut self) -> ISF30_W {
2825 ISF30_W { w: self }
2826 }
2827 #[doc = "Bit 31 - Interrupt Status Flag"]
2828 #[inline(always)]
2829 pub fn isf31(&mut self) -> ISF31_W {
2830 ISF31_W { w: self }
2831 }
2832}