1#[doc = "Reader of register DACCR"]
2pub type R = crate::R<u8, super::DACCR>;
3#[doc = "Writer for register DACCR"]
4pub type W = crate::W<u8, super::DACCR>;
5#[doc = "Register DACCR `reset()`'s with value 0"]
6impl crate::ResetValue for super::DACCR {
7 type Type = u8;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `VOSEL`"]
14pub type VOSEL_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `VOSEL`"]
16pub struct VOSEL_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> VOSEL_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u8) -> &'a mut W {
23 self.w.bits = (self.w.bits & !0x3f) | ((value as u8) & 0x3f);
24 self.w
25 }
26}
27#[doc = "Supply Voltage Reference Source Select\n\nValue on reset: 0"]
28#[derive(Clone, Copy, Debug, PartialEq)]
29pub enum VRSEL_A {
30 #[doc = "0: Vin1 is selected as resistor ladder network supply reference."]
31 _0,
32 #[doc = "1: Vin2 is selected as resistor ladder network supply reference."]
33 _1,
34}
35impl From<VRSEL_A> for bool {
36 #[inline(always)]
37 fn from(variant: VRSEL_A) -> Self {
38 match variant {
39 VRSEL_A::_0 => false,
40 VRSEL_A::_1 => true,
41 }
42 }
43}
44#[doc = "Reader of field `VRSEL`"]
45pub type VRSEL_R = crate::R<bool, VRSEL_A>;
46impl VRSEL_R {
47 #[doc = r"Get enumerated values variant"]
48 #[inline(always)]
49 pub fn variant(&self) -> VRSEL_A {
50 match self.bits {
51 false => VRSEL_A::_0,
52 true => VRSEL_A::_1,
53 }
54 }
55 #[doc = "Checks if the value of the field is `_0`"]
56 #[inline(always)]
57 pub fn is_0(&self) -> bool {
58 *self == VRSEL_A::_0
59 }
60 #[doc = "Checks if the value of the field is `_1`"]
61 #[inline(always)]
62 pub fn is_1(&self) -> bool {
63 *self == VRSEL_A::_1
64 }
65}
66#[doc = "Write proxy for field `VRSEL`"]
67pub struct VRSEL_W<'a> {
68 w: &'a mut W,
69}
70impl<'a> VRSEL_W<'a> {
71 #[doc = r"Writes `variant` to the field"]
72 #[inline(always)]
73 pub fn variant(self, variant: VRSEL_A) -> &'a mut W {
74 {
75 self.bit(variant.into())
76 }
77 }
78 #[doc = "Vin1 is selected as resistor ladder network supply reference."]
79 #[inline(always)]
80 pub fn _0(self) -> &'a mut W {
81 self.variant(VRSEL_A::_0)
82 }
83 #[doc = "Vin2 is selected as resistor ladder network supply reference."]
84 #[inline(always)]
85 pub fn _1(self) -> &'a mut W {
86 self.variant(VRSEL_A::_1)
87 }
88 #[doc = r"Sets the field bit"]
89 #[inline(always)]
90 pub fn set_bit(self) -> &'a mut W {
91 self.bit(true)
92 }
93 #[doc = r"Clears the field bit"]
94 #[inline(always)]
95 pub fn clear_bit(self) -> &'a mut W {
96 self.bit(false)
97 }
98 #[doc = r"Writes raw bits to the field"]
99 #[inline(always)]
100 pub fn bit(self, value: bool) -> &'a mut W {
101 self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u8) & 0x01) << 6);
102 self.w
103 }
104}
105#[doc = "DAC Enable\n\nValue on reset: 0"]
106#[derive(Clone, Copy, Debug, PartialEq)]
107pub enum DACEN_A {
108 #[doc = "0: DAC is disabled."]
109 _0,
110 #[doc = "1: DAC is enabled."]
111 _1,
112}
113impl From<DACEN_A> for bool {
114 #[inline(always)]
115 fn from(variant: DACEN_A) -> Self {
116 match variant {
117 DACEN_A::_0 => false,
118 DACEN_A::_1 => true,
119 }
120 }
121}
122#[doc = "Reader of field `DACEN`"]
123pub type DACEN_R = crate::R<bool, DACEN_A>;
124impl DACEN_R {
125 #[doc = r"Get enumerated values variant"]
126 #[inline(always)]
127 pub fn variant(&self) -> DACEN_A {
128 match self.bits {
129 false => DACEN_A::_0,
130 true => DACEN_A::_1,
131 }
132 }
133 #[doc = "Checks if the value of the field is `_0`"]
134 #[inline(always)]
135 pub fn is_0(&self) -> bool {
136 *self == DACEN_A::_0
137 }
138 #[doc = "Checks if the value of the field is `_1`"]
139 #[inline(always)]
140 pub fn is_1(&self) -> bool {
141 *self == DACEN_A::_1
142 }
143}
144#[doc = "Write proxy for field `DACEN`"]
145pub struct DACEN_W<'a> {
146 w: &'a mut W,
147}
148impl<'a> DACEN_W<'a> {
149 #[doc = r"Writes `variant` to the field"]
150 #[inline(always)]
151 pub fn variant(self, variant: DACEN_A) -> &'a mut W {
152 {
153 self.bit(variant.into())
154 }
155 }
156 #[doc = "DAC is disabled."]
157 #[inline(always)]
158 pub fn _0(self) -> &'a mut W {
159 self.variant(DACEN_A::_0)
160 }
161 #[doc = "DAC is enabled."]
162 #[inline(always)]
163 pub fn _1(self) -> &'a mut W {
164 self.variant(DACEN_A::_1)
165 }
166 #[doc = r"Sets the field bit"]
167 #[inline(always)]
168 pub fn set_bit(self) -> &'a mut W {
169 self.bit(true)
170 }
171 #[doc = r"Clears the field bit"]
172 #[inline(always)]
173 pub fn clear_bit(self) -> &'a mut W {
174 self.bit(false)
175 }
176 #[doc = r"Writes raw bits to the field"]
177 #[inline(always)]
178 pub fn bit(self, value: bool) -> &'a mut W {
179 self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u8) & 0x01) << 7);
180 self.w
181 }
182}
183impl R {
184 #[doc = "Bits 0:5 - DAC Output Voltage Select"]
185 #[inline(always)]
186 pub fn vosel(&self) -> VOSEL_R {
187 VOSEL_R::new((self.bits & 0x3f) as u8)
188 }
189 #[doc = "Bit 6 - Supply Voltage Reference Source Select"]
190 #[inline(always)]
191 pub fn vrsel(&self) -> VRSEL_R {
192 VRSEL_R::new(((self.bits >> 6) & 0x01) != 0)
193 }
194 #[doc = "Bit 7 - DAC Enable"]
195 #[inline(always)]
196 pub fn dacen(&self) -> DACEN_R {
197 DACEN_R::new(((self.bits >> 7) & 0x01) != 0)
198 }
199}
200impl W {
201 #[doc = "Bits 0:5 - DAC Output Voltage Select"]
202 #[inline(always)]
203 pub fn vosel(&mut self) -> VOSEL_W {
204 VOSEL_W { w: self }
205 }
206 #[doc = "Bit 6 - Supply Voltage Reference Source Select"]
207 #[inline(always)]
208 pub fn vrsel(&mut self) -> VRSEL_W {
209 VRSEL_W { w: self }
210 }
211 #[doc = "Bit 7 - DAC Enable"]
212 #[inline(always)]
213 pub fn dacen(&mut self) -> DACEN_W {
214 DACEN_W { w: self }
215 }
216}