1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u8,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u8,
8}
9impl super::PMPROT {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `AVLLS`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum AVLLSR {
48 #[doc = "Any VLLSx mode is not allowed"]
49 _0,
50 #[doc = "Any VLLSx mode is allowed"]
51 _1,
52}
53impl AVLLSR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 AVLLSR::_0 => false,
69 AVLLSR::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> AVLLSR {
76 match value {
77 false => AVLLSR::_0,
78 true => AVLLSR::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == AVLLSR::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == AVLLSR::_1
90 }
91}
92#[doc = "Possible values of the field `ALLS`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum ALLSR {
95 #[doc = "LLS is not allowed"]
96 _0,
97 #[doc = "LLS is allowed"]
98 _1,
99}
100impl ALLSR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 ALLSR::_0 => false,
116 ALLSR::_1 => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> ALLSR {
123 match value {
124 false => ALLSR::_0,
125 true => ALLSR::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline]
130 pub fn is_0(&self) -> bool {
131 *self == ALLSR::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline]
135 pub fn is_1(&self) -> bool {
136 *self == ALLSR::_1
137 }
138}
139#[doc = "Possible values of the field `AVLP`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum AVLPR {
142 #[doc = "VLPR, VLPW and VLPS are not allowed"]
143 _0,
144 #[doc = "VLPR, VLPW and VLPS are allowed"]
145 _1,
146}
147impl AVLPR {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 AVLPR::_0 => false,
163 AVLPR::_1 => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> AVLPR {
170 match value {
171 false => AVLPR::_0,
172 true => AVLPR::_1,
173 }
174 }
175 #[doc = "Checks if the value of the field is `_0`"]
176 #[inline]
177 pub fn is_0(&self) -> bool {
178 *self == AVLPR::_0
179 }
180 #[doc = "Checks if the value of the field is `_1`"]
181 #[inline]
182 pub fn is_1(&self) -> bool {
183 *self == AVLPR::_1
184 }
185}
186#[doc = "Values that can be written to the field `AVLLS`"]
187pub enum AVLLSW {
188 #[doc = "Any VLLSx mode is not allowed"]
189 _0,
190 #[doc = "Any VLLSx mode is allowed"]
191 _1,
192}
193impl AVLLSW {
194 #[allow(missing_docs)]
195 #[doc(hidden)]
196 #[inline]
197 pub fn _bits(&self) -> bool {
198 match *self {
199 AVLLSW::_0 => false,
200 AVLLSW::_1 => true,
201 }
202 }
203}
204#[doc = r" Proxy"]
205pub struct _AVLLSW<'a> {
206 w: &'a mut W,
207}
208impl<'a> _AVLLSW<'a> {
209 #[doc = r" Writes `variant` to the field"]
210 #[inline]
211 pub fn variant(self, variant: AVLLSW) -> &'a mut W {
212 {
213 self.bit(variant._bits())
214 }
215 }
216 #[doc = "Any VLLSx mode is not allowed"]
217 #[inline]
218 pub fn _0(self) -> &'a mut W {
219 self.variant(AVLLSW::_0)
220 }
221 #[doc = "Any VLLSx mode is allowed"]
222 #[inline]
223 pub fn _1(self) -> &'a mut W {
224 self.variant(AVLLSW::_1)
225 }
226 #[doc = r" Sets the field bit"]
227 pub fn set_bit(self) -> &'a mut W {
228 self.bit(true)
229 }
230 #[doc = r" Clears the field bit"]
231 pub fn clear_bit(self) -> &'a mut W {
232 self.bit(false)
233 }
234 #[doc = r" Writes raw bits to the field"]
235 #[inline]
236 pub fn bit(self, value: bool) -> &'a mut W {
237 const MASK: bool = true;
238 const OFFSET: u8 = 1;
239 self.w.bits &= !((MASK as u8) << OFFSET);
240 self.w.bits |= ((value & MASK) as u8) << OFFSET;
241 self.w
242 }
243}
244#[doc = "Values that can be written to the field `ALLS`"]
245pub enum ALLSW {
246 #[doc = "LLS is not allowed"]
247 _0,
248 #[doc = "LLS is allowed"]
249 _1,
250}
251impl ALLSW {
252 #[allow(missing_docs)]
253 #[doc(hidden)]
254 #[inline]
255 pub fn _bits(&self) -> bool {
256 match *self {
257 ALLSW::_0 => false,
258 ALLSW::_1 => true,
259 }
260 }
261}
262#[doc = r" Proxy"]
263pub struct _ALLSW<'a> {
264 w: &'a mut W,
265}
266impl<'a> _ALLSW<'a> {
267 #[doc = r" Writes `variant` to the field"]
268 #[inline]
269 pub fn variant(self, variant: ALLSW) -> &'a mut W {
270 {
271 self.bit(variant._bits())
272 }
273 }
274 #[doc = "LLS is not allowed"]
275 #[inline]
276 pub fn _0(self) -> &'a mut W {
277 self.variant(ALLSW::_0)
278 }
279 #[doc = "LLS is allowed"]
280 #[inline]
281 pub fn _1(self) -> &'a mut W {
282 self.variant(ALLSW::_1)
283 }
284 #[doc = r" Sets the field bit"]
285 pub fn set_bit(self) -> &'a mut W {
286 self.bit(true)
287 }
288 #[doc = r" Clears the field bit"]
289 pub fn clear_bit(self) -> &'a mut W {
290 self.bit(false)
291 }
292 #[doc = r" Writes raw bits to the field"]
293 #[inline]
294 pub fn bit(self, value: bool) -> &'a mut W {
295 const MASK: bool = true;
296 const OFFSET: u8 = 3;
297 self.w.bits &= !((MASK as u8) << OFFSET);
298 self.w.bits |= ((value & MASK) as u8) << OFFSET;
299 self.w
300 }
301}
302#[doc = "Values that can be written to the field `AVLP`"]
303pub enum AVLPW {
304 #[doc = "VLPR, VLPW and VLPS are not allowed"]
305 _0,
306 #[doc = "VLPR, VLPW and VLPS are allowed"]
307 _1,
308}
309impl AVLPW {
310 #[allow(missing_docs)]
311 #[doc(hidden)]
312 #[inline]
313 pub fn _bits(&self) -> bool {
314 match *self {
315 AVLPW::_0 => false,
316 AVLPW::_1 => true,
317 }
318 }
319}
320#[doc = r" Proxy"]
321pub struct _AVLPW<'a> {
322 w: &'a mut W,
323}
324impl<'a> _AVLPW<'a> {
325 #[doc = r" Writes `variant` to the field"]
326 #[inline]
327 pub fn variant(self, variant: AVLPW) -> &'a mut W {
328 {
329 self.bit(variant._bits())
330 }
331 }
332 #[doc = "VLPR, VLPW and VLPS are not allowed"]
333 #[inline]
334 pub fn _0(self) -> &'a mut W {
335 self.variant(AVLPW::_0)
336 }
337 #[doc = "VLPR, VLPW and VLPS are allowed"]
338 #[inline]
339 pub fn _1(self) -> &'a mut W {
340 self.variant(AVLPW::_1)
341 }
342 #[doc = r" Sets the field bit"]
343 pub fn set_bit(self) -> &'a mut W {
344 self.bit(true)
345 }
346 #[doc = r" Clears the field bit"]
347 pub fn clear_bit(self) -> &'a mut W {
348 self.bit(false)
349 }
350 #[doc = r" Writes raw bits to the field"]
351 #[inline]
352 pub fn bit(self, value: bool) -> &'a mut W {
353 const MASK: bool = true;
354 const OFFSET: u8 = 5;
355 self.w.bits &= !((MASK as u8) << OFFSET);
356 self.w.bits |= ((value & MASK) as u8) << OFFSET;
357 self.w
358 }
359}
360impl R {
361 #[doc = r" Value of the register as raw bits"]
362 #[inline]
363 pub fn bits(&self) -> u8 {
364 self.bits
365 }
366 #[doc = "Bit 1 - Allow very low leakage stop mode"]
367 #[inline]
368 pub fn avlls(&self) -> AVLLSR {
369 AVLLSR::_from({
370 const MASK: bool = true;
371 const OFFSET: u8 = 1;
372 ((self.bits >> OFFSET) & MASK as u8) != 0
373 })
374 }
375 #[doc = "Bit 3 - Allow low leakage stop mode"]
376 #[inline]
377 pub fn alls(&self) -> ALLSR {
378 ALLSR::_from({
379 const MASK: bool = true;
380 const OFFSET: u8 = 3;
381 ((self.bits >> OFFSET) & MASK as u8) != 0
382 })
383 }
384 #[doc = "Bit 5 - Allow very low power modes"]
385 #[inline]
386 pub fn avlp(&self) -> AVLPR {
387 AVLPR::_from({
388 const MASK: bool = true;
389 const OFFSET: u8 = 5;
390 ((self.bits >> OFFSET) & MASK as u8) != 0
391 })
392 }
393}
394impl W {
395 #[doc = r" Reset value of the register"]
396 #[inline]
397 pub fn reset_value() -> W {
398 W { bits: 0 }
399 }
400 #[doc = r" Writes raw bits to the register"]
401 #[inline]
402 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
403 self.bits = bits;
404 self
405 }
406 #[doc = "Bit 1 - Allow very low leakage stop mode"]
407 #[inline]
408 pub fn avlls(&mut self) -> _AVLLSW {
409 _AVLLSW { w: self }
410 }
411 #[doc = "Bit 3 - Allow low leakage stop mode"]
412 #[inline]
413 pub fn alls(&mut self) -> _ALLSW {
414 _ALLSW { w: self }
415 }
416 #[doc = "Bit 5 - Allow very low power modes"]
417 #[inline]
418 pub fn avlp(&mut self) -> _AVLPW {
419 _AVLPW { w: self }
420 }
421}