1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::LR {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `TCL`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum TCLR {
48 #[doc = "Time compensation register is locked and writes are ignored."]
49 _0,
50 #[doc = "Time compensation register is not locked and writes complete as normal."]
51 _1,
52}
53impl TCLR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 TCLR::_0 => false,
69 TCLR::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> TCLR {
76 match value {
77 false => TCLR::_0,
78 true => TCLR::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == TCLR::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == TCLR::_1
90 }
91}
92#[doc = "Possible values of the field `CRL`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum CRLR {
95 #[doc = "Control register is locked and writes are ignored."]
96 _0,
97 #[doc = "Control register is not locked and writes complete as normal."]
98 _1,
99}
100impl CRLR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 CRLR::_0 => false,
116 CRLR::_1 => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> CRLR {
123 match value {
124 false => CRLR::_0,
125 true => CRLR::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline]
130 pub fn is_0(&self) -> bool {
131 *self == CRLR::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline]
135 pub fn is_1(&self) -> bool {
136 *self == CRLR::_1
137 }
138}
139#[doc = "Possible values of the field `SRL`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum SRLR {
142 #[doc = "Status register is locked and writes are ignored."]
143 _0,
144 #[doc = "Status register is not locked and writes complete as normal."]
145 _1,
146}
147impl SRLR {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 SRLR::_0 => false,
163 SRLR::_1 => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> SRLR {
170 match value {
171 false => SRLR::_0,
172 true => SRLR::_1,
173 }
174 }
175 #[doc = "Checks if the value of the field is `_0`"]
176 #[inline]
177 pub fn is_0(&self) -> bool {
178 *self == SRLR::_0
179 }
180 #[doc = "Checks if the value of the field is `_1`"]
181 #[inline]
182 pub fn is_1(&self) -> bool {
183 *self == SRLR::_1
184 }
185}
186#[doc = "Possible values of the field `LRL`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum LRLR {
189 #[doc = "Lock register is locked and writes are ignored."]
190 _0,
191 #[doc = "Lock register is not locked and writes complete as normal."]
192 _1,
193}
194impl LRLR {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 LRLR::_0 => false,
210 LRLR::_1 => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> LRLR {
217 match value {
218 false => LRLR::_0,
219 true => LRLR::_1,
220 }
221 }
222 #[doc = "Checks if the value of the field is `_0`"]
223 #[inline]
224 pub fn is_0(&self) -> bool {
225 *self == LRLR::_0
226 }
227 #[doc = "Checks if the value of the field is `_1`"]
228 #[inline]
229 pub fn is_1(&self) -> bool {
230 *self == LRLR::_1
231 }
232}
233#[doc = "Values that can be written to the field `TCL`"]
234pub enum TCLW {
235 #[doc = "Time compensation register is locked and writes are ignored."]
236 _0,
237 #[doc = "Time compensation register is not locked and writes complete as normal."]
238 _1,
239}
240impl TCLW {
241 #[allow(missing_docs)]
242 #[doc(hidden)]
243 #[inline]
244 pub fn _bits(&self) -> bool {
245 match *self {
246 TCLW::_0 => false,
247 TCLW::_1 => true,
248 }
249 }
250}
251#[doc = r" Proxy"]
252pub struct _TCLW<'a> {
253 w: &'a mut W,
254}
255impl<'a> _TCLW<'a> {
256 #[doc = r" Writes `variant` to the field"]
257 #[inline]
258 pub fn variant(self, variant: TCLW) -> &'a mut W {
259 {
260 self.bit(variant._bits())
261 }
262 }
263 #[doc = "Time compensation register is locked and writes are ignored."]
264 #[inline]
265 pub fn _0(self) -> &'a mut W {
266 self.variant(TCLW::_0)
267 }
268 #[doc = "Time compensation register is not locked and writes complete as normal."]
269 #[inline]
270 pub fn _1(self) -> &'a mut W {
271 self.variant(TCLW::_1)
272 }
273 #[doc = r" Sets the field bit"]
274 pub fn set_bit(self) -> &'a mut W {
275 self.bit(true)
276 }
277 #[doc = r" Clears the field bit"]
278 pub fn clear_bit(self) -> &'a mut W {
279 self.bit(false)
280 }
281 #[doc = r" Writes raw bits to the field"]
282 #[inline]
283 pub fn bit(self, value: bool) -> &'a mut W {
284 const MASK: bool = true;
285 const OFFSET: u8 = 3;
286 self.w.bits &= !((MASK as u32) << OFFSET);
287 self.w.bits |= ((value & MASK) as u32) << OFFSET;
288 self.w
289 }
290}
291#[doc = "Values that can be written to the field `CRL`"]
292pub enum CRLW {
293 #[doc = "Control register is locked and writes are ignored."]
294 _0,
295 #[doc = "Control register is not locked and writes complete as normal."]
296 _1,
297}
298impl CRLW {
299 #[allow(missing_docs)]
300 #[doc(hidden)]
301 #[inline]
302 pub fn _bits(&self) -> bool {
303 match *self {
304 CRLW::_0 => false,
305 CRLW::_1 => true,
306 }
307 }
308}
309#[doc = r" Proxy"]
310pub struct _CRLW<'a> {
311 w: &'a mut W,
312}
313impl<'a> _CRLW<'a> {
314 #[doc = r" Writes `variant` to the field"]
315 #[inline]
316 pub fn variant(self, variant: CRLW) -> &'a mut W {
317 {
318 self.bit(variant._bits())
319 }
320 }
321 #[doc = "Control register is locked and writes are ignored."]
322 #[inline]
323 pub fn _0(self) -> &'a mut W {
324 self.variant(CRLW::_0)
325 }
326 #[doc = "Control register is not locked and writes complete as normal."]
327 #[inline]
328 pub fn _1(self) -> &'a mut W {
329 self.variant(CRLW::_1)
330 }
331 #[doc = r" Sets the field bit"]
332 pub fn set_bit(self) -> &'a mut W {
333 self.bit(true)
334 }
335 #[doc = r" Clears the field bit"]
336 pub fn clear_bit(self) -> &'a mut W {
337 self.bit(false)
338 }
339 #[doc = r" Writes raw bits to the field"]
340 #[inline]
341 pub fn bit(self, value: bool) -> &'a mut W {
342 const MASK: bool = true;
343 const OFFSET: u8 = 4;
344 self.w.bits &= !((MASK as u32) << OFFSET);
345 self.w.bits |= ((value & MASK) as u32) << OFFSET;
346 self.w
347 }
348}
349#[doc = "Values that can be written to the field `SRL`"]
350pub enum SRLW {
351 #[doc = "Status register is locked and writes are ignored."]
352 _0,
353 #[doc = "Status register is not locked and writes complete as normal."]
354 _1,
355}
356impl SRLW {
357 #[allow(missing_docs)]
358 #[doc(hidden)]
359 #[inline]
360 pub fn _bits(&self) -> bool {
361 match *self {
362 SRLW::_0 => false,
363 SRLW::_1 => true,
364 }
365 }
366}
367#[doc = r" Proxy"]
368pub struct _SRLW<'a> {
369 w: &'a mut W,
370}
371impl<'a> _SRLW<'a> {
372 #[doc = r" Writes `variant` to the field"]
373 #[inline]
374 pub fn variant(self, variant: SRLW) -> &'a mut W {
375 {
376 self.bit(variant._bits())
377 }
378 }
379 #[doc = "Status register is locked and writes are ignored."]
380 #[inline]
381 pub fn _0(self) -> &'a mut W {
382 self.variant(SRLW::_0)
383 }
384 #[doc = "Status register is not locked and writes complete as normal."]
385 #[inline]
386 pub fn _1(self) -> &'a mut W {
387 self.variant(SRLW::_1)
388 }
389 #[doc = r" Sets the field bit"]
390 pub fn set_bit(self) -> &'a mut W {
391 self.bit(true)
392 }
393 #[doc = r" Clears the field bit"]
394 pub fn clear_bit(self) -> &'a mut W {
395 self.bit(false)
396 }
397 #[doc = r" Writes raw bits to the field"]
398 #[inline]
399 pub fn bit(self, value: bool) -> &'a mut W {
400 const MASK: bool = true;
401 const OFFSET: u8 = 5;
402 self.w.bits &= !((MASK as u32) << OFFSET);
403 self.w.bits |= ((value & MASK) as u32) << OFFSET;
404 self.w
405 }
406}
407#[doc = "Values that can be written to the field `LRL`"]
408pub enum LRLW {
409 #[doc = "Lock register is locked and writes are ignored."]
410 _0,
411 #[doc = "Lock register is not locked and writes complete as normal."]
412 _1,
413}
414impl LRLW {
415 #[allow(missing_docs)]
416 #[doc(hidden)]
417 #[inline]
418 pub fn _bits(&self) -> bool {
419 match *self {
420 LRLW::_0 => false,
421 LRLW::_1 => true,
422 }
423 }
424}
425#[doc = r" Proxy"]
426pub struct _LRLW<'a> {
427 w: &'a mut W,
428}
429impl<'a> _LRLW<'a> {
430 #[doc = r" Writes `variant` to the field"]
431 #[inline]
432 pub fn variant(self, variant: LRLW) -> &'a mut W {
433 {
434 self.bit(variant._bits())
435 }
436 }
437 #[doc = "Lock register is locked and writes are ignored."]
438 #[inline]
439 pub fn _0(self) -> &'a mut W {
440 self.variant(LRLW::_0)
441 }
442 #[doc = "Lock register is not locked and writes complete as normal."]
443 #[inline]
444 pub fn _1(self) -> &'a mut W {
445 self.variant(LRLW::_1)
446 }
447 #[doc = r" Sets the field bit"]
448 pub fn set_bit(self) -> &'a mut W {
449 self.bit(true)
450 }
451 #[doc = r" Clears the field bit"]
452 pub fn clear_bit(self) -> &'a mut W {
453 self.bit(false)
454 }
455 #[doc = r" Writes raw bits to the field"]
456 #[inline]
457 pub fn bit(self, value: bool) -> &'a mut W {
458 const MASK: bool = true;
459 const OFFSET: u8 = 6;
460 self.w.bits &= !((MASK as u32) << OFFSET);
461 self.w.bits |= ((value & MASK) as u32) << OFFSET;
462 self.w
463 }
464}
465impl R {
466 #[doc = r" Value of the register as raw bits"]
467 #[inline]
468 pub fn bits(&self) -> u32 {
469 self.bits
470 }
471 #[doc = "Bit 3 - Time Compensation Lock"]
472 #[inline]
473 pub fn tcl(&self) -> TCLR {
474 TCLR::_from({
475 const MASK: bool = true;
476 const OFFSET: u8 = 3;
477 ((self.bits >> OFFSET) & MASK as u32) != 0
478 })
479 }
480 #[doc = "Bit 4 - Control Register Lock"]
481 #[inline]
482 pub fn crl(&self) -> CRLR {
483 CRLR::_from({
484 const MASK: bool = true;
485 const OFFSET: u8 = 4;
486 ((self.bits >> OFFSET) & MASK as u32) != 0
487 })
488 }
489 #[doc = "Bit 5 - Status Register Lock"]
490 #[inline]
491 pub fn srl(&self) -> SRLR {
492 SRLR::_from({
493 const MASK: bool = true;
494 const OFFSET: u8 = 5;
495 ((self.bits >> OFFSET) & MASK as u32) != 0
496 })
497 }
498 #[doc = "Bit 6 - Lock Register Lock"]
499 #[inline]
500 pub fn lrl(&self) -> LRLR {
501 LRLR::_from({
502 const MASK: bool = true;
503 const OFFSET: u8 = 6;
504 ((self.bits >> OFFSET) & MASK as u32) != 0
505 })
506 }
507}
508impl W {
509 #[doc = r" Reset value of the register"]
510 #[inline]
511 pub fn reset_value() -> W {
512 W { bits: 255 }
513 }
514 #[doc = r" Writes raw bits to the register"]
515 #[inline]
516 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
517 self.bits = bits;
518 self
519 }
520 #[doc = "Bit 3 - Time Compensation Lock"]
521 #[inline]
522 pub fn tcl(&mut self) -> _TCLW {
523 _TCLW { w: self }
524 }
525 #[doc = "Bit 4 - Control Register Lock"]
526 #[inline]
527 pub fn crl(&mut self) -> _CRLW {
528 _CRLW { w: self }
529 }
530 #[doc = "Bit 5 - Status Register Lock"]
531 #[inline]
532 pub fn srl(&mut self) -> _SRLW {
533 _SRLW { w: self }
534 }
535 #[doc = "Bit 6 - Lock Register Lock"]
536 #[inline]
537 pub fn lrl(&mut self) -> _LRLW {
538 _LRLW { w: self }
539 }
540}