1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::SYNCONF {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `HWTRIGMODE`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum HWTRIGMODER {
48 #[doc = "FTM clears the TRIGj bit when the hardware trigger j is detected."]
49 _0,
50 #[doc = "FTM does not clear the TRIGj bit when the hardware trigger j is detected."]
51 _1,
52}
53impl HWTRIGMODER {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 HWTRIGMODER::_0 => false,
69 HWTRIGMODER::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> HWTRIGMODER {
76 match value {
77 false => HWTRIGMODER::_0,
78 true => HWTRIGMODER::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == HWTRIGMODER::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == HWTRIGMODER::_1
90 }
91}
92#[doc = "Possible values of the field `CNTINC`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum CNTINCR {
95 #[doc = "CNTIN register is updated with its buffer value at all rising edges of system clock."]
96 _0,
97 #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."]
98 _1,
99}
100impl CNTINCR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 CNTINCR::_0 => false,
116 CNTINCR::_1 => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> CNTINCR {
123 match value {
124 false => CNTINCR::_0,
125 true => CNTINCR::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline]
130 pub fn is_0(&self) -> bool {
131 *self == CNTINCR::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline]
135 pub fn is_1(&self) -> bool {
136 *self == CNTINCR::_1
137 }
138}
139#[doc = "Possible values of the field `INVC`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum INVCR {
142 #[doc = "INVCTRL register is updated with its buffer value at all rising edges of system clock."]
143 _0,
144 #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."]
145 _1,
146}
147impl INVCR {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 INVCR::_0 => false,
163 INVCR::_1 => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> INVCR {
170 match value {
171 false => INVCR::_0,
172 true => INVCR::_1,
173 }
174 }
175 #[doc = "Checks if the value of the field is `_0`"]
176 #[inline]
177 pub fn is_0(&self) -> bool {
178 *self == INVCR::_0
179 }
180 #[doc = "Checks if the value of the field is `_1`"]
181 #[inline]
182 pub fn is_1(&self) -> bool {
183 *self == INVCR::_1
184 }
185}
186#[doc = "Possible values of the field `SWOC`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum SWOCR {
189 #[doc = "SWOCTRL register is updated with its buffer value at all rising edges of system clock."]
190 _0,
191 #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."]
192 _1,
193}
194impl SWOCR {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 SWOCR::_0 => false,
210 SWOCR::_1 => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> SWOCR {
217 match value {
218 false => SWOCR::_0,
219 true => SWOCR::_1,
220 }
221 }
222 #[doc = "Checks if the value of the field is `_0`"]
223 #[inline]
224 pub fn is_0(&self) -> bool {
225 *self == SWOCR::_0
226 }
227 #[doc = "Checks if the value of the field is `_1`"]
228 #[inline]
229 pub fn is_1(&self) -> bool {
230 *self == SWOCR::_1
231 }
232}
233#[doc = "Possible values of the field `SYNCMODE`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum SYNCMODER {
236 #[doc = "Legacy PWM synchronization is selected."]
237 _0,
238 #[doc = "Enhanced PWM synchronization is selected."]
239 _1,
240}
241impl SYNCMODER {
242 #[doc = r" Returns `true` if the bit is clear (0)"]
243 #[inline]
244 pub fn bit_is_clear(&self) -> bool {
245 !self.bit()
246 }
247 #[doc = r" Returns `true` if the bit is set (1)"]
248 #[inline]
249 pub fn bit_is_set(&self) -> bool {
250 self.bit()
251 }
252 #[doc = r" Value of the field as raw bits"]
253 #[inline]
254 pub fn bit(&self) -> bool {
255 match *self {
256 SYNCMODER::_0 => false,
257 SYNCMODER::_1 => true,
258 }
259 }
260 #[allow(missing_docs)]
261 #[doc(hidden)]
262 #[inline]
263 pub fn _from(value: bool) -> SYNCMODER {
264 match value {
265 false => SYNCMODER::_0,
266 true => SYNCMODER::_1,
267 }
268 }
269 #[doc = "Checks if the value of the field is `_0`"]
270 #[inline]
271 pub fn is_0(&self) -> bool {
272 *self == SYNCMODER::_0
273 }
274 #[doc = "Checks if the value of the field is `_1`"]
275 #[inline]
276 pub fn is_1(&self) -> bool {
277 *self == SYNCMODER::_1
278 }
279}
280#[doc = "Possible values of the field `SWRSTCNT`"]
281#[derive(Clone, Copy, Debug, PartialEq)]
282pub enum SWRSTCNTR {
283 #[doc = "The software trigger does not activate the FTM counter synchronization."]
284 _0,
285 #[doc = "The software trigger activates the FTM counter synchronization."]
286 _1,
287}
288impl SWRSTCNTR {
289 #[doc = r" Returns `true` if the bit is clear (0)"]
290 #[inline]
291 pub fn bit_is_clear(&self) -> bool {
292 !self.bit()
293 }
294 #[doc = r" Returns `true` if the bit is set (1)"]
295 #[inline]
296 pub fn bit_is_set(&self) -> bool {
297 self.bit()
298 }
299 #[doc = r" Value of the field as raw bits"]
300 #[inline]
301 pub fn bit(&self) -> bool {
302 match *self {
303 SWRSTCNTR::_0 => false,
304 SWRSTCNTR::_1 => true,
305 }
306 }
307 #[allow(missing_docs)]
308 #[doc(hidden)]
309 #[inline]
310 pub fn _from(value: bool) -> SWRSTCNTR {
311 match value {
312 false => SWRSTCNTR::_0,
313 true => SWRSTCNTR::_1,
314 }
315 }
316 #[doc = "Checks if the value of the field is `_0`"]
317 #[inline]
318 pub fn is_0(&self) -> bool {
319 *self == SWRSTCNTR::_0
320 }
321 #[doc = "Checks if the value of the field is `_1`"]
322 #[inline]
323 pub fn is_1(&self) -> bool {
324 *self == SWRSTCNTR::_1
325 }
326}
327#[doc = "Possible values of the field `SWWRBUF`"]
328#[derive(Clone, Copy, Debug, PartialEq)]
329pub enum SWWRBUFR {
330 #[doc = "The software trigger does not activate MOD, CNTIN, and CV registers synchronization."]
331 _0,
332 #[doc = "The software trigger activates MOD, CNTIN, and CV registers synchronization."]
333 _1,
334}
335impl SWWRBUFR {
336 #[doc = r" Returns `true` if the bit is clear (0)"]
337 #[inline]
338 pub fn bit_is_clear(&self) -> bool {
339 !self.bit()
340 }
341 #[doc = r" Returns `true` if the bit is set (1)"]
342 #[inline]
343 pub fn bit_is_set(&self) -> bool {
344 self.bit()
345 }
346 #[doc = r" Value of the field as raw bits"]
347 #[inline]
348 pub fn bit(&self) -> bool {
349 match *self {
350 SWWRBUFR::_0 => false,
351 SWWRBUFR::_1 => true,
352 }
353 }
354 #[allow(missing_docs)]
355 #[doc(hidden)]
356 #[inline]
357 pub fn _from(value: bool) -> SWWRBUFR {
358 match value {
359 false => SWWRBUFR::_0,
360 true => SWWRBUFR::_1,
361 }
362 }
363 #[doc = "Checks if the value of the field is `_0`"]
364 #[inline]
365 pub fn is_0(&self) -> bool {
366 *self == SWWRBUFR::_0
367 }
368 #[doc = "Checks if the value of the field is `_1`"]
369 #[inline]
370 pub fn is_1(&self) -> bool {
371 *self == SWWRBUFR::_1
372 }
373}
374#[doc = "Possible values of the field `SWOM`"]
375#[derive(Clone, Copy, Debug, PartialEq)]
376pub enum SWOMR {
377 #[doc = "The software trigger does not activate the OUTMASK register synchronization."]
378 _0,
379 #[doc = "The software trigger activates the OUTMASK register synchronization."]
380 _1,
381}
382impl SWOMR {
383 #[doc = r" Returns `true` if the bit is clear (0)"]
384 #[inline]
385 pub fn bit_is_clear(&self) -> bool {
386 !self.bit()
387 }
388 #[doc = r" Returns `true` if the bit is set (1)"]
389 #[inline]
390 pub fn bit_is_set(&self) -> bool {
391 self.bit()
392 }
393 #[doc = r" Value of the field as raw bits"]
394 #[inline]
395 pub fn bit(&self) -> bool {
396 match *self {
397 SWOMR::_0 => false,
398 SWOMR::_1 => true,
399 }
400 }
401 #[allow(missing_docs)]
402 #[doc(hidden)]
403 #[inline]
404 pub fn _from(value: bool) -> SWOMR {
405 match value {
406 false => SWOMR::_0,
407 true => SWOMR::_1,
408 }
409 }
410 #[doc = "Checks if the value of the field is `_0`"]
411 #[inline]
412 pub fn is_0(&self) -> bool {
413 *self == SWOMR::_0
414 }
415 #[doc = "Checks if the value of the field is `_1`"]
416 #[inline]
417 pub fn is_1(&self) -> bool {
418 *self == SWOMR::_1
419 }
420}
421#[doc = "Possible values of the field `SWINVC`"]
422#[derive(Clone, Copy, Debug, PartialEq)]
423pub enum SWINVCR {
424 #[doc = "The software trigger does not activate the INVCTRL register synchronization."]
425 _0,
426 #[doc = "The software trigger activates the INVCTRL register synchronization."]
427 _1,
428}
429impl SWINVCR {
430 #[doc = r" Returns `true` if the bit is clear (0)"]
431 #[inline]
432 pub fn bit_is_clear(&self) -> bool {
433 !self.bit()
434 }
435 #[doc = r" Returns `true` if the bit is set (1)"]
436 #[inline]
437 pub fn bit_is_set(&self) -> bool {
438 self.bit()
439 }
440 #[doc = r" Value of the field as raw bits"]
441 #[inline]
442 pub fn bit(&self) -> bool {
443 match *self {
444 SWINVCR::_0 => false,
445 SWINVCR::_1 => true,
446 }
447 }
448 #[allow(missing_docs)]
449 #[doc(hidden)]
450 #[inline]
451 pub fn _from(value: bool) -> SWINVCR {
452 match value {
453 false => SWINVCR::_0,
454 true => SWINVCR::_1,
455 }
456 }
457 #[doc = "Checks if the value of the field is `_0`"]
458 #[inline]
459 pub fn is_0(&self) -> bool {
460 *self == SWINVCR::_0
461 }
462 #[doc = "Checks if the value of the field is `_1`"]
463 #[inline]
464 pub fn is_1(&self) -> bool {
465 *self == SWINVCR::_1
466 }
467}
468#[doc = "Possible values of the field `SWSOC`"]
469#[derive(Clone, Copy, Debug, PartialEq)]
470pub enum SWSOCR {
471 #[doc = "The software trigger does not activate the SWOCTRL register synchronization."]
472 _0,
473 #[doc = "The software trigger activates the SWOCTRL register synchronization."]
474 _1,
475}
476impl SWSOCR {
477 #[doc = r" Returns `true` if the bit is clear (0)"]
478 #[inline]
479 pub fn bit_is_clear(&self) -> bool {
480 !self.bit()
481 }
482 #[doc = r" Returns `true` if the bit is set (1)"]
483 #[inline]
484 pub fn bit_is_set(&self) -> bool {
485 self.bit()
486 }
487 #[doc = r" Value of the field as raw bits"]
488 #[inline]
489 pub fn bit(&self) -> bool {
490 match *self {
491 SWSOCR::_0 => false,
492 SWSOCR::_1 => true,
493 }
494 }
495 #[allow(missing_docs)]
496 #[doc(hidden)]
497 #[inline]
498 pub fn _from(value: bool) -> SWSOCR {
499 match value {
500 false => SWSOCR::_0,
501 true => SWSOCR::_1,
502 }
503 }
504 #[doc = "Checks if the value of the field is `_0`"]
505 #[inline]
506 pub fn is_0(&self) -> bool {
507 *self == SWSOCR::_0
508 }
509 #[doc = "Checks if the value of the field is `_1`"]
510 #[inline]
511 pub fn is_1(&self) -> bool {
512 *self == SWSOCR::_1
513 }
514}
515#[doc = "Possible values of the field `HWRSTCNT`"]
516#[derive(Clone, Copy, Debug, PartialEq)]
517pub enum HWRSTCNTR {
518 #[doc = "A hardware trigger does not activate the FTM counter synchronization."]
519 _0,
520 #[doc = "A hardware trigger activates the FTM counter synchronization."]
521 _1,
522}
523impl HWRSTCNTR {
524 #[doc = r" Returns `true` if the bit is clear (0)"]
525 #[inline]
526 pub fn bit_is_clear(&self) -> bool {
527 !self.bit()
528 }
529 #[doc = r" Returns `true` if the bit is set (1)"]
530 #[inline]
531 pub fn bit_is_set(&self) -> bool {
532 self.bit()
533 }
534 #[doc = r" Value of the field as raw bits"]
535 #[inline]
536 pub fn bit(&self) -> bool {
537 match *self {
538 HWRSTCNTR::_0 => false,
539 HWRSTCNTR::_1 => true,
540 }
541 }
542 #[allow(missing_docs)]
543 #[doc(hidden)]
544 #[inline]
545 pub fn _from(value: bool) -> HWRSTCNTR {
546 match value {
547 false => HWRSTCNTR::_0,
548 true => HWRSTCNTR::_1,
549 }
550 }
551 #[doc = "Checks if the value of the field is `_0`"]
552 #[inline]
553 pub fn is_0(&self) -> bool {
554 *self == HWRSTCNTR::_0
555 }
556 #[doc = "Checks if the value of the field is `_1`"]
557 #[inline]
558 pub fn is_1(&self) -> bool {
559 *self == HWRSTCNTR::_1
560 }
561}
562#[doc = "Possible values of the field `HWWRBUF`"]
563#[derive(Clone, Copy, Debug, PartialEq)]
564pub enum HWWRBUFR {
565 #[doc = "A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization."]
566 _0,
567 #[doc = "A hardware trigger activates MOD, CNTIN, and CV registers synchronization."]
568 _1,
569}
570impl HWWRBUFR {
571 #[doc = r" Returns `true` if the bit is clear (0)"]
572 #[inline]
573 pub fn bit_is_clear(&self) -> bool {
574 !self.bit()
575 }
576 #[doc = r" Returns `true` if the bit is set (1)"]
577 #[inline]
578 pub fn bit_is_set(&self) -> bool {
579 self.bit()
580 }
581 #[doc = r" Value of the field as raw bits"]
582 #[inline]
583 pub fn bit(&self) -> bool {
584 match *self {
585 HWWRBUFR::_0 => false,
586 HWWRBUFR::_1 => true,
587 }
588 }
589 #[allow(missing_docs)]
590 #[doc(hidden)]
591 #[inline]
592 pub fn _from(value: bool) -> HWWRBUFR {
593 match value {
594 false => HWWRBUFR::_0,
595 true => HWWRBUFR::_1,
596 }
597 }
598 #[doc = "Checks if the value of the field is `_0`"]
599 #[inline]
600 pub fn is_0(&self) -> bool {
601 *self == HWWRBUFR::_0
602 }
603 #[doc = "Checks if the value of the field is `_1`"]
604 #[inline]
605 pub fn is_1(&self) -> bool {
606 *self == HWWRBUFR::_1
607 }
608}
609#[doc = "Possible values of the field `HWOM`"]
610#[derive(Clone, Copy, Debug, PartialEq)]
611pub enum HWOMR {
612 #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."]
613 _0,
614 #[doc = "A hardware trigger activates the OUTMASK register synchronization."]
615 _1,
616}
617impl HWOMR {
618 #[doc = r" Returns `true` if the bit is clear (0)"]
619 #[inline]
620 pub fn bit_is_clear(&self) -> bool {
621 !self.bit()
622 }
623 #[doc = r" Returns `true` if the bit is set (1)"]
624 #[inline]
625 pub fn bit_is_set(&self) -> bool {
626 self.bit()
627 }
628 #[doc = r" Value of the field as raw bits"]
629 #[inline]
630 pub fn bit(&self) -> bool {
631 match *self {
632 HWOMR::_0 => false,
633 HWOMR::_1 => true,
634 }
635 }
636 #[allow(missing_docs)]
637 #[doc(hidden)]
638 #[inline]
639 pub fn _from(value: bool) -> HWOMR {
640 match value {
641 false => HWOMR::_0,
642 true => HWOMR::_1,
643 }
644 }
645 #[doc = "Checks if the value of the field is `_0`"]
646 #[inline]
647 pub fn is_0(&self) -> bool {
648 *self == HWOMR::_0
649 }
650 #[doc = "Checks if the value of the field is `_1`"]
651 #[inline]
652 pub fn is_1(&self) -> bool {
653 *self == HWOMR::_1
654 }
655}
656#[doc = "Possible values of the field `HWINVC`"]
657#[derive(Clone, Copy, Debug, PartialEq)]
658pub enum HWINVCR {
659 #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."]
660 _0,
661 #[doc = "A hardware trigger activates the INVCTRL register synchronization."]
662 _1,
663}
664impl HWINVCR {
665 #[doc = r" Returns `true` if the bit is clear (0)"]
666 #[inline]
667 pub fn bit_is_clear(&self) -> bool {
668 !self.bit()
669 }
670 #[doc = r" Returns `true` if the bit is set (1)"]
671 #[inline]
672 pub fn bit_is_set(&self) -> bool {
673 self.bit()
674 }
675 #[doc = r" Value of the field as raw bits"]
676 #[inline]
677 pub fn bit(&self) -> bool {
678 match *self {
679 HWINVCR::_0 => false,
680 HWINVCR::_1 => true,
681 }
682 }
683 #[allow(missing_docs)]
684 #[doc(hidden)]
685 #[inline]
686 pub fn _from(value: bool) -> HWINVCR {
687 match value {
688 false => HWINVCR::_0,
689 true => HWINVCR::_1,
690 }
691 }
692 #[doc = "Checks if the value of the field is `_0`"]
693 #[inline]
694 pub fn is_0(&self) -> bool {
695 *self == HWINVCR::_0
696 }
697 #[doc = "Checks if the value of the field is `_1`"]
698 #[inline]
699 pub fn is_1(&self) -> bool {
700 *self == HWINVCR::_1
701 }
702}
703#[doc = "Possible values of the field `HWSOC`"]
704#[derive(Clone, Copy, Debug, PartialEq)]
705pub enum HWSOCR {
706 #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."]
707 _0,
708 #[doc = "A hardware trigger activates the SWOCTRL register synchronization."]
709 _1,
710}
711impl HWSOCR {
712 #[doc = r" Returns `true` if the bit is clear (0)"]
713 #[inline]
714 pub fn bit_is_clear(&self) -> bool {
715 !self.bit()
716 }
717 #[doc = r" Returns `true` if the bit is set (1)"]
718 #[inline]
719 pub fn bit_is_set(&self) -> bool {
720 self.bit()
721 }
722 #[doc = r" Value of the field as raw bits"]
723 #[inline]
724 pub fn bit(&self) -> bool {
725 match *self {
726 HWSOCR::_0 => false,
727 HWSOCR::_1 => true,
728 }
729 }
730 #[allow(missing_docs)]
731 #[doc(hidden)]
732 #[inline]
733 pub fn _from(value: bool) -> HWSOCR {
734 match value {
735 false => HWSOCR::_0,
736 true => HWSOCR::_1,
737 }
738 }
739 #[doc = "Checks if the value of the field is `_0`"]
740 #[inline]
741 pub fn is_0(&self) -> bool {
742 *self == HWSOCR::_0
743 }
744 #[doc = "Checks if the value of the field is `_1`"]
745 #[inline]
746 pub fn is_1(&self) -> bool {
747 *self == HWSOCR::_1
748 }
749}
750#[doc = "Values that can be written to the field `HWTRIGMODE`"]
751pub enum HWTRIGMODEW {
752 #[doc = "FTM clears the TRIGj bit when the hardware trigger j is detected."]
753 _0,
754 #[doc = "FTM does not clear the TRIGj bit when the hardware trigger j is detected."]
755 _1,
756}
757impl HWTRIGMODEW {
758 #[allow(missing_docs)]
759 #[doc(hidden)]
760 #[inline]
761 pub fn _bits(&self) -> bool {
762 match *self {
763 HWTRIGMODEW::_0 => false,
764 HWTRIGMODEW::_1 => true,
765 }
766 }
767}
768#[doc = r" Proxy"]
769pub struct _HWTRIGMODEW<'a> {
770 w: &'a mut W,
771}
772impl<'a> _HWTRIGMODEW<'a> {
773 #[doc = r" Writes `variant` to the field"]
774 #[inline]
775 pub fn variant(self, variant: HWTRIGMODEW) -> &'a mut W {
776 {
777 self.bit(variant._bits())
778 }
779 }
780 #[doc = "FTM clears the TRIGj bit when the hardware trigger j is detected."]
781 #[inline]
782 pub fn _0(self) -> &'a mut W {
783 self.variant(HWTRIGMODEW::_0)
784 }
785 #[doc = "FTM does not clear the TRIGj bit when the hardware trigger j is detected."]
786 #[inline]
787 pub fn _1(self) -> &'a mut W {
788 self.variant(HWTRIGMODEW::_1)
789 }
790 #[doc = r" Sets the field bit"]
791 pub fn set_bit(self) -> &'a mut W {
792 self.bit(true)
793 }
794 #[doc = r" Clears the field bit"]
795 pub fn clear_bit(self) -> &'a mut W {
796 self.bit(false)
797 }
798 #[doc = r" Writes raw bits to the field"]
799 #[inline]
800 pub fn bit(self, value: bool) -> &'a mut W {
801 const MASK: bool = true;
802 const OFFSET: u8 = 0;
803 self.w.bits &= !((MASK as u32) << OFFSET);
804 self.w.bits |= ((value & MASK) as u32) << OFFSET;
805 self.w
806 }
807}
808#[doc = "Values that can be written to the field `CNTINC`"]
809pub enum CNTINCW {
810 #[doc = "CNTIN register is updated with its buffer value at all rising edges of system clock."]
811 _0,
812 #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."]
813 _1,
814}
815impl CNTINCW {
816 #[allow(missing_docs)]
817 #[doc(hidden)]
818 #[inline]
819 pub fn _bits(&self) -> bool {
820 match *self {
821 CNTINCW::_0 => false,
822 CNTINCW::_1 => true,
823 }
824 }
825}
826#[doc = r" Proxy"]
827pub struct _CNTINCW<'a> {
828 w: &'a mut W,
829}
830impl<'a> _CNTINCW<'a> {
831 #[doc = r" Writes `variant` to the field"]
832 #[inline]
833 pub fn variant(self, variant: CNTINCW) -> &'a mut W {
834 {
835 self.bit(variant._bits())
836 }
837 }
838 #[doc = "CNTIN register is updated with its buffer value at all rising edges of system clock."]
839 #[inline]
840 pub fn _0(self) -> &'a mut W {
841 self.variant(CNTINCW::_0)
842 }
843 #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."]
844 #[inline]
845 pub fn _1(self) -> &'a mut W {
846 self.variant(CNTINCW::_1)
847 }
848 #[doc = r" Sets the field bit"]
849 pub fn set_bit(self) -> &'a mut W {
850 self.bit(true)
851 }
852 #[doc = r" Clears the field bit"]
853 pub fn clear_bit(self) -> &'a mut W {
854 self.bit(false)
855 }
856 #[doc = r" Writes raw bits to the field"]
857 #[inline]
858 pub fn bit(self, value: bool) -> &'a mut W {
859 const MASK: bool = true;
860 const OFFSET: u8 = 2;
861 self.w.bits &= !((MASK as u32) << OFFSET);
862 self.w.bits |= ((value & MASK) as u32) << OFFSET;
863 self.w
864 }
865}
866#[doc = "Values that can be written to the field `INVC`"]
867pub enum INVCW {
868 #[doc = "INVCTRL register is updated with its buffer value at all rising edges of system clock."]
869 _0,
870 #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."]
871 _1,
872}
873impl INVCW {
874 #[allow(missing_docs)]
875 #[doc(hidden)]
876 #[inline]
877 pub fn _bits(&self) -> bool {
878 match *self {
879 INVCW::_0 => false,
880 INVCW::_1 => true,
881 }
882 }
883}
884#[doc = r" Proxy"]
885pub struct _INVCW<'a> {
886 w: &'a mut W,
887}
888impl<'a> _INVCW<'a> {
889 #[doc = r" Writes `variant` to the field"]
890 #[inline]
891 pub fn variant(self, variant: INVCW) -> &'a mut W {
892 {
893 self.bit(variant._bits())
894 }
895 }
896 #[doc = "INVCTRL register is updated with its buffer value at all rising edges of system clock."]
897 #[inline]
898 pub fn _0(self) -> &'a mut W {
899 self.variant(INVCW::_0)
900 }
901 #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."]
902 #[inline]
903 pub fn _1(self) -> &'a mut W {
904 self.variant(INVCW::_1)
905 }
906 #[doc = r" Sets the field bit"]
907 pub fn set_bit(self) -> &'a mut W {
908 self.bit(true)
909 }
910 #[doc = r" Clears the field bit"]
911 pub fn clear_bit(self) -> &'a mut W {
912 self.bit(false)
913 }
914 #[doc = r" Writes raw bits to the field"]
915 #[inline]
916 pub fn bit(self, value: bool) -> &'a mut W {
917 const MASK: bool = true;
918 const OFFSET: u8 = 4;
919 self.w.bits &= !((MASK as u32) << OFFSET);
920 self.w.bits |= ((value & MASK) as u32) << OFFSET;
921 self.w
922 }
923}
924#[doc = "Values that can be written to the field `SWOC`"]
925pub enum SWOCW {
926 #[doc = "SWOCTRL register is updated with its buffer value at all rising edges of system clock."]
927 _0,
928 #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."]
929 _1,
930}
931impl SWOCW {
932 #[allow(missing_docs)]
933 #[doc(hidden)]
934 #[inline]
935 pub fn _bits(&self) -> bool {
936 match *self {
937 SWOCW::_0 => false,
938 SWOCW::_1 => true,
939 }
940 }
941}
942#[doc = r" Proxy"]
943pub struct _SWOCW<'a> {
944 w: &'a mut W,
945}
946impl<'a> _SWOCW<'a> {
947 #[doc = r" Writes `variant` to the field"]
948 #[inline]
949 pub fn variant(self, variant: SWOCW) -> &'a mut W {
950 {
951 self.bit(variant._bits())
952 }
953 }
954 #[doc = "SWOCTRL register is updated with its buffer value at all rising edges of system clock."]
955 #[inline]
956 pub fn _0(self) -> &'a mut W {
957 self.variant(SWOCW::_0)
958 }
959 #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."]
960 #[inline]
961 pub fn _1(self) -> &'a mut W {
962 self.variant(SWOCW::_1)
963 }
964 #[doc = r" Sets the field bit"]
965 pub fn set_bit(self) -> &'a mut W {
966 self.bit(true)
967 }
968 #[doc = r" Clears the field bit"]
969 pub fn clear_bit(self) -> &'a mut W {
970 self.bit(false)
971 }
972 #[doc = r" Writes raw bits to the field"]
973 #[inline]
974 pub fn bit(self, value: bool) -> &'a mut W {
975 const MASK: bool = true;
976 const OFFSET: u8 = 5;
977 self.w.bits &= !((MASK as u32) << OFFSET);
978 self.w.bits |= ((value & MASK) as u32) << OFFSET;
979 self.w
980 }
981}
982#[doc = "Values that can be written to the field `SYNCMODE`"]
983pub enum SYNCMODEW {
984 #[doc = "Legacy PWM synchronization is selected."]
985 _0,
986 #[doc = "Enhanced PWM synchronization is selected."]
987 _1,
988}
989impl SYNCMODEW {
990 #[allow(missing_docs)]
991 #[doc(hidden)]
992 #[inline]
993 pub fn _bits(&self) -> bool {
994 match *self {
995 SYNCMODEW::_0 => false,
996 SYNCMODEW::_1 => true,
997 }
998 }
999}
1000#[doc = r" Proxy"]
1001pub struct _SYNCMODEW<'a> {
1002 w: &'a mut W,
1003}
1004impl<'a> _SYNCMODEW<'a> {
1005 #[doc = r" Writes `variant` to the field"]
1006 #[inline]
1007 pub fn variant(self, variant: SYNCMODEW) -> &'a mut W {
1008 {
1009 self.bit(variant._bits())
1010 }
1011 }
1012 #[doc = "Legacy PWM synchronization is selected."]
1013 #[inline]
1014 pub fn _0(self) -> &'a mut W {
1015 self.variant(SYNCMODEW::_0)
1016 }
1017 #[doc = "Enhanced PWM synchronization is selected."]
1018 #[inline]
1019 pub fn _1(self) -> &'a mut W {
1020 self.variant(SYNCMODEW::_1)
1021 }
1022 #[doc = r" Sets the field bit"]
1023 pub fn set_bit(self) -> &'a mut W {
1024 self.bit(true)
1025 }
1026 #[doc = r" Clears the field bit"]
1027 pub fn clear_bit(self) -> &'a mut W {
1028 self.bit(false)
1029 }
1030 #[doc = r" Writes raw bits to the field"]
1031 #[inline]
1032 pub fn bit(self, value: bool) -> &'a mut W {
1033 const MASK: bool = true;
1034 const OFFSET: u8 = 7;
1035 self.w.bits &= !((MASK as u32) << OFFSET);
1036 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1037 self.w
1038 }
1039}
1040#[doc = "Values that can be written to the field `SWRSTCNT`"]
1041pub enum SWRSTCNTW {
1042 #[doc = "The software trigger does not activate the FTM counter synchronization."]
1043 _0,
1044 #[doc = "The software trigger activates the FTM counter synchronization."]
1045 _1,
1046}
1047impl SWRSTCNTW {
1048 #[allow(missing_docs)]
1049 #[doc(hidden)]
1050 #[inline]
1051 pub fn _bits(&self) -> bool {
1052 match *self {
1053 SWRSTCNTW::_0 => false,
1054 SWRSTCNTW::_1 => true,
1055 }
1056 }
1057}
1058#[doc = r" Proxy"]
1059pub struct _SWRSTCNTW<'a> {
1060 w: &'a mut W,
1061}
1062impl<'a> _SWRSTCNTW<'a> {
1063 #[doc = r" Writes `variant` to the field"]
1064 #[inline]
1065 pub fn variant(self, variant: SWRSTCNTW) -> &'a mut W {
1066 {
1067 self.bit(variant._bits())
1068 }
1069 }
1070 #[doc = "The software trigger does not activate the FTM counter synchronization."]
1071 #[inline]
1072 pub fn _0(self) -> &'a mut W {
1073 self.variant(SWRSTCNTW::_0)
1074 }
1075 #[doc = "The software trigger activates the FTM counter synchronization."]
1076 #[inline]
1077 pub fn _1(self) -> &'a mut W {
1078 self.variant(SWRSTCNTW::_1)
1079 }
1080 #[doc = r" Sets the field bit"]
1081 pub fn set_bit(self) -> &'a mut W {
1082 self.bit(true)
1083 }
1084 #[doc = r" Clears the field bit"]
1085 pub fn clear_bit(self) -> &'a mut W {
1086 self.bit(false)
1087 }
1088 #[doc = r" Writes raw bits to the field"]
1089 #[inline]
1090 pub fn bit(self, value: bool) -> &'a mut W {
1091 const MASK: bool = true;
1092 const OFFSET: u8 = 8;
1093 self.w.bits &= !((MASK as u32) << OFFSET);
1094 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1095 self.w
1096 }
1097}
1098#[doc = "Values that can be written to the field `SWWRBUF`"]
1099pub enum SWWRBUFW {
1100 #[doc = "The software trigger does not activate MOD, CNTIN, and CV registers synchronization."]
1101 _0,
1102 #[doc = "The software trigger activates MOD, CNTIN, and CV registers synchronization."]
1103 _1,
1104}
1105impl SWWRBUFW {
1106 #[allow(missing_docs)]
1107 #[doc(hidden)]
1108 #[inline]
1109 pub fn _bits(&self) -> bool {
1110 match *self {
1111 SWWRBUFW::_0 => false,
1112 SWWRBUFW::_1 => true,
1113 }
1114 }
1115}
1116#[doc = r" Proxy"]
1117pub struct _SWWRBUFW<'a> {
1118 w: &'a mut W,
1119}
1120impl<'a> _SWWRBUFW<'a> {
1121 #[doc = r" Writes `variant` to the field"]
1122 #[inline]
1123 pub fn variant(self, variant: SWWRBUFW) -> &'a mut W {
1124 {
1125 self.bit(variant._bits())
1126 }
1127 }
1128 #[doc = "The software trigger does not activate MOD, CNTIN, and CV registers synchronization."]
1129 #[inline]
1130 pub fn _0(self) -> &'a mut W {
1131 self.variant(SWWRBUFW::_0)
1132 }
1133 #[doc = "The software trigger activates MOD, CNTIN, and CV registers synchronization."]
1134 #[inline]
1135 pub fn _1(self) -> &'a mut W {
1136 self.variant(SWWRBUFW::_1)
1137 }
1138 #[doc = r" Sets the field bit"]
1139 pub fn set_bit(self) -> &'a mut W {
1140 self.bit(true)
1141 }
1142 #[doc = r" Clears the field bit"]
1143 pub fn clear_bit(self) -> &'a mut W {
1144 self.bit(false)
1145 }
1146 #[doc = r" Writes raw bits to the field"]
1147 #[inline]
1148 pub fn bit(self, value: bool) -> &'a mut W {
1149 const MASK: bool = true;
1150 const OFFSET: u8 = 9;
1151 self.w.bits &= !((MASK as u32) << OFFSET);
1152 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1153 self.w
1154 }
1155}
1156#[doc = "Values that can be written to the field `SWOM`"]
1157pub enum SWOMW {
1158 #[doc = "The software trigger does not activate the OUTMASK register synchronization."]
1159 _0,
1160 #[doc = "The software trigger activates the OUTMASK register synchronization."]
1161 _1,
1162}
1163impl SWOMW {
1164 #[allow(missing_docs)]
1165 #[doc(hidden)]
1166 #[inline]
1167 pub fn _bits(&self) -> bool {
1168 match *self {
1169 SWOMW::_0 => false,
1170 SWOMW::_1 => true,
1171 }
1172 }
1173}
1174#[doc = r" Proxy"]
1175pub struct _SWOMW<'a> {
1176 w: &'a mut W,
1177}
1178impl<'a> _SWOMW<'a> {
1179 #[doc = r" Writes `variant` to the field"]
1180 #[inline]
1181 pub fn variant(self, variant: SWOMW) -> &'a mut W {
1182 {
1183 self.bit(variant._bits())
1184 }
1185 }
1186 #[doc = "The software trigger does not activate the OUTMASK register synchronization."]
1187 #[inline]
1188 pub fn _0(self) -> &'a mut W {
1189 self.variant(SWOMW::_0)
1190 }
1191 #[doc = "The software trigger activates the OUTMASK register synchronization."]
1192 #[inline]
1193 pub fn _1(self) -> &'a mut W {
1194 self.variant(SWOMW::_1)
1195 }
1196 #[doc = r" Sets the field bit"]
1197 pub fn set_bit(self) -> &'a mut W {
1198 self.bit(true)
1199 }
1200 #[doc = r" Clears the field bit"]
1201 pub fn clear_bit(self) -> &'a mut W {
1202 self.bit(false)
1203 }
1204 #[doc = r" Writes raw bits to the field"]
1205 #[inline]
1206 pub fn bit(self, value: bool) -> &'a mut W {
1207 const MASK: bool = true;
1208 const OFFSET: u8 = 10;
1209 self.w.bits &= !((MASK as u32) << OFFSET);
1210 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1211 self.w
1212 }
1213}
1214#[doc = "Values that can be written to the field `SWINVC`"]
1215pub enum SWINVCW {
1216 #[doc = "The software trigger does not activate the INVCTRL register synchronization."]
1217 _0,
1218 #[doc = "The software trigger activates the INVCTRL register synchronization."]
1219 _1,
1220}
1221impl SWINVCW {
1222 #[allow(missing_docs)]
1223 #[doc(hidden)]
1224 #[inline]
1225 pub fn _bits(&self) -> bool {
1226 match *self {
1227 SWINVCW::_0 => false,
1228 SWINVCW::_1 => true,
1229 }
1230 }
1231}
1232#[doc = r" Proxy"]
1233pub struct _SWINVCW<'a> {
1234 w: &'a mut W,
1235}
1236impl<'a> _SWINVCW<'a> {
1237 #[doc = r" Writes `variant` to the field"]
1238 #[inline]
1239 pub fn variant(self, variant: SWINVCW) -> &'a mut W {
1240 {
1241 self.bit(variant._bits())
1242 }
1243 }
1244 #[doc = "The software trigger does not activate the INVCTRL register synchronization."]
1245 #[inline]
1246 pub fn _0(self) -> &'a mut W {
1247 self.variant(SWINVCW::_0)
1248 }
1249 #[doc = "The software trigger activates the INVCTRL register synchronization."]
1250 #[inline]
1251 pub fn _1(self) -> &'a mut W {
1252 self.variant(SWINVCW::_1)
1253 }
1254 #[doc = r" Sets the field bit"]
1255 pub fn set_bit(self) -> &'a mut W {
1256 self.bit(true)
1257 }
1258 #[doc = r" Clears the field bit"]
1259 pub fn clear_bit(self) -> &'a mut W {
1260 self.bit(false)
1261 }
1262 #[doc = r" Writes raw bits to the field"]
1263 #[inline]
1264 pub fn bit(self, value: bool) -> &'a mut W {
1265 const MASK: bool = true;
1266 const OFFSET: u8 = 11;
1267 self.w.bits &= !((MASK as u32) << OFFSET);
1268 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1269 self.w
1270 }
1271}
1272#[doc = "Values that can be written to the field `SWSOC`"]
1273pub enum SWSOCW {
1274 #[doc = "The software trigger does not activate the SWOCTRL register synchronization."]
1275 _0,
1276 #[doc = "The software trigger activates the SWOCTRL register synchronization."]
1277 _1,
1278}
1279impl SWSOCW {
1280 #[allow(missing_docs)]
1281 #[doc(hidden)]
1282 #[inline]
1283 pub fn _bits(&self) -> bool {
1284 match *self {
1285 SWSOCW::_0 => false,
1286 SWSOCW::_1 => true,
1287 }
1288 }
1289}
1290#[doc = r" Proxy"]
1291pub struct _SWSOCW<'a> {
1292 w: &'a mut W,
1293}
1294impl<'a> _SWSOCW<'a> {
1295 #[doc = r" Writes `variant` to the field"]
1296 #[inline]
1297 pub fn variant(self, variant: SWSOCW) -> &'a mut W {
1298 {
1299 self.bit(variant._bits())
1300 }
1301 }
1302 #[doc = "The software trigger does not activate the SWOCTRL register synchronization."]
1303 #[inline]
1304 pub fn _0(self) -> &'a mut W {
1305 self.variant(SWSOCW::_0)
1306 }
1307 #[doc = "The software trigger activates the SWOCTRL register synchronization."]
1308 #[inline]
1309 pub fn _1(self) -> &'a mut W {
1310 self.variant(SWSOCW::_1)
1311 }
1312 #[doc = r" Sets the field bit"]
1313 pub fn set_bit(self) -> &'a mut W {
1314 self.bit(true)
1315 }
1316 #[doc = r" Clears the field bit"]
1317 pub fn clear_bit(self) -> &'a mut W {
1318 self.bit(false)
1319 }
1320 #[doc = r" Writes raw bits to the field"]
1321 #[inline]
1322 pub fn bit(self, value: bool) -> &'a mut W {
1323 const MASK: bool = true;
1324 const OFFSET: u8 = 12;
1325 self.w.bits &= !((MASK as u32) << OFFSET);
1326 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1327 self.w
1328 }
1329}
1330#[doc = "Values that can be written to the field `HWRSTCNT`"]
1331pub enum HWRSTCNTW {
1332 #[doc = "A hardware trigger does not activate the FTM counter synchronization."]
1333 _0,
1334 #[doc = "A hardware trigger activates the FTM counter synchronization."]
1335 _1,
1336}
1337impl HWRSTCNTW {
1338 #[allow(missing_docs)]
1339 #[doc(hidden)]
1340 #[inline]
1341 pub fn _bits(&self) -> bool {
1342 match *self {
1343 HWRSTCNTW::_0 => false,
1344 HWRSTCNTW::_1 => true,
1345 }
1346 }
1347}
1348#[doc = r" Proxy"]
1349pub struct _HWRSTCNTW<'a> {
1350 w: &'a mut W,
1351}
1352impl<'a> _HWRSTCNTW<'a> {
1353 #[doc = r" Writes `variant` to the field"]
1354 #[inline]
1355 pub fn variant(self, variant: HWRSTCNTW) -> &'a mut W {
1356 {
1357 self.bit(variant._bits())
1358 }
1359 }
1360 #[doc = "A hardware trigger does not activate the FTM counter synchronization."]
1361 #[inline]
1362 pub fn _0(self) -> &'a mut W {
1363 self.variant(HWRSTCNTW::_0)
1364 }
1365 #[doc = "A hardware trigger activates the FTM counter synchronization."]
1366 #[inline]
1367 pub fn _1(self) -> &'a mut W {
1368 self.variant(HWRSTCNTW::_1)
1369 }
1370 #[doc = r" Sets the field bit"]
1371 pub fn set_bit(self) -> &'a mut W {
1372 self.bit(true)
1373 }
1374 #[doc = r" Clears the field bit"]
1375 pub fn clear_bit(self) -> &'a mut W {
1376 self.bit(false)
1377 }
1378 #[doc = r" Writes raw bits to the field"]
1379 #[inline]
1380 pub fn bit(self, value: bool) -> &'a mut W {
1381 const MASK: bool = true;
1382 const OFFSET: u8 = 16;
1383 self.w.bits &= !((MASK as u32) << OFFSET);
1384 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1385 self.w
1386 }
1387}
1388#[doc = "Values that can be written to the field `HWWRBUF`"]
1389pub enum HWWRBUFW {
1390 #[doc = "A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization."]
1391 _0,
1392 #[doc = "A hardware trigger activates MOD, CNTIN, and CV registers synchronization."]
1393 _1,
1394}
1395impl HWWRBUFW {
1396 #[allow(missing_docs)]
1397 #[doc(hidden)]
1398 #[inline]
1399 pub fn _bits(&self) -> bool {
1400 match *self {
1401 HWWRBUFW::_0 => false,
1402 HWWRBUFW::_1 => true,
1403 }
1404 }
1405}
1406#[doc = r" Proxy"]
1407pub struct _HWWRBUFW<'a> {
1408 w: &'a mut W,
1409}
1410impl<'a> _HWWRBUFW<'a> {
1411 #[doc = r" Writes `variant` to the field"]
1412 #[inline]
1413 pub fn variant(self, variant: HWWRBUFW) -> &'a mut W {
1414 {
1415 self.bit(variant._bits())
1416 }
1417 }
1418 #[doc = "A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization."]
1419 #[inline]
1420 pub fn _0(self) -> &'a mut W {
1421 self.variant(HWWRBUFW::_0)
1422 }
1423 #[doc = "A hardware trigger activates MOD, CNTIN, and CV registers synchronization."]
1424 #[inline]
1425 pub fn _1(self) -> &'a mut W {
1426 self.variant(HWWRBUFW::_1)
1427 }
1428 #[doc = r" Sets the field bit"]
1429 pub fn set_bit(self) -> &'a mut W {
1430 self.bit(true)
1431 }
1432 #[doc = r" Clears the field bit"]
1433 pub fn clear_bit(self) -> &'a mut W {
1434 self.bit(false)
1435 }
1436 #[doc = r" Writes raw bits to the field"]
1437 #[inline]
1438 pub fn bit(self, value: bool) -> &'a mut W {
1439 const MASK: bool = true;
1440 const OFFSET: u8 = 17;
1441 self.w.bits &= !((MASK as u32) << OFFSET);
1442 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1443 self.w
1444 }
1445}
1446#[doc = "Values that can be written to the field `HWOM`"]
1447pub enum HWOMW {
1448 #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."]
1449 _0,
1450 #[doc = "A hardware trigger activates the OUTMASK register synchronization."]
1451 _1,
1452}
1453impl HWOMW {
1454 #[allow(missing_docs)]
1455 #[doc(hidden)]
1456 #[inline]
1457 pub fn _bits(&self) -> bool {
1458 match *self {
1459 HWOMW::_0 => false,
1460 HWOMW::_1 => true,
1461 }
1462 }
1463}
1464#[doc = r" Proxy"]
1465pub struct _HWOMW<'a> {
1466 w: &'a mut W,
1467}
1468impl<'a> _HWOMW<'a> {
1469 #[doc = r" Writes `variant` to the field"]
1470 #[inline]
1471 pub fn variant(self, variant: HWOMW) -> &'a mut W {
1472 {
1473 self.bit(variant._bits())
1474 }
1475 }
1476 #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."]
1477 #[inline]
1478 pub fn _0(self) -> &'a mut W {
1479 self.variant(HWOMW::_0)
1480 }
1481 #[doc = "A hardware trigger activates the OUTMASK register synchronization."]
1482 #[inline]
1483 pub fn _1(self) -> &'a mut W {
1484 self.variant(HWOMW::_1)
1485 }
1486 #[doc = r" Sets the field bit"]
1487 pub fn set_bit(self) -> &'a mut W {
1488 self.bit(true)
1489 }
1490 #[doc = r" Clears the field bit"]
1491 pub fn clear_bit(self) -> &'a mut W {
1492 self.bit(false)
1493 }
1494 #[doc = r" Writes raw bits to the field"]
1495 #[inline]
1496 pub fn bit(self, value: bool) -> &'a mut W {
1497 const MASK: bool = true;
1498 const OFFSET: u8 = 18;
1499 self.w.bits &= !((MASK as u32) << OFFSET);
1500 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1501 self.w
1502 }
1503}
1504#[doc = "Values that can be written to the field `HWINVC`"]
1505pub enum HWINVCW {
1506 #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."]
1507 _0,
1508 #[doc = "A hardware trigger activates the INVCTRL register synchronization."]
1509 _1,
1510}
1511impl HWINVCW {
1512 #[allow(missing_docs)]
1513 #[doc(hidden)]
1514 #[inline]
1515 pub fn _bits(&self) -> bool {
1516 match *self {
1517 HWINVCW::_0 => false,
1518 HWINVCW::_1 => true,
1519 }
1520 }
1521}
1522#[doc = r" Proxy"]
1523pub struct _HWINVCW<'a> {
1524 w: &'a mut W,
1525}
1526impl<'a> _HWINVCW<'a> {
1527 #[doc = r" Writes `variant` to the field"]
1528 #[inline]
1529 pub fn variant(self, variant: HWINVCW) -> &'a mut W {
1530 {
1531 self.bit(variant._bits())
1532 }
1533 }
1534 #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."]
1535 #[inline]
1536 pub fn _0(self) -> &'a mut W {
1537 self.variant(HWINVCW::_0)
1538 }
1539 #[doc = "A hardware trigger activates the INVCTRL register synchronization."]
1540 #[inline]
1541 pub fn _1(self) -> &'a mut W {
1542 self.variant(HWINVCW::_1)
1543 }
1544 #[doc = r" Sets the field bit"]
1545 pub fn set_bit(self) -> &'a mut W {
1546 self.bit(true)
1547 }
1548 #[doc = r" Clears the field bit"]
1549 pub fn clear_bit(self) -> &'a mut W {
1550 self.bit(false)
1551 }
1552 #[doc = r" Writes raw bits to the field"]
1553 #[inline]
1554 pub fn bit(self, value: bool) -> &'a mut W {
1555 const MASK: bool = true;
1556 const OFFSET: u8 = 19;
1557 self.w.bits &= !((MASK as u32) << OFFSET);
1558 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1559 self.w
1560 }
1561}
1562#[doc = "Values that can be written to the field `HWSOC`"]
1563pub enum HWSOCW {
1564 #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."]
1565 _0,
1566 #[doc = "A hardware trigger activates the SWOCTRL register synchronization."]
1567 _1,
1568}
1569impl HWSOCW {
1570 #[allow(missing_docs)]
1571 #[doc(hidden)]
1572 #[inline]
1573 pub fn _bits(&self) -> bool {
1574 match *self {
1575 HWSOCW::_0 => false,
1576 HWSOCW::_1 => true,
1577 }
1578 }
1579}
1580#[doc = r" Proxy"]
1581pub struct _HWSOCW<'a> {
1582 w: &'a mut W,
1583}
1584impl<'a> _HWSOCW<'a> {
1585 #[doc = r" Writes `variant` to the field"]
1586 #[inline]
1587 pub fn variant(self, variant: HWSOCW) -> &'a mut W {
1588 {
1589 self.bit(variant._bits())
1590 }
1591 }
1592 #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."]
1593 #[inline]
1594 pub fn _0(self) -> &'a mut W {
1595 self.variant(HWSOCW::_0)
1596 }
1597 #[doc = "A hardware trigger activates the SWOCTRL register synchronization."]
1598 #[inline]
1599 pub fn _1(self) -> &'a mut W {
1600 self.variant(HWSOCW::_1)
1601 }
1602 #[doc = r" Sets the field bit"]
1603 pub fn set_bit(self) -> &'a mut W {
1604 self.bit(true)
1605 }
1606 #[doc = r" Clears the field bit"]
1607 pub fn clear_bit(self) -> &'a mut W {
1608 self.bit(false)
1609 }
1610 #[doc = r" Writes raw bits to the field"]
1611 #[inline]
1612 pub fn bit(self, value: bool) -> &'a mut W {
1613 const MASK: bool = true;
1614 const OFFSET: u8 = 20;
1615 self.w.bits &= !((MASK as u32) << OFFSET);
1616 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1617 self.w
1618 }
1619}
1620impl R {
1621 #[doc = r" Value of the register as raw bits"]
1622 #[inline]
1623 pub fn bits(&self) -> u32 {
1624 self.bits
1625 }
1626 #[doc = "Bit 0 - Hardware Trigger Mode"]
1627 #[inline]
1628 pub fn hwtrigmode(&self) -> HWTRIGMODER {
1629 HWTRIGMODER::_from({
1630 const MASK: bool = true;
1631 const OFFSET: u8 = 0;
1632 ((self.bits >> OFFSET) & MASK as u32) != 0
1633 })
1634 }
1635 #[doc = "Bit 2 - CNTIN register synchronization"]
1636 #[inline]
1637 pub fn cntinc(&self) -> CNTINCR {
1638 CNTINCR::_from({
1639 const MASK: bool = true;
1640 const OFFSET: u8 = 2;
1641 ((self.bits >> OFFSET) & MASK as u32) != 0
1642 })
1643 }
1644 #[doc = "Bit 4 - INVCTRL register synchronization"]
1645 #[inline]
1646 pub fn invc(&self) -> INVCR {
1647 INVCR::_from({
1648 const MASK: bool = true;
1649 const OFFSET: u8 = 4;
1650 ((self.bits >> OFFSET) & MASK as u32) != 0
1651 })
1652 }
1653 #[doc = "Bit 5 - SWOCTRL register synchronization"]
1654 #[inline]
1655 pub fn swoc(&self) -> SWOCR {
1656 SWOCR::_from({
1657 const MASK: bool = true;
1658 const OFFSET: u8 = 5;
1659 ((self.bits >> OFFSET) & MASK as u32) != 0
1660 })
1661 }
1662 #[doc = "Bit 7 - Synchronization Mode"]
1663 #[inline]
1664 pub fn syncmode(&self) -> SYNCMODER {
1665 SYNCMODER::_from({
1666 const MASK: bool = true;
1667 const OFFSET: u8 = 7;
1668 ((self.bits >> OFFSET) & MASK as u32) != 0
1669 })
1670 }
1671 #[doc = "Bit 8 - no description available"]
1672 #[inline]
1673 pub fn swrstcnt(&self) -> SWRSTCNTR {
1674 SWRSTCNTR::_from({
1675 const MASK: bool = true;
1676 const OFFSET: u8 = 8;
1677 ((self.bits >> OFFSET) & MASK as u32) != 0
1678 })
1679 }
1680 #[doc = "Bit 9 - no description available"]
1681 #[inline]
1682 pub fn swwrbuf(&self) -> SWWRBUFR {
1683 SWWRBUFR::_from({
1684 const MASK: bool = true;
1685 const OFFSET: u8 = 9;
1686 ((self.bits >> OFFSET) & MASK as u32) != 0
1687 })
1688 }
1689 #[doc = "Bit 10 - no description available"]
1690 #[inline]
1691 pub fn swom(&self) -> SWOMR {
1692 SWOMR::_from({
1693 const MASK: bool = true;
1694 const OFFSET: u8 = 10;
1695 ((self.bits >> OFFSET) & MASK as u32) != 0
1696 })
1697 }
1698 #[doc = "Bit 11 - no description available"]
1699 #[inline]
1700 pub fn swinvc(&self) -> SWINVCR {
1701 SWINVCR::_from({
1702 const MASK: bool = true;
1703 const OFFSET: u8 = 11;
1704 ((self.bits >> OFFSET) & MASK as u32) != 0
1705 })
1706 }
1707 #[doc = "Bit 12 - no description available"]
1708 #[inline]
1709 pub fn swsoc(&self) -> SWSOCR {
1710 SWSOCR::_from({
1711 const MASK: bool = true;
1712 const OFFSET: u8 = 12;
1713 ((self.bits >> OFFSET) & MASK as u32) != 0
1714 })
1715 }
1716 #[doc = "Bit 16 - no description available"]
1717 #[inline]
1718 pub fn hwrstcnt(&self) -> HWRSTCNTR {
1719 HWRSTCNTR::_from({
1720 const MASK: bool = true;
1721 const OFFSET: u8 = 16;
1722 ((self.bits >> OFFSET) & MASK as u32) != 0
1723 })
1724 }
1725 #[doc = "Bit 17 - no description available"]
1726 #[inline]
1727 pub fn hwwrbuf(&self) -> HWWRBUFR {
1728 HWWRBUFR::_from({
1729 const MASK: bool = true;
1730 const OFFSET: u8 = 17;
1731 ((self.bits >> OFFSET) & MASK as u32) != 0
1732 })
1733 }
1734 #[doc = "Bit 18 - no description available"]
1735 #[inline]
1736 pub fn hwom(&self) -> HWOMR {
1737 HWOMR::_from({
1738 const MASK: bool = true;
1739 const OFFSET: u8 = 18;
1740 ((self.bits >> OFFSET) & MASK as u32) != 0
1741 })
1742 }
1743 #[doc = "Bit 19 - no description available"]
1744 #[inline]
1745 pub fn hwinvc(&self) -> HWINVCR {
1746 HWINVCR::_from({
1747 const MASK: bool = true;
1748 const OFFSET: u8 = 19;
1749 ((self.bits >> OFFSET) & MASK as u32) != 0
1750 })
1751 }
1752 #[doc = "Bit 20 - no description available"]
1753 #[inline]
1754 pub fn hwsoc(&self) -> HWSOCR {
1755 HWSOCR::_from({
1756 const MASK: bool = true;
1757 const OFFSET: u8 = 20;
1758 ((self.bits >> OFFSET) & MASK as u32) != 0
1759 })
1760 }
1761}
1762impl W {
1763 #[doc = r" Reset value of the register"]
1764 #[inline]
1765 pub fn reset_value() -> W {
1766 W { bits: 0 }
1767 }
1768 #[doc = r" Writes raw bits to the register"]
1769 #[inline]
1770 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1771 self.bits = bits;
1772 self
1773 }
1774 #[doc = "Bit 0 - Hardware Trigger Mode"]
1775 #[inline]
1776 pub fn hwtrigmode(&mut self) -> _HWTRIGMODEW {
1777 _HWTRIGMODEW { w: self }
1778 }
1779 #[doc = "Bit 2 - CNTIN register synchronization"]
1780 #[inline]
1781 pub fn cntinc(&mut self) -> _CNTINCW {
1782 _CNTINCW { w: self }
1783 }
1784 #[doc = "Bit 4 - INVCTRL register synchronization"]
1785 #[inline]
1786 pub fn invc(&mut self) -> _INVCW {
1787 _INVCW { w: self }
1788 }
1789 #[doc = "Bit 5 - SWOCTRL register synchronization"]
1790 #[inline]
1791 pub fn swoc(&mut self) -> _SWOCW {
1792 _SWOCW { w: self }
1793 }
1794 #[doc = "Bit 7 - Synchronization Mode"]
1795 #[inline]
1796 pub fn syncmode(&mut self) -> _SYNCMODEW {
1797 _SYNCMODEW { w: self }
1798 }
1799 #[doc = "Bit 8 - no description available"]
1800 #[inline]
1801 pub fn swrstcnt(&mut self) -> _SWRSTCNTW {
1802 _SWRSTCNTW { w: self }
1803 }
1804 #[doc = "Bit 9 - no description available"]
1805 #[inline]
1806 pub fn swwrbuf(&mut self) -> _SWWRBUFW {
1807 _SWWRBUFW { w: self }
1808 }
1809 #[doc = "Bit 10 - no description available"]
1810 #[inline]
1811 pub fn swom(&mut self) -> _SWOMW {
1812 _SWOMW { w: self }
1813 }
1814 #[doc = "Bit 11 - no description available"]
1815 #[inline]
1816 pub fn swinvc(&mut self) -> _SWINVCW {
1817 _SWINVCW { w: self }
1818 }
1819 #[doc = "Bit 12 - no description available"]
1820 #[inline]
1821 pub fn swsoc(&mut self) -> _SWSOCW {
1822 _SWSOCW { w: self }
1823 }
1824 #[doc = "Bit 16 - no description available"]
1825 #[inline]
1826 pub fn hwrstcnt(&mut self) -> _HWRSTCNTW {
1827 _HWRSTCNTW { w: self }
1828 }
1829 #[doc = "Bit 17 - no description available"]
1830 #[inline]
1831 pub fn hwwrbuf(&mut self) -> _HWWRBUFW {
1832 _HWWRBUFW { w: self }
1833 }
1834 #[doc = "Bit 18 - no description available"]
1835 #[inline]
1836 pub fn hwom(&mut self) -> _HWOMW {
1837 _HWOMW { w: self }
1838 }
1839 #[doc = "Bit 19 - no description available"]
1840 #[inline]
1841 pub fn hwinvc(&mut self) -> _HWINVCW {
1842 _HWINVCW { w: self }
1843 }
1844 #[doc = "Bit 20 - no description available"]
1845 #[inline]
1846 pub fn hwsoc(&mut self) -> _HWSOCW {
1847 _HWSOCW { w: self }
1848 }
1849}