mk20d7_hal/
sim.rs

1use mk20d7::{sim::RegisterBlock, sim::clkdiv1};
2
3pub const MAXIMUM_CLOCK_FREQUENCY: u8 = 72;
4
5pub struct SystemIntegrationModule<'a> {
6    sim: &'a RegisterBlock,
7}
8
9impl<'a> SystemIntegrationModule<'a> {
10    pub fn new (sim: &'a RegisterBlock) -> SystemIntegrationModule<'a> {
11        SystemIntegrationModule { sim }
12    }
13
14    pub fn set_dividers(&mut self, core: u8, bus: u8, flash: u8) {
15        self.sim.clkdiv1.write(
16            |w| {
17                {
18                    let core_w = w.outdiv1();
19                    match core {
20                        1 => core_w._0000(),
21                        2 => core_w._0001(),
22                        3 => core_w._0010(),
23                        4 => core_w._0011(),
24                        5 => core_w._0100(),
25                        6 => core_w._0101(),
26                        7 => core_w._0110(),
27                        8 => core_w._0111(),
28                        9 => core_w._1000(),
29                        10 => core_w._1001(),
30                        11 => core_w._1010(),
31                        12 => core_w._1011(),
32                        13 => core_w._1100(),
33                        14 => core_w._1101(),
34                        15 => core_w._1110(),
35                        16 => core_w._1111(),
36                        _ => panic!("Must use core value in range [1, 16]!"),
37                    };
38                }
39
40                {
41                    let bus_w = w.outdiv2();
42                    match bus {
43                        1 => bus_w._0000(),
44                        2 => bus_w._0001(),
45                        3 => bus_w._0010(),
46                        4 => bus_w._0011(),
47                        5 => bus_w._0100(),
48                        6 => bus_w._0101(),
49                        7 => bus_w._0110(),
50                        8 => bus_w._0111(),
51                        9 => bus_w._1000(),
52                        10 => bus_w._1001(),
53                        11 => bus_w._1010(),
54                        12 => bus_w._1011(),
55                        13 => bus_w._1100(),
56                        14 => bus_w._1101(),
57                        15 => bus_w._1110(),
58                        16 => bus_w._1111(),
59                        _ => panic!("Must use bus value in range [1, 16]!"),
60                    };
61                }
62
63                {
64                    let flash_w = w.outdiv4();
65                    match flash {
66                        1 => flash_w._0000(),
67                        2 => flash_w._0001(),
68                        3 => flash_w._0010(),
69                        4 => flash_w._0011(),
70                        5 => flash_w._0100(),
71                        6 => flash_w._0101(),
72                        7 => flash_w._0110(),
73                        8 => flash_w._0111(),
74                        9 => flash_w._1000(),
75                        10 => flash_w._1001(),
76                        11 => flash_w._1010(),
77                        12 => flash_w._1011(),
78                        13 => flash_w._1100(),
79                        14 => flash_w._1101(),
80                        15 => flash_w._1110(),
81                        16 => flash_w._1111(),
82                        _ => panic!("Must use flash value in range [1, 16]!"),
83                    };
84                }
85
86                w
87            }
88        )
89    }
90
91    pub fn get_dividers(&self) -> (u8, u8, u8) {
92        let r = self.sim.clkdiv1.read();
93
94        let core = match r.outdiv1() {
95            clkdiv1::OUTDIV1R::_0000 => 1,
96            clkdiv1::OUTDIV1R::_0001 => 2,
97            clkdiv1::OUTDIV1R::_0010 => 3,
98            clkdiv1::OUTDIV1R::_0011 => 4,
99            clkdiv1::OUTDIV1R::_0100 => 5,
100            clkdiv1::OUTDIV1R::_0101 => 6,
101            clkdiv1::OUTDIV1R::_0110 => 7,
102            clkdiv1::OUTDIV1R::_0111 => 8,
103            clkdiv1::OUTDIV1R::_1000 => 9,
104            clkdiv1::OUTDIV1R::_1001 => 10,
105            clkdiv1::OUTDIV1R::_1010 => 11,
106            clkdiv1::OUTDIV1R::_1011 => 12,
107            clkdiv1::OUTDIV1R::_1100 => 13,
108            clkdiv1::OUTDIV1R::_1101 => 14,
109            clkdiv1::OUTDIV1R::_1110 => 15,
110            clkdiv1::OUTDIV1R::_1111 => 16,
111        };
112
113        let bus = match r.outdiv2() {
114            clkdiv1::OUTDIV2R::_0000 => 1,
115            clkdiv1::OUTDIV2R::_0001 => 2,
116            clkdiv1::OUTDIV2R::_0010 => 3,
117            clkdiv1::OUTDIV2R::_0011 => 4,
118            clkdiv1::OUTDIV2R::_0100 => 5,
119            clkdiv1::OUTDIV2R::_0101 => 6,
120            clkdiv1::OUTDIV2R::_0110 => 7,
121            clkdiv1::OUTDIV2R::_0111 => 8,
122            clkdiv1::OUTDIV2R::_1000 => 9,
123            clkdiv1::OUTDIV2R::_1001 => 10,
124            clkdiv1::OUTDIV2R::_1010 => 11,
125            clkdiv1::OUTDIV2R::_1011 => 12,
126            clkdiv1::OUTDIV2R::_1100 => 13,
127            clkdiv1::OUTDIV2R::_1101 => 14,
128            clkdiv1::OUTDIV2R::_1110 => 15,
129            clkdiv1::OUTDIV2R::_1111 => 16,
130        };
131
132        let flash = match r.outdiv4() {
133            clkdiv1::OUTDIV4R::_0000 => 1,
134            clkdiv1::OUTDIV4R::_0001 => 2,
135            clkdiv1::OUTDIV4R::_0010 => 3,
136            clkdiv1::OUTDIV4R::_0011 => 4,
137            clkdiv1::OUTDIV4R::_0100 => 5,
138            clkdiv1::OUTDIV4R::_0101 => 6,
139            clkdiv1::OUTDIV4R::_0110 => 7,
140            clkdiv1::OUTDIV4R::_0111 => 8,
141            clkdiv1::OUTDIV4R::_1000 => 9,
142            clkdiv1::OUTDIV4R::_1001 => 10,
143            clkdiv1::OUTDIV4R::_1010 => 11,
144            clkdiv1::OUTDIV4R::_1011 => 12,
145            clkdiv1::OUTDIV4R::_1100 => 13,
146            clkdiv1::OUTDIV4R::_1101 => 14,
147            clkdiv1::OUTDIV4R::_1110 => 15,
148            clkdiv1::OUTDIV4R::_1111 => 16,
149        };
150
151        (core, bus, flash)
152    }
153
154    pub fn get_frequencies(&self) -> (u8, u8, u8) {
155        let (core, bus, flash) = self.get_dividers();
156        (
157            MAXIMUM_CLOCK_FREQUENCY / core,
158            MAXIMUM_CLOCK_FREQUENCY / bus,
159            MAXIMUM_CLOCK_FREQUENCY / flash,
160        )
161    }
162}
mk20d7_hal/sim.rs

mk20d7_hal/
sim.rs
