mips_mcu/
interrupt.rs

1//! Interrupts
2// This is based on Work (c) by Jorge Aparicio, see
3// https://github.com/rust-embedded/cortex-m
4
5type IrqSave = u32;
6
7/// Enable multi-vectored interrupts
8#[inline]
9pub fn enable_mv_irq() {
10    extern "C" {
11        fn mips_enable_mv_irq();
12    }
13    unsafe {
14        mips_enable_mv_irq();
15    }
16}
17
18/// Disables all interrupts and return previous status
19#[inline]
20pub fn disable() -> IrqSave {
21    extern "C" {
22        fn mips_di() -> u32;
23    }
24    unsafe { mips_di() }
25}
26
27/// Enables all the interrupts and return previous status
28///
29/// # Safety
30///
31/// Do not call this function inside a critical section
32#[inline]
33pub unsafe fn enable() -> IrqSave {
34    extern "C" {
35        fn mips_ei() -> u32;
36    }
37    mips_ei()
38}
39
40/// Restore previously saved IRQ enablement state
41///
42/// # Safety
43///
44/// Do not call this function inside a critical section
45pub unsafe fn restore(previous_status: IrqSave) {
46    extern "C" {
47        fn mips_restore_irq(previous_status: u32);
48    }
49    mips_restore_irq(previous_status)
50}
51
52/// Wait for interrupts
53///
54/// Use the MIPS `wait` instruction to wait for interrupts and to put the
55/// processor in a power saving mode.
56pub fn wait() {
57    extern "C" {
58        fn mips_wait();
59    }
60    unsafe {
61        mips_wait();
62    }
63}
mips_mcu/interrupt.rs

mips_mcu/
interrupt.rs
